JP2004312039A - Photoelectric conversion device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photoelectric conversion device which suppresses the generation of defects in a semiconductor region where a depletion layer is formed. <P>SOLUTION: The photoelectric conversion device has a first conductivity-type first semiconductor region 67, a second semiconductor region 61 which is arranged on the first semiconductor region, is the first conductivity-type and is of lower impurity concentration than that of the first semiconductor region, a second conductivity-type electrode region 62 arranged in the surface of the second semiconductor region, an electrode 15 connected with the electrode region and an amplifying device M2 in a read-out circuit connected with the electrode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a photoelectric conversion element structure of an image sensor used in an image reading system such as a digital camera, an image scanner, a facsimile, a copying machine, and the like. The present invention relates to a photoelectric conversion element structure suitable for a photoelectric conversion device having a relatively large photoelectric conversion element of 10 microns or more.

  In recent years, non-CCD image sensors such as CCD image sensors and CMOS image sensors have been actively developed as photoelectric conversion devices.

  In general, a photodiode formed of a semiconductor pn junction is used as a light receiving element of these photoelectric conversion devices.

Conventional technology (1)
For example, Patent Document 1 discloses a structure in which a region having the same conductivity type as the substrate and having a higher impurity concentration than the substrate is provided on the surface of the substrate where the pn junction is not formed to reduce dark current generated on the surface of the substrate. Proposed.

29 (A) and 29 (B) show a conventional light receiving element structure according to the same publication, 201 is an n-type semiconductor substrate, 202 is a p-type semiconductor layer, and 203 is an impurity concentration of 5 × 10 ¹⁵ cm ⁻ An n-type semiconductor layer of ³ to 10 × 10 ¹⁵ cm ⁻³ and a thickness of 0.2 μm to 0.3 μm, 205 is a thermal oxide film, 208 is an n ⁺ channel stopper, and 209 is a non-reflective coating film (anti- 215, 216 are aluminum electrodes, 228 is an n ⁺ type semiconductor layer, and 238 is a back electrode. DL indicates a depletion layer, and DLS indicates a surface-side portion of the depletion layer.

  In this conventional example, since the anode of the photodiode is formed only of the p-type semiconductor layer 202, the ohmic contact with the electrode 215 is deteriorated when the concentration is reduced, and when the concentration is increased, the depletion layer DL is reduced. It does not extend into 202.

Conventional technology (2)
Further, as a light receiving element for a one-dimensional photoelectric conversion device, one having a reduced junction capacitance formed by a pn junction has been proposed as disclosed in Patent Document 2.

Figure 30 shows the upper surface of the photoelectric conversion device such as a CCD image sensor according to the prior of the publication, the p-type substrate 301, 302 is a storage unit of the n ⁺ -type, of the p-type substrate 301, n ⁺ A portion surrounded by the type accumulation unit 302 is a p-type photoelectric conversion region as a pixel. PG is a photo gate, SG is a shift gate, and SR is a CCD shift register.

In this structure, the p-type substrate 301 and the n ⁺ -type storage unit 302 generate an electric signal corresponding to an image signal as a p-type photoelectric conversion element, shift through the photo gate PG and the shift gate SG, and perform CCD shift. Image signals are sequentially read from the register SR as horizontal output lines. With this structure, although the area of the pn junction is reduced, the perimeter of the pn junction is increased, so that the capacitance value of the pn junction cannot be sufficiently reduced, and it is difficult to achieve high sensitivity.

Conventional technology (3)
Further, as a photosensitive unit structure used in a contact type image sensor, for example, as disclosed in Japanese Patent Application Laid-Open No. H11-163, there has been proposed a structure in which dark current caused by scribing of a chip end in a photosensitive unit structure is reduced. .

  FIG. 31 shows a cross section of a conventional light receiving element according to the same publication, wherein 301 is a p-type semiconductor region, 302 is an n-type semiconductor region, 303 is a p-type shallow channel stop layer, 305 is a field oxide film, and 306 is p-type. A mold substrate, 308 is a p-type channel stop layer, 309 is an interlayer insulating film, and 317 is a light shielding film for defining an opening OP. The depletion layer DL extends into the p-type semiconductor region 301, and electrons of the generated photocarriers PC are collected in the n-type semiconductor region 302 by an internal electric field.

Conventional technology (4)
As a light receiving element in a CCD image sensor, for example, as disclosed in Patent Document 4, a photodiode having a cross-sectional structure of n-type substrate / p-type region / n-type region / p-type region is generally used. ing.

FIG. 32 shows a cross section of a conventional light receiving element according to the same publication, 406 denotes an n-type substrate, 401 denotes a p-type semiconductor region, 402 denotes an n-type semiconductor region, 403 denotes a shallow p-type semiconductor layer, and 408 denotes a p ⁺ type. A channel stop, 409 is an insulating film, 415 is an electrode made of polysilicon, and 420 is an n-type region of the CCD register.

Conventional technology (5)
On the other hand, as a photoelectric conversion device using a light receiving element, for example, in Patent Document 5, a photodiode is used as a light receiving element, an electrode is attached to this light receiving element, connected to the gate electrode of a MOS transistor, and a charge is used as a source follower amplifier. There has been proposed a photoelectric conversion device that performs batch readout by using the same.
JP-A-55-154784 JP-A-61-264758 JP-A-01-303752 JP-A-64-14958 JP-A-09-205588

  However, when the photo-generated carriers are accumulated in a pn photodiode and applied to an amplification-type photoelectric conversion device that reads out a signal voltage from the pn photodiode by using a charge-to-voltage converter, the sensitivity may be reduced.

  In the case of an amplification type photoelectric conversion device, the optical output Vp is represented by the equation [1].

Vp = Qp / Cs [1]
Here, Qp is the amount of charge stored in the pn photodiode, and Cs is the capacitance of the photodiode.

For example, in the case of an amplification type photoelectric conversion device having a pixel in which a MOS source follower or a reset MOS transistor is connected to the photodiode, the capacitance Cs of the photodiode is
Cs = Cpd + Ca [2]
Can be represented.

  Here, Cpd is the pn junction capacitance of the pn photodiode itself including the light receiving unit, and Ca is another capacitance connected to the photodiode. In the above case, the gate capacitance of the MOS transistor constituting the MOS source follower and the reset MOS transistor. It includes the junction capacitance between the source and the well, the overlap capacitance between the source and the gate, the wiring capacitance, and the like.

  Therefore, in order to realize high sensitivity, it is necessary to effectively accumulate photogenerated carriers and to minimize the capacity of the photodiode in which the carriers are accumulated.

  On the other hand, when light is incident on the photodiode, charges are generated in the photodiode, and the charges generated in the depletion layer formed by the pn junction surface in the semiconductor substrate and its surroundings are collected on the anode or the cathode, and the electrode is formed there. When attached, it can be extracted as an electrical signal.

  FIG. 33 is a sectional view of a light receiving element having a conventional electrode. 701 is a first semiconductor region, and 702 is a second semiconductor region to be an anode. The respective conductivity types are n-type and p-type. DL is a depletion layer formed by a pn junction between the first semiconductor region 701 and the second semiconductor region 702. Although not shown, a reverse bias is applied between the first semiconductor region 701 and the second semiconductor region 702. Further, reference numeral 715 denotes an electrode, and the electrode 715 is connected to the second semiconductor region 702 via a contact hole CH of the insulating film 709.

  The electrode 715 is made of, for example, a metal mainly composed of Al or the like, and is connected to an electrode region formed on the main surface of the semiconductor substrate via a contact hole CH of an insulating film covering the surface of the photodiode. Generally, such a light receiving element has a configuration in which a conductive material such as Al is connected to a semiconductor region in order to obtain an optical signal by a photocarrier photoelectrically converted in the semiconductor region.

  For example, when this electrode is formed by using a general RIE (reactive ion etching) method, usually, over-etching is performed so as not to leave an unnecessary portion. At the time of this over-etching, some of the ions accelerated by the electric field penetrate the insulating film 709 and reach the main surface of the semiconductor substrate, thereby damaging the vicinity of the interface between the semiconductor and the insulating film, thereby generating crystal defects. There are cases.

  Also, in the process after the formation of the electrodes, crystal defects may occur similarly to the above due to plasma ashing of the photoresist.

  In a general light receiving element, a pn junction surface exists around the semiconductor region on the main surface of the semiconductor substrate to which the electrodes are connected, and the junction surface reaches near the interface between the main surface of the semiconductor substrate and the insulating film. There are many.

  Therefore, when the electrode is formed inside the bonding surface reaching the main surface of the semiconductor substrate, a crystal defect due to etching damage occurs near the bonding surface, and this crystal defect becomes a carrier generation center. The crystal defects generated in the depletion layer cause dark current.

  In addition, the dark current generated by this causes a change in the amount of crystal defects generated near the bonding surface or a change in the amount of crystal defects themselves due to misalignment of the mask when forming a current or the like and etching conditions. This also causes a variation in dark current.

[Object of the invention]
An object of the present invention is to provide a photoelectric conversion element in which generation of defects in a semiconductor region where a depletion layer is formed is suppressed.

  In order to solve the above problem, the photoelectric conversion element of the present invention is obtained by applying the light receiving element shown in FIG. 24 to the circuit shown in FIG.

  According to the present invention, a first semiconductor region 67 of the first conductivity type and a second semiconductor region 61 of the first conductivity type, which has a lower impurity concentration than the first semiconductor region, are disposed on the first semiconductor region. And an electrode region 62 of the second conductivity type disposed on the surface of the second semiconductor region, an electrode 15 connected to the electrode region, and an amplification element M2 of a read circuit connected to the electrode. It is characterized by the following.

  By using the photoelectric conversion device of the present embodiment to form a contact image sensor and using it as an image reading device of an image input system such as a facsimile or an image scanner, for example, a low dark current is realized, thereby achieving high quality. Since image reading can be realized and the yield is high, a low-cost image reading device can be provided.

  As described above, a photoelectric conversion element capable of reducing dark current can be obtained, and a high-performance photoelectric conversion device with less variation in dark current can be realized even when manufacturing processes vary. A high-quality image can be obtained, and a low-cost image reading device and image input system can be provided.

  An embodiment of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
Hereinafter, a first embodiment as a basic embodiment of the present invention will be described with reference to FIGS. 1 (A) to 1 (D), 2 and 3. FIG.

  1 (A) to 1 (D) are views showing the features of the present embodiment best, FIG. 1 (A) is a top view of a light receiving element portion of the present embodiment, and FIG. 1 (B) is FIG. 1A is a cross-sectional view taken along a line AA ′, FIG. 1C is a potential profile in a direction along the line XX ′ in FIG. 1B, and FIG. FIG. 6 is a potential profile diagram in a direction along a line YY ′.

  Reference numerals 1, 2, and 3 denote first semiconductor regions of the first conductivity type provided in the semiconductor substrate, second semiconductor regions of the second conductivity type provided in the first semiconductor region 1, respectively. This is a third semiconductor region of the first conductivity type provided on the main surface side of the second semiconductor region 2.

  Reference numeral 4 denotes an electrode region adjacent to the second semiconductor region 2 for extracting electric charges generated by light. Specifically, the electrode region 4 has the same conductivity type as that of the second semiconductor region 2 and has a lower impurity concentration. It is composed of a high high concentration impurity region.

  Reference numeral 102 denotes a light receiving region including the first, second, and third semiconductor regions 1, 2, 3, and 3. In the light receiving region 102, carriers generated by light incidence are captured by the region 101. Of course, if light enters the region 101, carriers are generated also in the region 101.

  In FIG. 1, the first conductivity type is shown as p-type and the second conductivity type is shown as n-type.

  If necessary, an insulating film is formed on the surface of the semiconductor substrate, an opening is formed in the insulating film, and a conductor serving as an electrode is formed in the opening.

  For example, in the light receiving region 102, carriers (in this case, electrons) generated by the photons hν move in the horizontal direction as shown in FIG. 1C, and the electrons pass through this potential groove, that is, the lowest potential region. 4 is collected in the area 101.

  In the absence of such a potential structure, the generated electrons stray in the substrate due to diffusion, and if they cannot reach the region 4 within the lifetime, they recombine with holes and disappear.

  As shown in FIG. 1D, a further feature of the present embodiment is that the third semiconductor region 3, the first semiconductor region 1, and the second semiconductor region 3 on the surface are depleted so that the second semiconductor region 2 is almost completely depleted. The point is that the impurity concentration and the junction depth of the region 2 and the potential applied to the electrode region 4 and the region 1 are set. As a result, the second semiconductor region 2 hardly contributes as a capacity, and the capacity of the light receiving section can be reduced.

  That is, electrons generated near the junction interface between the regions 2 and 3 are collected in the region 2 by the built-in potential due to the pn junction. On the other hand, electrons generated near the junction interface between the regions 2 and 3 are collected in the region 2 by a built-in potential due to the pn junction. Here, since the region 2 of the light receiving region 102 is almost depleted by the two pn junctions, there is no neutral region. Such a state will be referred to as complete depletion. Then, the collected electrons are collected in the region 4 as described above and output from an electrode (not shown).

  FIG. 2 shows the distribution of the impurity concentration in the direction along the line YY '. In FIG. 2, Np1 indicates a p-type impurity concentration such as boron (B) in a p-type semiconductor substrate serving as a starting material of the region 1, and Nn1 indicates a phosphorus or arsenic introduced for forming the region 2. Np2 indicates a p-type impurity concentration introduced for forming the region 3.

  Nc indicates the net impurity concentration (net value) of each region.

The impurity concentration and thickness in each region can be selected from the following ranges. As a parameter of the thickness, a junction depth from the substrate surface is shown. The first semiconductor region 1 has an impurity concentration ND1 of 10 ¹⁴ cm ⁻³ to 10 ¹⁷ cm ⁻³ , more preferably 10 ¹⁵ cm ⁻³ to 10 ¹⁶ cm ⁻³ , and a junction depth of 0.1 μm to 1000 μm. It is.

The impurity concentration ND2 of the second semiconductor region 2 is 10 ¹⁵ cm ⁻³ to 10 ¹⁸ cm ⁻³ , more preferably 10 ¹⁶ cm ⁻³ to 10 ¹⁷ cm ⁻³ , and the junction depth is 0.2 μm to 2 μm. .

The impurity concentration ND3 of the semiconductor region 3 is 10 ¹⁶ cm ⁻³ to 10 ¹⁹ cm ⁻³ , more preferably 10 ¹⁷ cm ⁻³ to 10 ¹⁸ cm ⁻³ , and the junction depth is 0.1 μm to 0.5 μm. .

The impurity concentration ND4 of the electrode region 4 is 10 ¹⁸ cm ⁻³ to 10 ²¹ cm ⁻³ , more preferably 10 ¹⁹ cm ⁻³ to 10 ²⁰ cm ⁻³ , and the junction depth is 0.1 μm to 0.3 μm. is there.

  The impurity concentration ND2 of the second semiconductor region 2 is higher than the impurity concentration ND1 of the first semiconductor region 1, and the impurity concentration ND3 of the third semiconductor region 3 is higher than the impurity concentration ND2 of the second semiconductor region 2. It is good to decide.

  For more detailed description, FIG. 3 is a graph showing the relationship between the voltage of the electrode region 4 and the capacitance at that time. Although the capacity decreases as the voltage increases, the capacity of the region 4 becomes constant at the point A.

  When the voltage is low, region 2 is not depleted, and the capacitance changes depending on the depletion layer capacitance between region 2 and region 3 and the depletion layer capacitance between region 2 and region 1. . That is, as the voltage of the region 4 increases, the depletion layer expands, and thus the capacitance gradually decreases. However, when the upper and lower depletion layers are connected, the region 2 in the light receiving region 102 is almost completely depleted, and the capacitance is reduced. It decreases sharply and then stabilizes. The transition point is point A in the figure, and the voltage at point A is hereinafter referred to as a depletion voltage.

Since the depletion voltage is determined depending on the thickness of each of the regions 1, 2, 3 and the impurity concentration,
(A) the potential of the electrode region 4 when the light receiving element is reset,
(B) By setting the voltage of the electrode region 4 where the light output of the light receiving element is saturated to be equal to or higher than the depletion voltage, the capacitance of the photodiode itself is substantially reduced to about the junction capacitance C0 at the bottom of the reference numeral 101. It is possible to achieve a high sensitivity.

  Here, the electric potential of the electrode changes due to the accumulation of the charges generated by the light in the electrode region, but the operating point (the range in which the electric potential changes) is designed to be equal to or higher than the depletion voltage. Since the capacitance of No. 4 has linearity, it is possible to obtain a photoelectric conversion characteristic with high sensitivity and good linearity.

  Further, when the voltage decreases at the boundary of the depletion voltage, the capacitance value increases exponentially from C0 to a capacitance value determined by the area of the region 2.

For example, the thickness of the region 1 is about 600 μm, the impurity concentration is 1 × 10 ¹⁶ cm ⁻³ , the junction depth of the region 2 is 0.5 μm, and the impurity concentration is 1 × 10 ¹⁷ cm ^−3. The junction depth of the region 3 is 0.2 μm, the impurity concentration is 1 × 10 ¹⁸ cm ⁻³ , the junction depth of the region 4 is 0.2 μm, the impurity concentration is 1 × 10 ¹⁹ cm ⁻³ , The capacity ratio of the photodiode when the area 4 is not depleted is about 4400 times as compared with the capacity of the photodiode when the area is 80 μm × 80 μm and the area of the upper surface of the area 4 is 1.2 μm × 1.2 μm. .

  If there is no potential profile as shown in FIG. 1 (C), electrons generated in the vicinity of the electrode region 4 can easily reach there, but electrons generated at the end of the light receiving surface are located in the electrode region about 40 μm apart. The probability of reaching is very low, resulting in a significant loss of sensitivity.

  On the other hand, in the structure of the present embodiment, at least electrons generated within about 1 μm from the surface can be collected almost anywhere in the light receiving surface. In particular, since most of the blue light is absorbed within 1 μm of the silicon surface, the sensitivity of blue, which is a problem in the visible light sensor, is improved.

  In addition, by using a technique such as high-energy ion implantation, a retrograde well structure having a peak value of the impurity concentration inside the substrate is used, or conversely, the concentration of the substrate 1 is reduced and the depletion layer is expanded. It is also possible to collect electrons generated at a deep place.

  Furthermore, by forming a high-concentration impurity layer on the substrate surface, providing a low-impurity-concentration epitaxial layer thereon, and applying the present invention, it is possible to obtain a light-receiving portion structure with high long-wavelength sensitivity.

FIG. 4 shows an example of a read and reset circuit used in the present invention. In FIG. 4, D1 is a photodiode formed of a light receiving element according to the present invention, M1 is a reset switch formed of a MOS transistor or the like, M2 is an amplification element formed of a MOS transistor or the like, and M3 is a load formed of a MOS transistor or the like. It can also be used. Also, VR is a reset line or a reset terminal providing a reference voltage for reset, VDD is the power supply voltage line or the power supply voltage terminal gives a supply voltage, phi _R is reset control line for turning on / off the reset switch M1, V _OUT is an output terminal.

The operation of the read and reset circuit of FIG. 4 will be described. After the reset switch M1 is turned on and the cathode (region 4 in FIG. 1A) is given a reset reference voltage equal to or higher than the depletion voltage to the reset control line φ _R to reset the floating gate of the amplifier M2, When the reset switch M1 is turned off, the accumulation of optical carriers starts, and the potential of the input terminal of the amplification element M2 changes. After a predetermined accumulation time has elapsed, if on the selection switch M3 to input-pulse to the selected line phi _S, a current flows in accordance with the optical carrier through a source follower circuit having the transistors M2, M3, an output signal is obtained .

(Embodiment 2)
FIG. 5A is a top view of the light receiving element according to the present embodiment, and FIG. 5B is a cross-sectional view taken along line BB ′ of FIG. 5A.

  In FIG. 5, reference numeral 11 denotes a first semiconductor region of a first conductivity type (here, n type), 12 denotes a second semiconductor region of a second conductivity type (here, p type), and 13 denotes a third semiconductor region of the first conductivity type. The semiconductor region 14 is an electrode region of the second conductivity type having a high impurity concentration.

  In this embodiment, an element isolation region (isolation region) 5 formed by a selective oxidation method called LOCOS or the like for isolating the light receiving element is formed.

Next, the method for manufacturing the light receiving element according to the present embodiment will be explained. An element isolation region 5 made of silicon oxide SiO ₂ is formed by a selective oxidation method in which a silicon nitride film SiN (not shown) is formed as an oxidation-resistant mask and a thick oxide film is formed in a portion exposed from the mask (FIG. 6A). ). Such a method is known as LOCOS.

  Next, a photoresist mask (not shown) is formed, ion implantation is performed, and heat treatment is performed to form a p-type second semiconductor region 12 in the first semiconductor region 11 made of an n-type semiconductor substrate. The depletion layer formed by the pn junction is prevented from reaching the edge 104 by separating the edge 103 of the second semiconductor region 12 from the edge 104 of the element isolation region 5 where many defects exist. Thus, generation of dark current due to defects can be suppressed (FIG. 6B).

  Next, an n-type third semiconductor region 13 is formed on the surface of the substrate by forming a photoresist mask (not shown) and performing ion implantation, removing the photoresist mask and performing heat treatment (FIG. 6C )).

  Then, a photoresist mask (not shown) is formed, ions are implanted, and heat treatment is performed after the removal of the photoresist mask to form the p-type electrode region 14, whereby the structure shown in FIG. 5B is obtained.

  Thereafter, if necessary, an insulating film covering the surface is formed, a contact hole is opened, and the electrode region 14 may be connected to a read and reset circuit formed in another place of the same semiconductor substrate through a wiring.

  In this embodiment, since a signal is output from the anode of the photodiode, the configuration of the read and reset circuit used therein is also reversed in the relationship between the potential level and the conductivity type.

FIG. 7 is a circuit diagram of another read and reset circuit used in the present invention. In FIG. 7, D1 is a photodiode comprising the light receiving element of the present invention, M2 and M3 are an amplifying element and a selection element, respectively, and a source which is an amplifier for converting a photoelectric charge generated by the photodiode D1 into a charge voltage and reading it out. Constitutes a follower. The selection of the pixel was performed by turning on / off the switch M3 which is also a low current source of the source follower. After reading out the photoelectric charge information of the pixel with the selection switch M3, the photodiode D1 was reset by the reset switch M1. The reset voltage (φ _R -Vth), as a reverse voltage of more than the depletion voltage is applied to the anode of the photodiode, and sets the reset voltage. Here, Vth is a threshold value of the reset switch M1. The outputs of the amplification element M2 and the selection element M3 having the source follower configuration are output via the buffer B1, the coupling capacitor C for cutting off the DC component, and the buffer B2 by shifting the ON time of the selection element. .

  For example, since the depletion voltage was 1.0 volt in the reverse bias voltage of the photodiode D1, the reset voltage was set to be applied 3 volts in the reverse bias voltage. That is, when the power supply voltage applied to the terminal VDD was used at 5 volts, the voltage applied to the reset terminal VR was set to 2.0 volts, and the read operation was performed.

  In the present embodiment, when the size of the light receiving surface is 40 μm × 40 μm and the size of the upper surface of the electrode region 14 is 6 μm × 6 μm, the capacitance of the photodiode is 3.8 fF, which is considerably lower than the conventional one, and high photoelectric conversion. Sensitivity could be obtained.

  In the present embodiment, image information in the region in front of the light receiving surface can be obtained, and a high-definition image can be obtained.

  In particular, the present embodiment is effective in the case of a light receiving element having a large light receiving surface such that light collection efficiency is deteriorated. When the size of the light receiving surface is 20 μm square or more, the collection efficiency starts to deteriorate.

(Embodiment 3)
FIG. 8A shows an upper surface of a light receiving element according to Embodiment 3 of the present invention, and FIG. 8B shows a cross section taken along line CC ′ of FIG. 8A.

  The difference from the embodiment shown in FIGS. 5A and 5B is that the second semiconductor region is composed of two regions having different impurity concentrations from each other. In FIG. 8, the internal region 22 in contact with the electrode region 14 has a higher impurity concentration than the external region 12 and has a lower impurity concentration than the electrode region 14. The junction depth of the inner region 22 may be shallower or deeper than the outer region 12.

  FIG. 9 shows a potential profile in a direction along the line CC ′ of FIG. 8A. A potential gradient steeper than that in FIG. 1C is formed by the inner region 22 and the outer region 12 having different impurity concentrations. In this way, the charges generated at the end of the light receiving surface can be easily collected on the electrode region 14, and the optical signal reading time can be shortened.

  Next, the method for manufacturing the light receiving element according to the present embodiment will be explained with reference to FIG. An element isolation region 5 made of silicon oxide is formed on the n-type semiconductor substrate 11 by a selective oxidation method in which a silicon nitride film (not shown) is formed as an oxidation-resistant mask and a thick oxide film is formed in a portion exposed from the mask (FIG. FIG. 10 (A)).

  A p-type second semiconductor region 12 is formed in the first semiconductor region 11 formed of an n-type semiconductor substrate by forming a photoresist mask (not shown), performing ion implantation, and performing heat treatment. The depletion layer formed by the pn junction is prevented from reaching the edge 104 by separating the edge 103 of the second semiconductor region 12 from the edge 104 of the element isolation region 5 where many defects exist.

  Thus, generation of dark current due to defects can be suppressed. Then, a photoresist mask (not shown) is formed, and an internal region 22 having a high impurity concentration is formed by ion implantation and heat treatment (FIG. 10B).

Next, an n ⁺ -type third semiconductor region 13 is formed by ion implantation and heat treatment (FIG. 10C).

Then, when the p ⁺ -type electrode region 14 is formed by ion implantation and heat treatment, the structure of FIG. 8B is obtained.

  Thereafter, if necessary, a transparent insulating film covering the surface is formed, an opening is formed in the insulating film, and a read and reset circuit formed in another place of the same semiconductor substrate is connected to the electrode region 14 through wiring. Should be connected.

  As described above, the same circuit as that shown in FIG. 7 can be employed as the readout circuit and the reset circuit according to the present embodiment.

(Embodiment 4)
FIG. 11A shows the top surface of the light receiving element according to the present embodiment, and FIG. 11B shows a cross section taken along line DD ′ of FIG. 11A.

The difference from the embodiments shown in FIGS. 5A and 5B is that an n-type epitaxial layer 21 formed on the surface of a p-type semiconductor substrate 6 by epitaxial growth is used as a first semiconductor region. After forming the n-type epitaxial layer 21, the p-type second semiconductor region 12 is formed by ion implantation or the like, and further, the n ⁺ -type third semiconductor region 13 is formed by ion implantation and heat treatment. Then, a p ⁺ -type electrode region 14 is formed by ion implantation and heat treatment.

  In the present embodiment, instead of forming the n-type epitaxial layer 21, an n-type well formed by ion implantation and heat treatment in a p-type semiconductor substrate can be used.

  According to the present embodiment, it is possible to prevent charges generated at a deep position of the p-type substrate from reaching the p-type second semiconductor region 12.

  Specifically, if the thickness of the well is, for example, about 4 μm, most of the holes generated at a depth of about 4 μm away from the surface of the light receiving element flow into the p-type substrate, so that the dark current is not generated. Can be suppressed.

  In the case of the structure shown in FIGS. 5A and 5B, noise generated when driving the reset circuit or the readout circuit easily enters the second semiconductor region. On the other hand, by forming the second semiconductor region in a well formed individually or commonly for all pixels as in the present embodiment, the entry of the noise can be suppressed.

(Embodiment 5)
12 shows a top view of the light receiving element according to the fifth embodiment, FIG. 13 shows a cross section taken along line EE 'in FIG. 12, and FIG. 14 shows a cross section taken along line FF' in FIG. Is shown.

In FIG. 12, a p-type second semiconductor region 32 constituting a photodiode serving as a light receiving element is formed in an opening OP, and a p-type internal region 22 is formed in this region 32. Further, a p ⁺ electrode region 34 is formed in the internal region 22. The electrode region 34 is formed by a drain portion of a MOS transistor M1 serving as a reset switch and a gate portion of a source follower MOS transistor M2 serving as an amplifying element. Are electrically connected by a wiring 15 formed of the first metal layer. The opening OP of the light receiving element is defined by a light shielding layer 17 formed of a second metal layer, and the light shielding layer 17 is connected to a power supply and fixed at a predetermined reference potential.

Here, the p ⁺ -type electrode region 34 is arranged closer to the direction in which the drain portion of the reset MOS transistor M1 and the source follower MOS transistor M2 are arranged than the center of the opening. On the side opposite to 34, a power supply line 16 for determining the potential of the n-type well region 31 as the first semiconductor region is provided. In the figure, the size of the opening OP is 40 μm × 60 μm.

  13 and 14, the second semiconductor region 32 is formed in the opening OP of the n-type well region 31 provided in the p-type semiconductor substrate 6, and the internal region 22 is further formed in the second semiconductor region 32. It can be seen that the electrode region 34 is formed in the inner region 22 in an island shape.

  On the main surfaces of the second semiconductor region 32 and the internal region 22, an n-type surface region 33 is provided as a third semiconductor region, and is electrically connected to the n-type well region 31 at an end of the opening OP. .

Therefore, a photodiode is formed by the pn junction between the second semiconductor region 32 and the internal region 22 made of the p-type semiconductor and the first and third semiconductor regions 31 and 33 made of the n-type semiconductor, and the photodiode is photoelectrically converted by the photodiode. The photocarriers are collected in the electrode region 34 made of the p ⁺ type semiconductor, and change the potential of the wiring 15 formed of the first metal layer.

  Further, a protective film 18 is provided on the electrode region 34 and on the light shielding layer 17 formed of the second metal layer.

Here, as shown in FIG. 12, the p ⁺ type region 34 is disposed on the side where the reset MOS transistor M1 and the source follower MOS transistor M2 are disposed, that is, on the right side in FIG. 14 than the center of the opening OP. On the other hand, the contact of the power supply line 16 for supplying a voltage to the n-type well region 31 is arranged only on the opposite side of the p ⁺ -type region (1511).

  Here, the n-type well region 31 is formed in the p-type substrate 6 and is surrounded by a p-type well region 7 serving as an element isolation region for each pixel, and is electrically connected to each pixel by a pn junction. The structure is separated into

  In FIG. 13 and FIG. 14, representative values of the approximate surface concentration and the junction depth of each region are shown below.

p-type substrate 6: about 1 × 10 ¹⁵ (cm ⁻³ )
First semiconductor region 31: about 1 × 10 ¹⁷ (cm ⁻³ ) / about 4.0 μm
Second semiconductor region 32: about 2 × 10 ¹⁷ (cm ⁻³ ) / about 0.35 μm
Internal area 22: about 3 × 10 ¹⁷ (cm ⁻³ ) / about 0.30 μm
Third semiconductor region 33: about 3 × 10 ¹⁸ (cm ⁻³ ) / about 0.20 μm
Electrode area 34: about 3 × 10 ¹⁹ (cm ⁻³ )
In this embodiment, the depletion voltage of each of the region 32 and the region 22 is:
Area 32: about -1.0 V
Region 22: about -1.5V
It has become.

  Therefore, since the depletion voltage of the regions 32 and 22 increases toward the electrode region 34, a potential gradient of the photocarrier is formed, and the photocarrier can be more efficiently collected at the electrode region 34. It becomes.

  In the present embodiment, since the photomask (reticle) for exposure is formed such that the corners of the region 32 and the region 22 are all obtuse, potential grooves are formed due to non-uniform electric fields at the corners. And the afterimage characteristics are improved. Furthermore, since the region 31 is formed in the p-type substrate 6 and has a structure in which the periphery is surrounded by the p-type well region 7 for each pixel, crosstalk generated by mixing of optical carriers into adjacent pixels is generated. Can be almost completely suppressed, and a high-quality resolution pattern can be obtained.

  Further, even if the photo carriers that are saturated or more are accumulated in a certain pixel, the overflowing photo carriers are absorbed by the surrounding p-type well region 7 and the substrate 6, so that the bleeding is not affected on other pixels. A few high-quality images can be obtained.

  In the present embodiment, the region 32 and the region 22 are illustrated as regions where the photodiode is formed. For example, the second p-type internal region including the electrode region 34 inside the internal region 22 is illustrated. Are formed, and the depletion voltage in the second internal region is set to an impurity concentration and a junction depth that are higher than the depletion voltage in the internal region 22, thereby forming a light receiving element having further lower image lag characteristics. It is also possible.

(Embodiment 6)
15 shows a top view of a light receiving element according to the sixth embodiment, FIG. 16 shows a cross section taken along line GG ′ in FIG. 15, and FIG. 17 shows a cross section taken along line HH ′ in FIG. Is shown.

  This embodiment differs from the embodiments shown in FIGS. 12 to 14 in that the planar shape of the internal region 22 made of a p-type semiconductor is changed so as to have a portion whose width gradually changes.

  In addition, a portion 22A whose width narrows downward in the drawing extends downward from above in the drawing beyond the center of the light receiving surface (opening).

  Reference numeral 8 shown in FIG. 17 is a contact region having a high impurity concentration, and serves as a cathode contact of the power supply line 16.

  15 to 17, a second semiconductor region of a photodiode serving as a light receiving element is formed in an opening OP, and an internal region 22 is formed in this region 32. Further, an electrode region 34 is formed in the internal region 22, and this region 34 is formed of a wiring formed of a first metal layer at the drain of the reset MOS transistor M1 and the gate of the source follower MOS transistor M3. 15 are electrically connected. The opening OP of the light receiving element is defined by a light shielding layer 17 formed of a second metal layer, and the light shielding layer 17 is connected to a power supply and fixed at a desired potential.

  Here, the electrode region 34 is arranged so as to be closer to the direction in which the drain portion of the reset MOS transistor M1 and the source follower MOS transistor M2 are arranged than the center of the opening, and the opening opposite to the electrode region 34. A power line 16 for supplying reverse bias electric power to the n-type well region 31 as the first semiconductor region is provided on the side of the unit. In the figure, the size of the opening OP is 40 μm × 60 μm.

  An n-type surface region 33 as a third semiconductor region is provided on the main surfaces of the region 32 and the region 22, and is electrically connected to the n-type well region 31.

  Therefore, a photodiode is formed by a pn junction between the p-type region 32 and the region 22 and the n-type region 31 and the region 33, and the photocarriers photoelectrically converted by the photodiode are collected in the region 34 and the potential of the wiring 15 is reduced. Change it.

  Further, a protective film 17 is provided on the light-shielding layer 17 formed of the second metal layer.

  Here, the electrode region 34 is arranged on the side where the reset MOS transistor M1 and the source follower MOS transistor M2 are arranged, that is, on the right side in FIG. 17 with respect to the center of the opening. The contact of the power supply line 16 for supplying the potential is arranged only on the side opposite to the electrode region 34 (the left side in FIG. 17).

  Here, the n-type well region 31 is formed in the p-type substrate 6, and is surrounded by the p-type well region 7 for each pixel, and has a structure electrically isolated for each pixel. I have.

  Further, the inner region 22 has a shape whose width gradually increases from W1 to W2 (W2> W1) toward the electrode region 34, and the corners of the upper surfaces of the region 32 and the region 22 are all It has a shape consisting of an obtuse angle greater than 90 degrees.

  In FIGS. 16 and 17, representative values of approximate surface concentration / junction depth in each region are shown below.

p-type substrate 6: about 1 × 10 ¹⁵ (cm ⁻³ )
Area 31: about 1 × 10 ¹⁷ (cm ⁻³ ) / about 4.0 μm
Area 32: about 2 × 10 ¹⁷ (cm ⁻³ ) / about 0.35 μm
Area 22: about 3 × 10 ¹⁷ (cm ⁻³ ) / about 0.30 μm
Area 33: about 3 × 10 ¹⁸ (cm ⁻³ ) / about 0.20 μm
Area 34: about 3 × 10 ¹⁹ (cm ⁻³ )
In this embodiment, the depletion voltage of each of the region 32 and the region 22 is:
Area 32: about -1.0 V
Region 22: about -1.5V
It has become.

  Therefore, since the depletion voltage in the regions 32 and 22 increases toward the electrode region 34, a potential gradient of the photocarrier is formed, and the photocarrier can be more efficiently collected in the region 54. .

Further, since the power supply line 16 for supplying a voltage for fixing the potential of the n-type well region 31, which is the first semiconductor region, is provided on the opposite side of the region 34, the photocurrent generated by the photo-generated electrons becomes n-type. By flowing in the well region 31 toward the contact region 8, a potential gradient is generated from the contact region 8 toward the region 34, so that photogenerated holes can be more efficiently collected in the p ⁺ -type region 511. The afterimage characteristics are improved.

  In addition, in the present embodiment, since the region 22 has a portion whose width increases toward the region 34, the light generation holes reaching the tip of the region 22 due to the potential gradient flow toward the region 34. In this case, since the sheet resistance of the region 22 gradually decreases with respect to the photocurrent generated by the light generation holes, the light generation holes can be collected in the region 34 at high speed, and the afterimage characteristics during high-speed operation are improved. I do.

  Further, since the tip of the region 22 is arranged beyond the center of the opening OP, the efficiency of collecting holes on the contact region 8 side is improved.

  Further, since the corners of the region 32 and the region 22 are all formed with obtuse angles, a potential groove due to non-uniform electric field at the corner portion is less likely to be formed, and the afterimage characteristics are further improved. Such a shape can be easily formed by a pattern of a photomask used when exposing the photoresist.

  Furthermore, since the region 31 is formed in the p-type substrate 6 and has a structure in which the periphery is surrounded by the p-type well region 7 for each pixel, crosstalk generated by mixing of optical carriers into adjacent pixels is generated. Can be suppressed almost completely, and a high-quality resolution pattern can be obtained.

  Further, even if a high carrier exceeding saturation is accumulated in a certain pixel, the overflowing optical carrier is absorbed by the surrounding region 7 and the substrate 6, so that it does not affect the other pixels and has a low blur and high quality. Pixel can be obtained.

  In the present embodiment, the region 32 and the region 22 are illustrated as regions for forming the photodiode. For example, a second internal region 22 that further includes the region 34 inside the internal region 22 is provided. By setting the depletion voltage in the second internal region to an impurity concentration and a junction depth higher than the depletion voltage in the internal region 22, a light receiving element having further lower image lag characteristics is formed. Is also possible.

(Embodiment 7)
FIG. 18 is a top view of the light receiving element according to the present embodiment, and FIG. 19 is a cross-sectional view taken along line II ′ of FIG.

  The feature of the light receiving element of the seventh embodiment is that a doped region 43 having a low impurity concentration is formed in an offset region between the electrode region 34 and the semiconductor region 33.

18 and 19, a p-type region as a second semiconductor region 32 of a photodiode serving as a light receiving element is formed in an opening OP, and a p-type region as an electrode region 34 formed in the p-type region 32 of the photodiode is formed. ^{The +} type region is electrically connected to the drain of the reset MOS transistor M1 and the gate of the source follower MOS transistor M2 by a wiring 15 formed of a first metal layer. The opening OP of the light receiving element is defined by a light shielding layer 17 formed of a second metal layer, and the light shielding layer 17 is connected to a power supply and fixed at a desired potential. Here, the size of the opening OP is 40 μm × 40 μm.

A p-type region 32 is formed in an opening OP of an n-type well region 31 provided in a p-type semiconductor substrate 6, and a p ⁺ -type region 34 is provided in the p-type region 32 in an island shape.

  Further, an n-type surface region 33 as a third semiconductor region is provided on the main surface of the p-type region 34, and is electrically connected to the n-type well region 31.

Here, the n-type surface region 33 is arranged so as to have an offset (interval) of about 2 μm so as not to directly contact the p ⁺ -type region 34, and further, the second n-type surface region is provided on the entire surface of the light receiving element including this offset region. A region 43 is formed.

Therefore, a photodiode is formed by a pn junction between the p-type region 32 and the n-type regions 31, 33, and 43. Photocarriers photoelectrically converted by the photodiode are collected in the p ⁺ -type electrode region 34, and the first The potential of the wiring 15 formed of the metal layer is changed.

  Further, an interlayer insulating film 9 is provided between the semiconductor surface and the first metal layer and between the first metal layer and the second metal layer, and a light-shielding layer formed by the second metal layer A protective film 18 is provided on the upper part of 17.

  In FIG. 19, the approximate surface concentration / junction depth of each region is shown below.

p-type substrate 6: about 1 × 10 ¹⁵ (cm ⁻³ )
n-type well region 31: about 1 × 10 ¹⁷ (cm ⁻³ ) / about 4.0 μm
P-type region 32: about 2 × 10 ¹⁷ (cm ⁻³ ) / about 0.35 μm
First n-type surface region 33: about 3 × 10 ¹⁸ (cm ⁻³ ) / about 0.20 μm
Second n-type surface area 43: about 3 × 10 ¹⁷ (cm ⁻³ ) / about 0.1 μm
p ⁺ type region 34: about 3 × 10 ¹⁹ (cm ⁻³ )
Therefore, if there is no second n-type surface region 43, the vicinity of the surface of the offset region becomes a p-type region having an impurity concentration of 10 ¹⁷ cm ⁻³ or less. Further, since the boron concentration near the semiconductor surface is liable to fluctuate depending on the manufacturing process, carriers generated in this offset region cause dark current and dark current variation.

On the other hand, when the p ⁺ -type region 34 and the first n-type surface region 33 are brought into contact with each other so as not to form the offset region, a reverse bias between the p ⁺ -type region 34 and the first n-type surface region 33 causes Breakdown is likely to occur.

On the other hand, by setting the surface concentration of the second n-type surface region 43 to about 10 ¹⁷ to 10 ¹⁸ cm ⁻³ , the distance between the p ⁺ -type region 34 and the first n-type No problem such as breakdown occurs even when a reverse bias is applied.

If the offset region is too small, the probability that the p ⁺ -type region 511 and the first n-type surface region 520 come into contact with each other due to misalignment in photolithography or the like increases, and the yield decreases.

Therefore, the n-type semiconductor as the low-doped region 43 has a concentration near the surface of the offset region of about 10 ¹⁷ cm ^−3, so that generation of carriers in the offset region can be suppressed. For example, even if this second n-type surface region 43 is formed over the entire light receiving portion by ion implantation, the impurity concentration is sufficiently low with respect to the first n-type surface region 33 and the p ⁺ -type region 34. Have little effect on these areas. As described above, since there is no problem such as misalignment in photolithography, it is possible to selectively control the surface concentration of the offset region and reduce the dark current.

  According to the findings of the present inventor, as a result of measuring the dark current, the dark current is reduced to 場合 when the second n-type surface region 43 is present, as compared with the case where the second n-type surface region 43 is not present.

Here, the depletion voltage of the semiconductor region 32 in the present embodiment was about -2V. Therefore, for example, when the n-type well region 31 is connected to the power supply voltage in the operation at the power supply voltage of 5 V, if the potentials of the p ⁺ -type region 34 and the wiring 15 are 3 V or less, the p-type region 32 is depleted. The neutral region disappears.

  The above-described depletion voltage changes sensitively mainly with respect to the impurity concentration and the junction depth of each of the n-type well region 31, the p-type region 32, and the first n-type surface region 33. Therefore, the manufacturing variation of the depletion voltage is relatively large, for example, about ± 1.0 V at ± 3σ, but by setting the depletion voltage and the operating point to appropriate regions, the depletion voltage can be reduced. A high yield can be maintained even if there is variation.

In the present embodiment, the n-type surface region 43 is provided in order to suppress the generation of carriers on the surface of the offset region. However, the present invention is not limited to the n-type. Current suppression can be realized. In this case, the neutral region of the p-type increases, but the p-type may be used when the capacity of the light-receiving unit has a margin by design. In any case, from the viewpoint of reducing dark current and preventing breakdown, the impurity concentration in the offset region is about 10 ¹⁶ to 10 ¹⁸ cm ⁻³ , and more preferably 5 × 10 ^{16 to} 5 × 10 ¹⁷ cm ^−3. It is.

  The n-type well effect 31 is formed in the p-type substrate 6 and has a structure in which the periphery is surrounded by the p-type well region 7 for each pixel.

  Next, the method for manufacturing the light receiving element according to the present embodiment will be described with reference to FIGS.

  An n-type well region 31 and a p-type region 7 are formed on the surface side of the p-type semiconductor substrate 6.

  The field insulating film 5 is formed by selective oxidation. After a P-type semiconductor region 32 serving as a photodiode is formed inside a region surrounded by the field insulating film 5, an n-type semiconductor region 33 is formed on the surface thereof.

  Ion implantation is performed on the substrate surface to form an n-type semiconductor layer 43. Then, a p-type electrode region 34 is formed.

  The distance between the electrode region 34 and the semiconductor region 33 (the width of the offset region) is 0.4 μm to 1.5 μm, and more preferably 0.5 μm to 1.0 μm. And the concentration is lower by at least one order of magnitude than the electrode region 34 and is higher than that of the semiconductor region 32.

  Next, another embodiment of the read and reset circuit used in the present invention will be described again with reference to FIGS.

  FIG. 21 is a circuit diagram of the circuit according to the present embodiment.

  In FIG. 21, D1 is a photodiode as a light receiving element according to each embodiment of the present invention, M2 is a PMOS transistor of an amplifying element, and forms a source follower with a constant current source via a selection switch M3. . M1 is a reset switch, and M3 is a selection switch. M4 is a transfer switch for transferring a photoelectric signal from a photodiode to an input terminal of a source follower.

  The optical signal and the reset signal read from the source follower are respectively transferred to the memory unit ME, and are output to the outside via the buffer B1, the coupling capacitor C, and the buffer B2 via the read scanning circuit RE and the like.

  According to the present embodiment, in particular, as a result of suppressing the area of the electrode to 1 μm square, the junction capacitance can be suppressed to 0.1 fF. As a result, reset noise can be suppressed to about four electrons, and a solid-state imaging device having no afterimage even with a dynamic range of 10 bits can be provided with a high yield.

  Next, another read and reset circuit used in the present invention will be described. This circuit is disclosed in JP-A-09-205588.

  FIG. 22 is an equivalent circuit diagram of one pixel of the circuit described in the above publication.

  In FIG. 22, here, for each pixel, a light receiving element D1, a reset MOS switch M1 for resetting the light receiving element D1, a first MOS source follower M2 for converting a signal charge of the light receiving element D1 into a voltage signal, and a light receiving element D1 A MOS switch M3 for holding the noise signal at the time of reset during the accumulation period, a holding capacitor 605, a second MOS source follower M4 for converting the signal of the holding capacitor 605 into an impedance, and a MOS for reading the noise signal charge immediately after the reset. The switch 607 includes a switch 607, a noise signal holding capacitor 609, a MOS switch 608 for reading an optical signal charge after storing an optical signal, and a light signal holding capacitor 610.

  Further, this circuit includes a shift for sequentially reading out the noise signal of the noise signal holding capacitor 609 and the optical signal of the optical signal holding capacitor 610 to the noise signal common output line 690 and the optical signal common output line 691, respectively. A register 613, buffer amplifiers 614 and 614 'for converting the voltages of the noise signal common output line 690 and the optical signal common output line 691 into impedances, and the noise signal common output line 690 and the optical signal common output line 691 A differential amplifier 615 for obtaining a voltage difference signal and amplifying the signal, and an output buffer amplifier 692 for impedance-converting the output of the differential amplifier 615 and outputting a signal to the outside of the photoelectric conversion device. Is provided. A common output line reset unit 693 for resetting the noise signal common output line 690 and the optical signal common output line 691 every time one pixel is read is also provided.

  The light output voltage VP of the photoelectric conversion device shown in FIG. 22 is represented by the following [Equation 1].

[Equation 1]
Vp = [QP / Cpd] ・ Gsf1 ・ Gsf2 ・ [CT / (CT + CH)] ・ Gamp
here,
QP: optical signal charge CPD: light receiving portion capacitance Gsf1: gain of first source follower M2 Gsf2: gain of second source follower M4 CT: capacitance value of noise signal and optical signal storage capacitance CH: noise signal and optical signal common output line capacitance Gamp: the gain of the differential amplifier 615.

In FIG.
V1PD: the potential of the light receiving element immediately after resetting the light receiving element,
V2PD: potential of light receiving element after photocharge accumulation,
Then, the above equation can be represented as the equation of [Equation 2].

[Equation 2]
V2PD-V1PD = ΔVPD = [QP / Cpd] = [Vp / [Gsf1, Gsf2, [CT / (CT + CH)], Gamp]]
Here, ΔVPD is a change in potential of the light receiving element due to photocharge.

Therefore, by setting V1PD and V2PD in the depletion region in the light receiving element in the above formula, a highly sensitive photoelectric conversion device can be realized.

In this embodiment, in each of the above equations,
Gsf1 = Gsf2 = 0.9
CT / (CT + CH) = 0.5
Gamp = 20
Power supply voltage (VDD): 5V
Depletion voltage of light receiving element: -2V
Saturation output of light output (Vp): 2V
The reset voltage of the light receiving element (V _R): 1V
Was set.

Therefore, according to the above equations,
(A) Potential (V1PD) of light receiving element immediately after reset: about 0.70 V
(B) Potential (V2PD) of light receiving element at the time of saturation output: about 0.95V
It becomes.

  From the values of the power supply voltage and the depletion voltage, it is understood that the light-receiving element portion is in a depleted state if the potential of the light-receiving element portion is 3 V or less.

  From (a) and (b) in the above equations, the potential (V1PD) of the light-receiving element immediately after reset and the potential (V2PD) of the light-receiving element at the time of saturation output are both 3 V or less. It can be used in a small range and has high sensitivity.

  Incidentally, as a result of measuring the capacitance of the light receiving portion, it was found that the total of the parasitic capacitance such as the junction capacitance of the electrode region of the light receiving element, the gate capacitance of the source follower MOS, the junction capacitance of the drain of the reset MOS, the wiring capacitance, etc. It was 25 fF.

  Further, in the present embodiment, when the variation of the depletion voltage is about −2 V ± 2 V, the depletion region of the light receiving element portion is 1 V to 5 V, but the operating point in this embodiment is the minimum value of the depletion region. Since it is smaller than 1 V, a high yield can be maintained even if the depletion voltage varies by about ± 2 V.

  Note that the reason why the potential of the light receiving element portion immediately after the reset is lower than the reset voltage (Vres) is that the potential of the light receiving element portion is turned off when the reset switch is turned off because an NMOS transistor is used for the reset switch. Is turned to the minus side.

  Further, the present embodiment has shown an example in which the present inventors have applied to a photoelectric conversion device proposed in Japanese Patent Application Laid-Open No. 09-205588, but the present invention is not limited to this embodiment. For example, it goes without saying that the present invention can be applied to other photoelectric conversion devices and solid-state imaging devices.

  Although not shown, this embodiment constitutes a primary photoelectric conversion device provided with 344 pixels using the pixels having the above configuration as line sensors.

  By using the photoelectric conversion device of the present embodiment to form a contact image sensor and use it as an image reading device of an image input system such as a facsimile or an image scanner, the afterimage characteristics are good even during high-speed operation. Therefore, high-quality image reading can be realized, and a low-cost image reading apparatus can be provided because of high yield.

(Embodiment 8)
Hereinafter, Embodiment 8 of the present invention will be described with reference to FIGS. 23 (A) and 23 (B).

  FIG. 23A shows an upper surface of the light receiving element portion of the present embodiment, and FIG. 23B shows a cross section taken along line JJ ′ of FIG.

  23A and 23B, reference numeral 51 denotes a first semiconductor region which is a semiconductor substrate, and 52 denotes a second semiconductor region. Here, the respective conductivity types are n-type and p-type. The second semiconductor region 52 is formed inside the opening OP defined by the light shielding layer 17.

  A depletion layer DL is formed by a pn junction between the first semiconductor region 51 and the second semiconductor region 52. A reverse bias is applied between the first semiconductor region 51 and the second semiconductor region 52, and a large depletion layer DL extends toward the region 51 with a low impurity concentration. The electrode 15 is connected to the second semiconductor region 52 via the contact hole CH of the insulating film 9.

  When light is applied to the light receiving element, charges are generated in and around the depletion layer DL. The charge is collected in the second semiconductor region 52. On the other hand, many crystal defects exist at the interface between the main surface of the semiconductor substrate and the insulating film 9. This crystal defect becomes a generation level of an electron-hole pair and causes a dark current. In particular, the influence of crystal defects near the depletion layer DL is large.

  Further, when the electrode 15 is formed, if the formation position extends to a position where the depletion layer DL is not covered by the electrode 15, damage due to etching or the like increases the amount of crystal defects and increases dark current.

  Therefore, in the structure of the light receiving element according to the present embodiment, the portion 59 where the depletion layer DL and the insulating film 9 are in contact with each other is covered with the electrode 15 via the insulating film 9 so that the etching damage at the time of electrode formation is reduced. Since it does not reach DL, the dark current can be reduced.

  In addition, the electrode 15 is always formed on the portion 59 where the depletion layer DL and the insulating film 15 are in contact with each other in consideration of misalignment in photolithography. This suppresses the amount of crystal defects generated near the depletion layer DL from fluctuating due to process variations. Therefore, variations in dark current due to process variations are reduced.

  In the present embodiment, for example, Al, Al alloy, Ti, Ti alloy, W, W alloy, Co, Co alloy, Ta, Ta alloy, Mo, Mo alloy, Cu, Cu alloy, WN, TiN , TaN, Cr, Cr alloys and other metals, alloys and compounds are used. Or, they may be a plurality of types of laminates. Alternatively, it can be used as a conductive material mainly composed of silicon, such as doped polysilicon.

(Embodiment 9)
FIG. 24A shows an upper surface of the light receiving element, and FIG. 24B shows a cross section taken along line KK ′ of FIG.

In FIG. 24, 66 is an n-type semiconductor substrate, 67 is a buried n ⁺ -type region formed by ion implantation into the n-type semiconductor substrate 66, and 61 is a first semiconductor region formed on the n ⁺ -type region 67. ^- -type epitaxial layer 68 is the n ^- -type epitaxial layer 61 is formed by ion implantation is a n ⁺ -type region in contact with the embedded n ⁺ -type region.

  Reference numeral 62 denotes a second semiconductor region and an electrode region, specifically, a p-type high-concentration impurity region. Reference numeral 63 denotes an n-type region, which is provided to suppress the spread of the depletion layer DL on the main surface of the semiconductor substrate (the surface of the epitaxial layer). Electrode 15 formed of a metal or the like containing Al as a main component is electrically connected to electrode region 62 through contact hole CH of insulating film 9 formed on the main surface of the substrate. Further, 17 is a light shielding layer, OP is an opening, 5 is a LOCOS insulating film for element isolation, and 9 is an interlayer insulating film for insulating the light shielding layer 17 from the electrode 15.

In the present embodiment, the n-type substrate 66, the n ⁺ -type region 67, the n ^-- type epitaxial layer 61, the n ⁺ -type region 68, the n-type region 63, and the electrode region 62 are formed. The semiconductor part is called a substrate.

In FIG. 24, the potential barrier is formed by forming the n ⁻ -type epitaxial layer 61 so as to be surrounded by the lower portion and surrounding n ⁺ -type regions 67 and 68. As a result, holes among carriers generated by light are finally collected in the p-type electrode region 62 having the lowest potential.

The depletion layer DL is formed around the electrode region 62. Here, when the impurity concentration of the electrode region 62 is approximately 3 × 10 ¹⁹ cm ⁻³ , the impurity concentration of the n-type region 63 is approximately 2 × 10 ¹⁷ cm ^−3, and a reverse bias voltage of 3 V is applied to these, The layer width of the depletion layer DL is about 0.14 μm. Most of the depletion layer DL has spread to the n ⁻ type region 61 side from the pn junction surface between the electrode region 62 and the n ⁻ type region 61. On the substrate surface, the spread of the depletion layer DL is suppressed by the n-type region 63.

  The electrode 15 is arranged, for example, 0.4 μm larger than the electrode region 62 so as to cover the upper part of the portion where the depletion layer DL is in contact with the interlayer insulating film 9. As a result, the crystal defects caused by the etching damage at the time of forming the electrode 62 and the damage by the ashing of the resist do not reach the depletion layer DL, and the dark current is reduced.

  The dark current was compared between the case where the electrode 15 was formed so as to cover the portion 59 where the depletion layer DL and the insulating film 9 were in contact with each other. As a result, the portion where the depletion layer DL was in contact with the insulating film 9 was obtained. Is formed so as to completely cover the upper portion, the dark current is reduced to 2/3. That is, the dark current can be reduced depending on the size and the formation position of the electrode 15.

  Although the substrate 66 and the regions 67 and 68, the epitaxial layer 61, and the region 63 are described as n-type and the region 62 is described as p-type for the sake of simplicity, the present embodiment is limited to this conductivity type. Instead, each may be of the opposite conductivity type.

Further, in the present embodiment, a potential barrier is formed so as to surround the n ⁻ -type epitaxial layer 61 with the n ⁺ -type regions 67 and 68 to prevent photocarriers from being mixed into adjacent pixels. Since optical carriers do not mix into adjacent pixels, high-quality resolution patterns can be obtained by almost completely suppressing the occurrence of crosstalk.

(Embodiment 10)
FIG. 25A shows the top surface of the light receiving element, and FIG. 25B shows a cross section taken along line LL ′ of FIG.

In FIG. 25, reference numeral 76 denotes an n-type substrate. Reference numeral 77 denotes a buried n ⁺ -type region formed by ion implantation into the n-type substrate 76, 71 denotes an n ⁻ -type epitaxial layer which is a first semiconductor region formed on the n ⁺ -type region 77, and 78 denotes an n ⁻ -type epitaxial layer Is an n ⁺ -type region formed by ion implantation to surround the periphery of the epitaxial layer 71.

  Reference numeral 72 denotes a second semiconductor region. Reference numeral 74 denotes an electrode region, specifically, a p-type high-concentration impurity region. Reference numeral 73 denotes an n-type region, which is provided to suppress the spread of the depletion layer DL on the main surface of the substrate. Reference numeral 15 denotes an electrode formed of a metal or the like containing Al as a main component. Electrode 15 is electrically connected to electrode region 74 through contact hole CH of insulating film 9 formed on the main surface of the substrate.

When the electrode region 74 is miniaturized and the depletion layer DL spreads over the electrode region having a high impurity concentration, a dark current increases due to defects in the depletion layer. The p ⁻ type semiconductor region 72 is provided to suppress this. OP is an opening, 5 is an element isolation insulating film, and the upper interlayer insulating film 9 is an insulating film for insulating the light shielding layer 17 from the electrode 15.

In this embodiment, the n-type substrate 76, the n ⁺ -type region 77, the n ^-- type epitaxial layer 71, the n ⁺ -type region 78, the n-type region 73, and the electrode region 74 are formed. The thing is called a substrate.

In FIG. 25, the potential barrier is formed by forming the n ⁻ -type epitaxial layer 71 such that it is surrounded by the n ⁺ -type regions 77 and 78. Finally, it was collected in the p-type electrode region 74 having the lowest potential.

Depletion layer DL is formed around p-type region 72. Here, when the impurity concentration of the p-type region 72 is about 3 × 10 ¹⁸ cm ⁻³ , the impurity concentration of the n-type region 73 is about 2 × 10 ¹⁷ cm ^−3, and a reverse bias voltage of 3 V is applied to these, Means that the layer width of the depletion layer DL is about 0.15 μm. Most of the depletion layer DL has spread to the n-type region 71 side from the pn junction surface of the p-type region 72 and the n-type region 71.

  The electrode 15 is arranged, for example, 0.4 μm larger than the p-type region 72 so as to cover a portion 69 where the depletion layer DL and the insulating film 9 are in contact. As a result, crystal defects on the substrate surface caused by etching damage when the electrode 15 is formed and damage due to resist ashing do not reach the depletion layer DL, so that dark current can be reduced.

  For simplicity, the substrate 76 and the regions 77 and 78, the epitaxial layer 71 and the region 73 are described as n-type, and the regions 72 and 74 are described as p-type. However, this embodiment is limited to this conductivity type. Instead, each may be of the opposite conductivity type.

(Embodiment 11)
FIG. 26A is a top view of a light receiving element according to Embodiment 11 of the present invention, and FIG. 26B is a cross-sectional view taken along a line MM ′ in FIG.

In FIG. 26, 86 is a p-type substrate, 81 is an n-type region as a first semiconductor region, 82 is a p-type region as a second semiconductor region, and 83 is an n ⁺ type region as a third semiconductor region.

Reference numeral 84 denotes a p-type high-concentration impurity region serving as an electrode region, that is, a p ⁺ -type region, which is arranged on the main surface of the substrate with the n ⁺ -type region 83 and the offset region OF interposed therebetween. Reference numeral 15 denotes an electrode, which is formed of a metal containing Al as a main component. Electrode 15 is electrically connected to p ⁺ -type region 84 via contact hole CH of insulating film 9 formed on the main surface of p-type substrate 86. DL is a depletion layer.

The structure is such that the p-type region 82 is sandwiched between the n-type region 81 and the n ⁺ -type region 83. As a result, the depletion layer DL is formed at the p-type junction on the lower surface side and the pn junction on the upper surface side of the p-type region 82, and a state like a low potential groove is formed in the semiconductor region 82.

As a result, holes among the charges generated by light are collected in the p-type region 82 and finally collected in the p ⁺ -type region 84 having the lowest potential. In addition, by appropriately setting the impurity concentration of the n-type region 81, the impurity concentration and the junction depth of the p-type region 82 and the n ⁺ -type region 83, and the bias voltage of the pn junction as appropriate, Almost the whole can be depleted. As a result, the p-type region 82 hardly contributes to the capacitance of the light receiving element, and the capacitance of the light receiving element can be reduced.

When the electrode region 84 is brought into contact with the n ⁺ type region 83 without forming the offset region OF, a breakdown is caused when a reverse bias is applied between the electrode region 84 and the n ⁺ type region 83, A large amount of leak current flows into the p ⁺ type region 84, which is not preferable.

If the offset region OF is too small, the probability that the p ⁺ -type region 84 and the n ⁺ -type region 83 come into contact with each other due to misalignment in photolithography or the like increases. In order to reduce the yield of light receiving elements, in the present embodiment, a 1 μm offset region OF is provided between the p ⁺ region 84 and the left and right n ⁺ regions 83.

  The electrode 15 was formed so as to cover a portion 89 where the depletion layer DL and the insulating film 9 were in contact. Therefore, crystal defects on the substrate surface caused by etching damage during formation of the electrode 15 and damage due to resist ashing do not reach the depletion layer DL, and the dark current is reduced.

  The present embodiment is not limited to this conductivity type, and each conductivity type may be a conductivity type opposite to that described above.

  Further, in the present embodiment, the n-type region 81 is formed in the p-type substrate 86 to prevent optical carriers from being mixed into adjacent pixels. Therefore, the occurrence of crosstalk is almost completely suppressed, and a high-quality resolution pattern can be obtained.

  Even if an optical carrier equal to or larger than the accumulated saturation value is generated in a certain pixel, the overflowing optical carrier is absorbed by the p-type region 86 around the n-type region 81, and does not affect other pixels. A high-quality image with little bleeding can be obtained.

  With reference to FIGS. 27A to 27C and FIGS. 28A to 28C, the method for manufacturing the light receiving element according to the present embodiment will be described.

  A p-type semiconductor substrate 86 is prepared, and an n-type region 81 made of an n-type semiconductor is formed by ion implantation or the like (FIG. 27A).

  The field insulating film 5 is formed by a selective oxidation method, and thereafter, a p-type semiconductor region 82 is formed (FIG. 27B).

After forming the n ⁺ -type semiconductor region 83, a p ⁺ -type electrode region 84 is formed. Here, if necessary, low-concentration dopant ions may be implanted into the offset region between the semiconductor region 83 and the electrode region 84 (FIG. 27C).

  Next, an insulating film 9 made of PSG (PhosphoSilicate Glass: an oxide film doped with phosphorus), BSG (BoroSilicate Glass), BPSG (BoroPhosphoSilicata Glass) or the like is formed, and an opening CH is formed on the electrode region 84 ( FIG. 28 (A)).

  Next, a layer 15 of a conductive material such as Al-Cu is formed by sputtering or the like (FIG. 28B). At this time, a barrier metal such as TiN may be formed below the conductive material layer 15.

Then, the conductive material layer 15 is patterned by dry etching using BCl ₃ , Cl _2, etc., while leaving the conductive material layer 15 so as to cover the offset portion. Thus, the anode electrode 15 is obtained.

  The read and reset circuits shown in FIGS. 4, 7, 21 and 22 can also be used in the light receiving elements of the eighth to eleventh embodiments described above.

  Further, the present invention can be preferably applied to the photoelectric conversion device proposed in Japanese Patent Application Laid-Open No. 09-205588. Thus, a solid-state imaging device having a high yield in the manufacturing process can be manufactured, and thus a high-quality device can be provided.

(A) is a top view of the light receiving element according to the embodiment of the present invention, (B) is a cross-sectional view of the light receiving element according to the embodiment of the present invention, and (C) is a lateral potential profile of the light receiving element according to the embodiment of the present invention. FIG. 3D is a schematic diagram showing a vertical potential profile of the light receiving element according to the embodiment of the present invention. FIG. 4 is a diagram illustrating an impurity concentration distribution in a light receiving element according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a relationship between an applied voltage and a capacitance in a light receiving element. FIG. 2 is a circuit diagram of a read and reset circuit used in the present invention. (A) is a top view of the light receiving element according to the embodiment of the present invention, and (B) is a cross-sectional view of the light receiving element according to the embodiment of the present invention. (A)-(C) are typical sectional views showing an example of a method for manufacturing a light receiving element according to the embodiment of the present invention. FIG. 2 is a circuit diagram of a read and reset circuit used in the present invention. (A) is a top view of the light receiving element according to the embodiment of the present invention, and (B) is a cross-sectional view of the light receiving element according to the embodiment of the present invention. FIG. 5 is a schematic diagram illustrating a lateral potential profile of the light receiving element according to the embodiment of the present invention. (A)-(C) are typical sectional views showing an example of a method for manufacturing a light receiving element according to the embodiment of the present invention. (A) is a top view of the light receiving element according to the embodiment of the present invention, and (B) is a cross-sectional view of the light receiving element according to the embodiment of the present invention. FIG. 3 is a top view of the light receiving element according to the embodiment of the present invention. FIG. 3 is a sectional view of a light receiving element according to the embodiment of the present invention. FIG. 3 is a sectional view of a light receiving element according to the embodiment of the present invention. FIG. 3 is a top view of the light receiving element according to the embodiment of the present invention. FIG. 3 is a sectional view of a light receiving element according to the embodiment of the present invention. FIG. 3 is a sectional view of a light receiving element according to the embodiment of the present invention. FIG. 3 is a top view of the light receiving element according to the embodiment of the present invention. FIG. 3 is a sectional view of a light receiving element according to the embodiment of the present invention. (A)-(D) are typical sectional views showing an example of a method for manufacturing a light receiving element according to the embodiment of the present invention. FIG. 2 is a circuit diagram of a read and reset circuit used in the present invention. FIG. 2 is a circuit diagram of a read and reset circuit used in the present invention. (A) is a top view of the light receiving element according to the embodiment of the present invention, and (B) is a cross-sectional view of the light receiving element according to the embodiment of the present invention. (A) is a top view of the light receiving element according to the embodiment of the present invention, and (B) is a cross-sectional view of the light receiving element according to the embodiment of the present invention. (A) is a top view of the light receiving element according to the embodiment of the present invention, and (B) is a cross-sectional view of the light receiving element according to the embodiment of the present invention. (A) is a top view of the light receiving element according to the embodiment of the present invention, and (B) is a cross-sectional view of the light receiving element according to the embodiment of the present invention. (A) to (C) are diagrams illustrating an example of a method for manufacturing the light receiving element according to the present embodiment. (A) to (C) are diagrams illustrating an example of a method for manufacturing the light receiving element according to the present embodiment. (A), (B) is sectional drawing of the conventional light receiving element. It is a top view of the conventional light receiving element. It is sectional drawing of the conventional light receiving element. It is sectional drawing of the conventional light receiving element. It is sectional drawing of the conventional light receiving element.

Explanation of reference numerals

1, 11, 31 First semiconductor regions 2, 12, 32 Second semiconductor regions 3, 13, 33 Third semiconductor regions 4, 14, 34 Low potential regions (electrode regions)
5 element isolation region 15 wiring 16 power supply line 17 light shielding layer 101 electrode region 102 photodiode region (light receiving region)
103 edge 104 edge 605 holding capacitor 609 noise signal holding capacitor 610 optical signal holding capacitor 614 buffer amplifier 615 differential amplifier 690 noise signal common output line 691 optical signal common output line M1 reset MOS transistor M2 amplifying MOS transistor M3 MOS transistor

Claims (5)

A first semiconductor region of a first conductivity type;
A second semiconductor region of a first conductivity type and having a lower impurity concentration than the first semiconductor region, the second semiconductor region being disposed on the first semiconductor region;
A second conductivity type electrode region disposed on a surface of the second semiconductor region;
An electrode connected to the electrode region;
An amplification element of a readout circuit connected to the electrode;
A photoelectric conversion element comprising: The photoelectric conversion element according to claim 1,
The second semiconductor region is an epitaxial layer. The photoelectric conversion element according to claim 1,
The photoelectric conversion element, wherein the amplification element forms a source follower circuit. The photoelectric conversion element according to claim 1,
The photoelectric conversion element according to claim 1, wherein the second semiconductor region is surrounded by a region of a first conductivity type having a higher impurity concentration than the second semiconductor region. The photoelectric conversion element according to claim 1,
A portion wider than the electrode region, wherein the anode or cathode electrode has a depletion layer formed between the electrode region and the second semiconductor region covering above all portions in contact with the interlayer insulating film; A photoelectric conversion element comprising: