JP2005123280A - Solid state image sensing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decrease the quantity of saturation-signal charges of a sensor by the reduction of the volume of a signal-charge storage region because a p-type well region reduces the volume of the signal-charge storage region when a sensor structure is adopted in which a p-type semiconductor region on the surface of the sensor and the p-type well region under an element isolation layer are overlapped. <P>SOLUTION: In a solid state image sensing device adopting a HAD sensor structure having the p-type semiconductor region 34 on the surface of a sensor, second semiconductor regions 37 are formed near the boundaries of photodiodes 21 and the element isolation layers 35, and a dark current generated among the photodiodes 21 and the element isolation layers 35, and a white-point defect resulting from the dark current is inhibited by the working of the semiconductor regions 37. Consequently, the reduction of the volume of the n-type semiconductor region 33 (the signal-charge storage region) is decreased, and the reduction of the quantities of the saturation-signal charges of the photodiodes 21 is inhibited minimally. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state image sensor, and more particularly to a solid-state image sensor having a sensor structure in which a sensor unit that performs photoelectric conversion suppresses a dark current generated between the sensor unit and an element isolation layer.

In a solid-state imaging device, for example, a MOS type or CMOS type solid-state imaging device, each of sensor parts (pixels) that perform photoelectric conversion is arranged in an XY matrix by an element isolation layer by selective oxidation, a so-called LOCOS (local oxidation of silicon) layer It is formed by isolation (element isolation). Specifically, for example, after forming a P-type well region in an N-type silicon semiconductor substrate, an element isolation layer (LOCOS layer) is formed by selective oxidation, and then a thin insulating film (for example, SiO ₂ film) is interposed. Thus, the sensor portion is formed by ion-implanting N-type impurities into the surface of the P-type well region to form a signal charge storage region.

  Also, a sensor structure (so-called HAD (Hole Accumulated Diode) that reduces dark current generated from the sensor surface by forming a P-type semiconductor region at the surface of the sensor portion, that is, at the interface between the signal charge storage region and the insulating film. Sensor structure) is generally adopted. In this type of solid-state imaging device, at the time of forming the sensor portion, an N-type impurity is ion-implanted to protect other regions with a photoresist layer aligned on the device isolation layer. A PN junction appears. It is known that crystal defects such as dislocations are generated due to stress at the end of the element isolation layer. Therefore, when the depletion layer generated by applying a reverse bias to the PN junction comes to the end region of the element isolation layer having the crystal defect, the leakage current is increased by the electric field.

  When the leakage current increases in the sensor unit, electric charges are generated even when no light is incident, and this becomes a dark current. Since this dark current is generated due to crystal defects, the amount generated differs depending on each sensor unit, and the difference in the amount of dark current generated appears as unevenness in image quality or appears as a white spot defect. . Therefore, conventionally, a second P-type well region is formed between the P-type well region formed in the silicon semiconductor substrate and the element isolation layer, and the second P-type well below the element isolation layer is formed. The region and the P-type semiconductor region on the surface of the sensor part overlap each other to some extent (for example, see Patent Document 1).

  Thus, by adopting a sensor structure in which the P-type semiconductor region on the surface of the sensor unit and the P-type well region (second P-type well region) under the element isolation layer are overlapped, the sensor unit and the element isolation are provided. It is possible to suppress dark current generated between layers and white spot defects caused by the dark current. Further, the greater the amount of overlap between the P-type semiconductor region and the P-type well region, the greater the effect of suppressing dark current and white spot defects.

JP 2000-299453 A

  However, when a sensor structure in which the P-type semiconductor region on the surface of the sensor unit and the second P-type well region under the element isolation layer are overlapped, the P-type well region is also used as the signal charge storage region of the sensor unit. Since the overlap occurs, the overlap portion reduces the volume of the signal charge storage region. When the volume of the signal charge accumulation region is reduced, the saturation signal charge amount of the sensor unit is reduced by the volume reduction.

  The present invention has been made in view of the above problems, and its object is to suppress dark current generated between the sensor unit and the element isolation layer and white spot defects caused by the dark current. An object of the present invention is to provide a solid-state imaging device capable of minimizing a decrease in the saturation signal charge amount of the sensor unit.

  A solid-state imaging device according to the present invention includes a second conductivity type semiconductor region formed on a first conductivity type first well region and a first conductivity type first region formed on the second conductivity type semiconductor region. A plurality of sensor portions having one semiconductor region, an element isolation layer that performs element isolation between the plurality of sensor portions, and a first well region formed between the first well region and the element isolation layer. The structure includes a first conductivity type second well region and a first conductivity type second semiconductor region formed in the vicinity of the boundary between the sensor portion and the element isolation layer.

  In the solid-state imaging device having the above configuration, a PN junction type sensor unit is formed by the first well region and the semiconductor region formed thereon. In the sensor unit, the first semiconductor region reduces dark current by accumulating electric charges (for example, holes) generated from the sensor surface. The second well region deepens the position of the PN junction of the sensor unit. Thereby, since the spreading depth of the depletion layer becomes deep, the photoelectric conversion efficiency in the sensor unit increases. The second semiconductor region isolates the PN junction of the sensor portion from the end portion of the element isolation layer where crystal defects such as dislocations exist, and when the PN junction is biased, the depletion layer becomes the end of the element isolation layer. It is generated at a position away from the part. As a result, the generation of a leak current near the end of the element isolation layer is suppressed, and the dark current is reduced. That is, even if the second well region under the element isolation layer is not formed so as to overlap the first semiconductor region, the second well region is generated between the sensor portion and the element isolation layer by the action of the second semiconductor region. Dark current can be reduced.

  According to the present invention, the second well region under the element isolation layer is overlapped with the first semiconductor area by the second semiconductor region formed in the vicinity of the boundary between the sensor portion and the element isolation layer. Since the dark current can be reduced even if it is not, the dark current generated between the sensor unit and the element isolation layer and the white spot defect caused by the dark current can be suppressed, and the signal charge accumulation region caused by the overlap Therefore, the decrease in the saturation signal charge amount of the sensor unit can be minimized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an outline of a configuration of a solid-state imaging device according to an embodiment of the present invention, for example, an XY address type solid-state imaging device represented by a CMOS image sensor.

  As shown in FIG. 1, the XY address type solid-state imaging device according to the present embodiment includes an imaging unit 11 in which pixels (sensor units) including photoelectric conversion elements are two-dimensionally arranged in a matrix, and the imaging unit 11. And a signal for performing signal processing such as CDS (Correlated Double Sampling) processing on the signal of each pixel read out from the imaging unit 11 in units of rows. A processing circuit 13, a horizontal scanning circuit 14 for sequentially selecting pixel signals for one row output from the signal processing circuit 13 in units of pixels, and a horizontal output for sequentially outputting pixel signals selected by the horizontal scanning circuit 15 And a circuit 15.

  FIG. 2 is a circuit diagram showing an example of a specific circuit configuration of the pixel 16 when the XY address type solid-state imaging device is a CMOS image sensor, for example. As apparent from FIG. 2, the pixel 16 includes, for example, a photodiode (PD) 21 as a photoelectric conversion element, and the transfer transistor 22, the amplification transistor 23, the address transistor 24, and the like are connected to the one photodiode 21. The circuit configuration has four transistors of the reset transistor 25 as active elements.

  The photodiode 21 is grounded at its anode, and photoelectrically converts incident light into charges (here, electrons) in an amount corresponding to the amount of light. The transfer transistor 22 is connected between the cathode of the photodiode 21 and the floating diffusion portion FD, and a transfer pulse is applied to the gate through the transfer wiring 26, whereby the electrons photoelectrically converted by the photodiode 21 are transferred to the floating diffusion portion. Transfer to FD.

  The gate of the amplification transistor 23 is connected to the floating diffusion portion FD. The amplification transistor 23 is connected to a vertical signal line 27 via an address transistor 24. When the selection pulse is applied to the gate of the address transistor 25 through the address wiring 28 and the address transistor 25 is turned on, the amplification transistor 23 amplifies the potential of the floating diffusion portion FD and applies a voltage corresponding to the potential to the vertical signal line. 27. The vertical signal line 27 transmits the voltage output from each pixel to the signal processing circuit 13 (see FIG. 1).

  The reset transistor 25 is connected between the power supply Vdd and the floating diffusion portion FD, and is turned on when a reset pulse is applied to the gate through the reset wiring 29, and the potential of the floating diffusion portion FD is reset to the potential of the power supply Vdd. To do. In these operations, since the wirings 26, 28, and 29 to which the gates of the transfer transistor 22, the address transistor 24, and the reset transistor 25 are connected are wired in units of rows, the pixels for one row are simultaneously processed. Is called.

  FIG. 3 is a plan pattern diagram showing a configuration example of the photodiode (PD) 21 of the pixel 16, the floating diffusion portion FD, and the gate portion (read gate portion) of the transfer transistor 22. FIG. 4 shows a cross section taken along the line XX ′ of FIG. Here, the semiconductor conductivity type will be described by taking as an example the case where the first conductivity type is P-type and the second conductivity type is N-type, but the opposite is also possible.

  In FIG. 4, the solid-state imaging device according to the present embodiment has a configuration employing an N-type silicon substrate 31 and a P-type well region 32 formed on the silicon substrate 31. The photodiode 21 which is a sensor unit is formed by a PN diode including a P-type well region 32 and an N-type semiconductor region (N layer) 33 formed on the P-type well region 32. The N-type semiconductor region 33 serves as a signal charge accumulation region for accumulating signal charges (here, electrons) obtained by photoelectric conversion.

  The photodiode 21 has a HAD sensor structure having a first P-type semiconductor region (P layer) 34 at the interface between the N-type semiconductor region 33 and the substrate surface. The first P-type semiconductor region 34 functions to accumulate holes generated from the sensor surface and reduce dark current caused by the holes. Each of the photodiodes 21 is separated into pixels by an element isolation layer (for example, a LOCOS layer) 35 by selective oxidation.

  Here, the first P-type well region 32 accumulates an appropriate amount of signal charge in the N-type semiconductor region 33 and functions as an overflow barrier for overflowing excess signal charge to the N-type silicon substrate 31. A second P type well region 36 is formed between the first P type well region 32 and the element isolation layer 35. The second P-type well region 36 functions to deepen the position of the PN junction of the photodiode 21. As the position of the PN junction becomes deeper, the depletion layer spreads deeper and the photoelectric conversion efficiency in the photodiode 21 increases.

  The photodiode 21 further has a second P-type semiconductor region 37 in the vicinity of the boundary between the photodiode 21 and the element isolation layer 35. The second P-type semiconductor region 37 functions as follows. That is, in forming the photodiode 21, when the N-type semiconductor region 33 is formed by ion implantation of N-type impurities while protecting other regions with a photoresist layer aligned on the device isolation layer 35. A PN junction appears at the end of layer 35. Since crystal defects such as dislocations are generated due to stress at the end portion of the element isolation layer 35, a depletion layer generated by applying a reverse bias to the PN junction comes to a region of the element isolation layer 35 having this crystal defect. As a result, the leakage current that causes dark current is increased by the electric field.

  On the other hand, the second P-type semiconductor region 37 isolates the PN junction of the photodiode 21 from the end of the element isolation layer 35 where crystal defects such as dislocations exist and biases the PN junction. In addition, a depletion layer is generated at a position away from the end of the element isolation layer 35. As a result, the generation of leakage current near the end of the element isolation layer 35 is suppressed, so that dark current is reduced. That is, the second P-type semiconductor region can be formed without forming the second P-type well region 36 under the element isolation layer 35 so as to overlap the first P-type semiconductor region 34 as in the prior art. The action of 37 can reduce the leakage current generated between the photodiode 21 and the element isolation layer 35, and hence the dark current.

  In forming the second P-type semiconductor region 37, as shown in FIG. 3, a predetermined distance d from the readout gate portion 38 that transfers the signal charge photoelectrically converted by the photodiode 21 to the floating diffusion portion FD, For example, it is preferable to form them separated by a distance of about 0.3 μm. Thus, by forming the second P-type semiconductor region 37 away from the read gate portion 38 by a predetermined distance d, the influence on the read gate portion 38 due to ion implantation of P-type impurities is minimized. Therefore, the signal charge can be reliably transferred from the photodiode 21 to the floating diffusion portion FD without increasing the voltage of the transfer pulse applied to the read gate portion 38.

  As described above, by forming the second semiconductor region 37 in the vicinity of the boundary between the photodiode 21 and the element isolation layer 35, the element isolation layer 35 in which the PN junction of the photodiode 21 has crystal defects such as dislocations exists. When the PN junction is biased, the depletion layer can be generated at a position away from the end of the element isolation layer 35, so that the second under the element isolation layer 35 is provided. Even if the P-type well region 36 is not formed so as to overlap the first P-type semiconductor region 34, a dark current generated between the photodiode 21 and the element isolation layer 35 and a white spot caused by the dark current Defects can be suppressed. In addition, since the volume of the N-type semiconductor region (signal charge storage region) 33 caused by the overlap is small, a decrease in the saturation signal charge amount of the photodiode 21 can be minimized.

  When the second semiconductor region 37 is not provided (prior art), the second P-type well region 36 is larger than the amount of the second P-type well region 36 that protrudes (overlaps) to the photodiode 21. In principle, even if the amount of protrusion to the photodiode 21 is small, as shown in FIG. 4, the second P-type well region 36 does not protrude to the photodiode 21 at all. The above-described operation and effect by the semiconductor region 37 can be obtained.

  However, in FIG. 4, the second P-type well region 36 under the element isolation layer 35 is shown so as not to protrude from the end portion of the element isolation layer 35 to the photodiode 21. When the impurity concentration of the P-type well region 36 is high, the amount of diffusion in the lateral direction increases, so that it inevitably protrudes toward the photodiode 21 and overlaps with the N-type semiconductor region 33 and the first P-type semiconductor region 34, thereby The volume of the N-type semiconductor region 33 as the accumulation region is reduced, and the saturation signal amount is reduced.

  Therefore, the impurity concentration of the second P-type well region 36 is made lower than the impurity concentration when the second P-type well region 36 is not provided (prior art). Thereby, the amount of diffusion of the impurity in the second P-type well region 36 in the lateral direction can be reduced, so that the amount of protrusion of the second P-type well region 36 to the photodiode 21 can be suppressed, and the N-type semiconductor region 33. The decrease in the volume can be suppressed. Even if the second P-type well region 36 protrudes to the photodiode 21 due to diffusion, the second P-type well region 36 has a low concentration due to the low impurity concentration of the second P-type well region 36. Since it can be considered that there is substantially no volume of the N-type semiconductor region 33 due to the portion, a decrease in the saturation signal charge amount of the photodiode 21 can be minimized.

  In addition, the above-described action by the semiconductor region 37, that is, the action of generating a depletion layer at a position away from the end of the element isolation layer 35 when a bias is applied to the PN junction, The second semiconductor region 37 is not provided in the second P-type well region 36 below the second P-type well region 36 but provided in the second semiconductor region 37 formed separately from the second P-type well region 36. 37 can be formed away from the read gate portion 38, so that the influence of ion implantation of P-type impurities on the read operation (transfer operation) of the signal charge from the photodiode 21 to the floating diffusion portion FD is minimized. Can do.

  In the above-described embodiment, the case where the present invention is applied to a sensor unit of an XY address type solid-state imaging device typified by a CMOS image sensor has been described as an example. However, the present invention is not limited to this application example. Can be similarly applied to a sensor portion of a charge transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) image sensor.

  The solid-state imaging device according to the present invention can be used, for example, as an imaging device of a camera module such as a digital still camera or a video camera, and further as an imaging device of a mobile terminal device represented by a mobile phone equipped with a camera function. .

It is a block diagram which shows the outline of a structure of the XY address type solid-state image sensor concerning one Embodiment of this invention. It is a circuit diagram which shows an example of the specific circuit structure of the pixel in the case of a CMOS image sensor. It is a plane pattern figure which shows the structural example of a photodiode (PD), the floating diffusion part FD, and the read-out gate part. It is XX 'arrow sectional drawing of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Imaging part, 12 ... Vertical scanning circuit, 13 ... Signal processing circuit, 14 ... Horizontal scanning circuit, 15 ... Horizontal output circuit, 16 ... Pixel, 21 ... Photodiode, 22 ... Transfer transistor, 23 ... Amplifying transistor, 24 ... Address transistor, 25 ... reset transistor, 31 ... N-type silicon substrate, 32 ... first P-type well region, 33 ... N-type semiconductor region (signal charge storage region), 34 ... first P-type semiconductor region (holes) Accumulation region), 35 ... element isolation layer, 36 ... second P-type well region, 37 ... second P-type semiconductor region, 38 ... read gate portion

Claims (4)

A plurality of first conductivity type semiconductor regions formed on the first conductivity type first well region and a first conductivity type first semiconductor region formed on the second conductivity type semiconductor region. Sensor part of
An element isolation layer that performs element isolation between the plurality of sensor units;
A second well region of a first conductivity type formed between the first well region and the element isolation layer;
A solid-state imaging device comprising: a first conductivity type second semiconductor region formed in the vicinity of a boundary between the sensor unit and the element isolation layer. 2. The solid-state imaging device according to claim 1, wherein the second well region has an amount of protrusion to the sensor portion smaller than an amount of protrusion when the second semiconductor region is not provided. 2. The solid-state imaging device according to claim 1, wherein the second well region has an impurity concentration lower than an impurity concentration when the second semiconductor region is not provided. The solid-state imaging device according to claim 1, wherein the second semiconductor region is formed apart from a read gate portion that reads signal charges from the sensor portion.

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