CN110797368A - Image sensor unit and method for manufacturing the same - Google Patents
Image sensor unit and method for manufacturing the same Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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- H—ELECTRICITY
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Abstract
The invention discloses an image sensor unit and a preparation method thereof, wherein the image sensor unit comprises a photodiode, a floating diffusion region and a shallow groove isolation region, wherein the photodiode and the floating diffusion region are formed on an active region of a substrate and are connected, the shallow groove isolation region is formed on the boundary of the active region, a gap is formed between the boundary of the floating diffusion region and the boundary of the shallow groove isolation region, a first protection region is formed in the gap, the first protection region has a doping type opposite to that of the floating diffusion region and forms a PN junction with the floating diffusion region and is used for isolating the floating diffusion region from the shallow groove isolation region, and/or a second protection region is formed at the bottom of the floating diffusion region and has a doping type opposite to that of the floating diffusion region and forms a PN junction with the floating diffusion region and is used for isolating the floating diffusion region from the substrate. The invention can effectively reduce the parasitic leakage and noise of the node capacitance of the floating diffusion region.
Description
Technical Field
The invention relates to the technical field of image sensors, in particular to a global shutter image sensor unit.
Background
Generally, an image sensor refers to a device that converts an optical signal into an electrical signal. The image sensor cell class is dominated by Charge Coupled Devices (CCD) and Complementary Metal Oxide Semiconductor (CMOS) devices. Compared with the traditional CCD sensor, the CMOS image sensor has the characteristics of low power consumption, low cost, compatibility with the CMOS process and the like, so that the CMOS image sensor is more and more widely applied.
The CMOS image sensor comprises a pixel array formed by a plurality of pixel units, and the pixel units are core devices for realizing sensitization of the image sensor. In CMOS image sensors, the exposure time is usually controlled by an electronic shutter, which is classified into two types according to the operating principle: drum-type and global exposure type. Exposure time between each row of the drum-type electronic shutter is inconsistent, and a smear phenomenon is easily caused when a high-speed object is shot; each row of the global exposure type electronic shutter is exposed at the same time, then charge signals are stored in storage nodes of the pixel units at the same time, and finally signals of the storage nodes are output row by row. Since all the rows of the global exposure type CMOS image sensor are exposed at the same time, the smear phenomenon is not caused.
In the prior art, a common image sensor capable of realizing a global shutter is a five-transistor (5Transistors, 5T) unit, and an active pixel structure composed of one Photodiode (PD) and 5Transistors is usually included in a pixel unit.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a structural principle of a pixel unit of a conventional 5T CMOS image sensor. The 5T pixel unit includes one photodiode 101 formed on a P-type substrate 108, and 5 MOS transistors and Floating Diffusion (FD) connected to the photodiode 101. The 5 MOS transistors are a Reset (RX) transistor 102, a Transmission (TX) transistor 103, a Source Follower (SF) 104, a Row Select (RS) transistor 105, and a Global Reset Gate (GX) transistor 106, respectively, and the floating diffusion 107 is a charge storage node. Among these devices, the photodiode 101 is a light-sensing unit that generates electrons based on incident light, achieving collection of light and photoelectric conversion; the transfer transistor 103 transfers electrons generated by the photodiode 101 to the floating diffusion region 107 as a storage node by its gate control. The 5 MOS transistors 102 to 106 are control units that mainly realize control of selection, reset, and readout of the photodiode 101. In general, the number of electrons generated by exposure in the photodiode 101 is proportional to the amount of incident light until the diode is saturated.
In the process of reading out the signals of the 5T global shutter image sensor unit, the global transistor 106 simultaneously resets the pixel units of the whole array and starts exposure timing, after exposure is finished, an electronic signal is simultaneously transmitted to the floating diffusion region 107 serving as a storage node through the transmission transistor 103, and then the electronic signal is sequentially read out through the column-level ADC circuit. Therefore, there is a time difference between the first row readout and the last row readout, and the size of the time difference is determined by the row processing time and the number of array rows (array size). However, the floating diffusion region 107 itself is a PN junction diode, and there is a problem that a signal is disturbed due to influence of light leakage, noise, or the like. The larger the array, the longer the row processing time, the more signal interference, and the more affected the rows read later. These factors result in the image appearing as a gradual change from top to bottom and non-uniform pits.
Therefore, special protection of the floating diffusion region is needed to reduce or even eliminate interference from parasitic light, parasitic leakage, noise, etc.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art, and provides an image sensor cell and a method for fabricating the same, so as to reduce the parasitic leakage and noise of the node capacitance of the floating diffusion region.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an image sensor unit comprising: the photodiode and the floating diffusion region which are formed on an active region of a substrate and are connected with each other, and a shallow slot isolation region formed on the boundary of the active region, wherein a gap is formed between the boundary of the floating diffusion region and the boundary of the shallow slot isolation region, a first protection region is formed in the gap, the first protection region has a doping type opposite to that of the floating diffusion region, forms a PN junction with the floating diffusion region and is used for isolating the floating diffusion region from the shallow slot isolation region, and/or a second protection region is formed at the bottom of the floating diffusion region, has a doping type opposite to that of the floating diffusion region, forms a PN junction with the floating diffusion region and is used for isolating the floating diffusion region from the substrate.
Further, the first protection area is connected with the second protection area.
Further, the second protection region has the same doping type as the substrate, and the doping concentration of the second protection region is higher than that of the substrate.
Further, the gap has a width of 0.05 to 0.5 micrometers.
Further, still include: a global transistor, a transfer transistor, a reset transistor, a source follower, and a row select transistor formed on an active region of the substrate; wherein one side of the photodiode is connected to a power supply voltage through the global transistor, the other side of the photodiode is connected to the floating diffusion region through the transfer transistor, and the floating diffusion region is connected to a signal output terminal through the reset transistor, the source follower, and the row select transistor.
An image sensor cell preparation method comprising the steps of:
providing a substrate, defining an active region on the substrate, forming a photodiode and a floating diffusion region which are connected on the active region, and forming a shallow slot isolation region which surrounds the active region on the boundary of the active region; wherein a gap is arranged between the boundary of the floating diffusion region and the boundary of the shallow trench isolation region;
forming a lithographic window over the gap;
performing ion implantation of the opposite doping type of the substrate to the floating diffusion region through the photoetching window in an inclined angle implantation mode, and simultaneously implanting impurities into the gap at the edge of the floating diffusion region and below the bottom of the floating diffusion region;
and annealing to form a protective region in the gap and below the bottom of the floating diffusion region.
Further, still include:
forming a global transistor, a transmission transistor, a reset transistor, a source follower and a row selection transistor on the active region, connecting one side of the photodiode with the global transistor, connecting the other side of the photodiode with the floating diffusion region through the transmission transistor, and connecting the floating diffusion region with the reset transistor, the source follower and the row selection transistor.
Further, the gap has a width of 0.05 to 0.5 micrometers.
Further, the doping concentration of the tilt angle injection is higher than that of the substrate.
Further, the inclination angle is inclined by 10 to 45 degrees with respect to the vertical direction.
Compared with the conventional global shutter image sensor unit, the invention forms a PN junction by adding another type of doping around and at the bottom of the floating diffusion region, thereby effectively protecting the signals of the floating diffusion region. The invention has the following advantages:
firstly, PN junction isolation is formed in the edge area of the floating diffusion area close to the shallow groove isolation area, so that the influence from the shallow groove isolation area can be effectively prevented, and the electric leakage is reduced. The boundary of the shallow trench isolation region is affected by etching damage and is a main source of dark current. After PN junction protection is formed, the boundary of the floating diffusion region can be effectively pushed away from the boundary of the shallow trench isolation region, so that the influence of the shallow trench isolation region is greatly reduced.
And secondly, the doping concentration of the other type is increased for the protection region at the bottom of the floating diffusion region, so that the formed PN junction has better isolation effect, and the noise and the electric leakage of the substrate can be effectively isolated.
Thirdly, the preparation method provided by the invention provides a process implementation method of the dip angle injection, the process is simple, and another type of impurities can be simultaneously injected at the edge and the bottom of the floating diffusion region only by one-time photoetching and injection.
Drawings
Fig. 1 is a schematic diagram of a structural principle of a pixel unit of a conventional 5T CMOS image sensor.
Fig. 2 is a schematic diagram of a pixel unit structure of a 5T global shutter image sensor according to a preferred embodiment of the invention.
Fig. 3-8 are schematic diagrams of a process flow structure for manufacturing a pixel unit of a 5T global shutter image sensor according to a preferred embodiment of the invention.
Detailed Description
The present invention provides an image sensor unit including: the photodiode and the floating diffusion region which are formed on an active region of a substrate and are connected with each other, and a shallow slot isolation region formed on the boundary of the active region, wherein a gap is formed between the boundary of the floating diffusion region and the boundary of the shallow slot isolation region, a first protection region is formed in the gap, the first protection region has a doping type opposite to that of the floating diffusion region, forms a PN junction with the floating diffusion region and is used for isolating the floating diffusion region from the shallow slot isolation region, and/or a second protection region is formed at the bottom of the floating diffusion region, has a doping type opposite to that of the floating diffusion region, forms a PN junction with the floating diffusion region and is used for isolating the floating diffusion region from the substrate. Compared with the conventional global shutter image sensor unit, the invention forms a PN junction by adding another type of doping around and at the bottom of the floating diffusion region, thereby effectively protecting the signals of the floating diffusion region.
The invention is applicable to any structure with a floating diffusion region (FD) as a global pixel signal storage node, such as the structures of 5T, 6T, 7T and other CMOS image sensor pixel units represented by 5T.
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following detailed description of the present invention, please refer to fig. 2, wherein fig. 2 is a schematic diagram illustrating a pixel unit structure of a 5T global shutter image sensor according to a preferred embodiment of the present invention. As shown in fig. 2, taking the structure of a 5T global shutter image sensor pixel unit as an example, but not limited thereto, an image sensor unit of the present invention may include: a photodiode 201, a floating diffusion 207, a global transistor 206, a transfer transistor 203, a reset transistor 202, a source follower 204, a row select transistor 205, and the like formed on an active area of a substrate 208. A shallow trench isolation region STI for isolating the active region is provided around the substrate 208 at the boundary of the active region, and a gap L is provided between the boundary of the floating diffusion region 207 and the boundary of the shallow trench isolation region STI. The width of the gap L may be, for example, 0.05 to 0.5 microns. The substrate 208 may be, for example, a silicon substrate 208, but is not limited thereto.
Please refer to fig. 2. One side of the photodiode 201 is connected to a power supply voltage VDD through a global transistor 206, and the other side of the photodiode 201 is connected to a floating diffusion region 207 through a transfer transistor 203. The floating diffusion 207 is connected to the power supply voltage VDD through the reset transistor 202, and at the same time, the floating diffusion 207 is also connected to the gate of the source follower 204 and transfers a signal to the output terminal VOUT through the row select transistor 205. The row select transistor 205 is also connected to ground VSS. Regions of the silicon substrate 208 having different doping types and doping concentrations, including N-type and P-type doped regions, are illustrated as can be understood with reference to the prior art.
The floating diffusion region 207 is doped with an N-type impurity, for example. In a region of the floating diffusion region 207 near a gap L between an edge region (boundary) of the shallow trench isolation region STI and the boundary of the shallow trench isolation region STI, there is a P-type doped region of an opposite doping type as a first protection region 209'. The first guard region 209' may extend from the front surface of the silicon substrate 208 down into the substrate 208 at least no lower than the bottom of the floating diffusion region 207.
The first protection region 209' forms a PN junction with the floating diffusion region 207 for isolating the floating diffusion region 207 from the shallow trench isolation region STI to isolate the influence of the edge of the shallow trench isolation region STI on the storage node signal of the floating diffusion region 207.
Please refer to fig. 2. A second guard region 209 "may also be provided at the bottom of the floating diffusion region 207, either separately or simultaneously. The second protection region 209 ″ is also a P-type doped region and forms a PN junction with the floating diffusion region 207 for isolating the influence of the silicon substrate 208 on the storage node signal of the floating diffusion region 207.
When the second guard region 209 "is disposed simultaneously with the first guard region 209 ', the second guard region 209" may be connected to the first guard region 209 ' to form a guard region 209 of an integral structure composed of the first guard region 209 ' and the second guard region 209 "under and at the edge of the floating diffusion region 207. The protection region 209 forms a PN junction with the floating diffusion 207, which can simultaneously isolate the STI edge and the substrate 208 from the storage node signal of the floating diffusion 207.
In operation, the global transistor 206 simultaneously resets the photodiodes 201 of the entire pixel cell array, clears all electrons, turns off, and begins exposure. The reset transistor 202 resets the floating diffusion region 207. Upon being affected by the illumination, the photodiode 201 generates electrons and stores them. After the exposure time is over, the transfer transistor 203 is turned on and transfers the electrons stored in the photodiode 201 to the floating diffusion region 207 for storage, and the storage signal needs to be stored for a long time.
However, the boundary of the shallow trench isolation STI near the floating diffusion 207 is affected by the etching damage and is a main source of dark current. Meanwhile, the silicon dioxide filled in the shallow trench isolation STI may be affected by the process, and has metal ion positive charges, which may also cause leakage on the silicon surface, resulting in loss of the storage node signal of the floating diffusion region 207.
In the invention, the floating diffusion region 207 is close to the edge region (gap L) of the shallow trench isolation region STI to form a PN junction isolation (first protection region 209'), thereby effectively preventing the influence of the shallow trench isolation region STI and reducing electric leakage. After PN junction protection, the boundary of the floating diffusion region 207 is pushed away from the STI boundary of the shallow trench isolation region, thereby greatly reducing the influence of the STI.
Meanwhile, the silicon substrate 208 of the whole image sensor array is connected together, and the floating diffusion region 207 of the pixel unit of the image sensor is easily affected by noise or leakage of the silicon substrate 208 to interfere with the storage signal. The present invention can effectively isolate the influence of noise and leakage of the silicon substrate 208 on the floating diffusion region 207 by forming the PN junction isolation (second protection region 209) also at the bottom of the floating diffusion region 207.
Further, the doping concentration of the second protection region 209 "(which may include the first protection region 209') may be increased to make the doping concentration of the second protection region 209" higher than the doping concentrations of the silicon substrate 208 and the P-well, so that the isolation effect of the formed PN junction may be better.
A method for manufacturing an image sensor unit according to the present invention is described in detail below with reference to the accompanying drawings.
Referring to fig. 3-8, fig. 3-8 are schematic process flow structures for manufacturing a pixel unit of a 5T global shutter image sensor according to a preferred embodiment of the invention. As shown in fig. 3-8, a method for fabricating an image sensor unit according to the present invention can be used to fabricate the above-mentioned image sensor unit structure such as that shown in fig. 2. Taking the formation of a 5T global shutter image sensor pixel unit as an example, the method for manufacturing an image sensor unit of the present invention may include the following steps:
first, a substrate 208, such as a P-type single crystal silicon substrate 208, is provided, and an active region is defined on the silicon substrate 208.
Fig. 3 shows a key layout diagram of a global shutter image sensor unit for manufacturing the present embodiment, which indicates the layout positions of the main devices. Wherein reticle 301 is the active region for forming the primary devices. Outside the active area 301 is a shallow trench isolation STI. Reticle 302 is a polysilicon gate used to form the gates of global transistor 206, transfer transistor 203, reset transistor 202, source follower 204, and row select transistor 205. The reticle 303 is N+Ion implantation region for N+Lead out, including the shape of the floating diffusion region 207And (4) obtaining. The layout levels of the other reticles are not labeled in fig. 3.
Wherein, unlike a conventional global shutter image sensor cell, N of the floating diffusion region 207+The implanted region 303 is bounded within the active region 301, i.e., has a gap L.
P at low doping concentration based on the layout of FIG. 3-On a type monocrystalline silicon substrate 208, a P-well, a photodiode 201, a floating diffusion 207, a global transistor 206, a transfer transistor 203, and a reset transistor 202, a source follower 204, and a row select transistor 205 of a readout circuit may be formed using conventional image sensor process flow. A schematic cross-sectional view of the global shutter image sensor unit cut and formed in the X direction in fig. 3 is shown in fig. 4.
The floating diffusion region 207 uses a high concentration of N+Type doping, wherein the N type doping ion can be V group element ion such as phosphorus, arsenic, etc. or their mixture, and the doping concentration can be 1017cm-3To 1020cm-3. The floating diffusion region 207 may be formed to a junction depth of 0.2 microns to 0.5 microns.
Please refer to fig. 5-8. High concentration P can be formed simultaneously in the bottom region of the signal storage node of the N-type floating diffusion region 207 and the edge region (gap L) near the STI of the shallow trench isolation region by photolithography, ion implantation, annealing, etc+And a type protection area 209. Since the doping types of the floating diffusion region 207 and the protection region 209 are opposite, PN junction isolation is formed.
FIG. 5 is P of the present embodiment+The lithography layout of the isolation protected area 209. Wherein, P+There is an overlap region (gap L) between the isolation implant reticle 304 and the active region reticle 301 at the floating diffusion region 207. Preferably, the width of the overlap region is 0.05 microns to 0.5 microns. Form P+The specific process steps of the isolation protection region 209 may be:
carry out P+And (5) isolating and photoetching. By P+The isolation implant reticle 304 protects the center region and other regions of the floating diffusion region 207 with photoresist and opens only the edge regions of the floating diffusion region 207 to form a lithography window. According toDefinition of the reticle, preferably, P+The width of the overlap between the isolation lithographically opened region and the active region 301 at the floating diffusion region 207 may be 0.05 microns to 0.5 microns.
And performing tilt angle ion implantation. Fig. 6 and 7 are schematic diagrams of ion implantation under protection of photoresist, and are schematic diagrams of cross-sectional structures formed by cutting along the X direction and cutting along the Y direction in fig. 5, respectively. The implanted ions may be P-type impurities of group III elements, preferably boron. The implantation energy can be 30keV to 120keV, and the doping concentration can be 1017cm-3To 1019cm-3. The injection mode is an inclination angle, and the preferred angle is 10 degrees to 45 degrees. By the tilt angle implantation, P-type impurities can be simultaneously implanted into the edge gap L of the floating diffusion region 207 and the lower region of the bottom of the floating diffusion region 207.
And removing the photoresist and annealing. The implanted P-type impurity is activated by annealing.
Please refer to fig. 8, which is the completion P+The cross-sectional structure of the isolated protection region 209 along the X-direction in fig. 5 is shown. P is formed simultaneously under the edge and bottom of the floating diffusion region 207 by angled ion implantation and annealing+The isolation protection region 209 and the N-type floating diffusion region 207 form a PN junction, which can effectively prevent the influence of the STI edge of the shallow trench isolation region, reduce the leakage, and effectively isolate the influence of the noise and the leakage of the silicon substrate 208 on the storage node of the floating diffusion region 207.
Finally, the conventional process flow can be adopted to complete the subsequent processes of metal interconnection and the like.
In summary, with the optimized process for manufacturing the global shutter image sensor unit provided in this embodiment, only one step P is added on the basis of the conventional 5T global image sensor unit+Isolation lithography and implant, creatively using angled ion implantation, forms P simultaneously under the edge and bottom of floating diffusion region 207+The process is simple by isolating the protection region 209. Furthermore, by tilt angle ion implantation, an isolation protection region 209 is formed at the edge and bottom of the floating diffusion region 207 to form a PN junction with the floating diffusion region 207, thereby effectively preventing the formation of a void in the floating diffusion region 207The floating-stop diffusion region 207 is affected by the STI edge, so as to reduce the leakage, and effectively isolate the noise and leakage of the substrate 208 from the influence on the storage node of the floating diffusion region 207.
The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. An image sensor unit, comprising: the photodiode and the floating diffusion region which are formed on an active region of a substrate and are connected with each other, and a shallow slot isolation region formed on the boundary of the active region, wherein a gap is formed between the boundary of the floating diffusion region and the boundary of the shallow slot isolation region, a first protection region is formed in the gap, the first protection region has a doping type opposite to that of the floating diffusion region, forms a PN junction with the floating diffusion region and is used for isolating the floating diffusion region from the shallow slot isolation region, and/or a second protection region is formed at the bottom of the floating diffusion region, has a doping type opposite to that of the floating diffusion region, forms a PN junction with the floating diffusion region and is used for isolating the floating diffusion region from the substrate.
2. The image sensor cell of claim 1, wherein the first protective region is connected to the second protective region.
3. The image sensor cell of claim 1, wherein the second guard region has a same doping type as the substrate, and a doping concentration of the second guard region is higher than a doping concentration of the substrate.
4. The image sensor cell of claim 1, wherein the gap has a width of 0.05 to 0.5 microns.
5. The image sensor unit of claim 1, further comprising: a global transistor, a transfer transistor, a reset transistor, a source follower, and a row select transistor formed on an active region of the substrate; wherein one side of the photodiode is connected to a power supply voltage through the global transistor, the other side of the photodiode is connected to the floating diffusion region through the transfer transistor, and the floating diffusion region is connected to a signal output terminal through the reset transistor, the source follower, and the row select transistor.
6. An image sensor cell fabrication method, comprising:
providing a substrate, defining an active region on the substrate, forming a photodiode and a floating diffusion region which are connected on the active region, and forming a shallow slot isolation region which surrounds the active region on the boundary of the active region; wherein a gap is arranged between the boundary of the floating diffusion region and the boundary of the shallow trench isolation region;
forming a lithographic window over the gap;
performing ion implantation of the opposite doping type of the substrate to the floating diffusion region through the photoetching window in an inclined angle implantation mode, and simultaneously implanting impurities into the gap at the edge of the floating diffusion region and below the bottom of the floating diffusion region;
and annealing to form a protective region in the gap and below the bottom of the floating diffusion region.
7. The image sensor cell preparation method of claim 6, further comprising:
forming a global transistor, a transmission transistor, a reset transistor, a source follower and a row selection transistor on the active region, connecting one side of the photodiode with the global transistor, connecting the other side of the photodiode with the floating diffusion region through the transmission transistor, and connecting the floating diffusion region with the reset transistor, the source follower and the row selection transistor.
8. The method of manufacturing an image sensor cell according to claim 6, wherein the width of the gap is 0.05 to 0.5 μm.
9. The method of manufacturing an image sensor cell according to claim 6, wherein a doping concentration at the time of tilt angle implantation is made higher than a doping concentration of the substrate.
10. The method of manufacturing an image sensor unit according to claim 6, wherein the inclination angle is 10 degrees to 45 degrees with respect to a vertical direction.
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