CN116207120A - Image sensor and manufacturing method thereof - Google Patents

Image sensor and manufacturing method thereof Download PDF

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Publication number
CN116207120A
CN116207120A CN202310484402.2A CN202310484402A CN116207120A CN 116207120 A CN116207120 A CN 116207120A CN 202310484402 A CN202310484402 A CN 202310484402A CN 116207120 A CN116207120 A CN 116207120A
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well region
substrate
image sensor
shallow trench
trench isolation
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CN116207120B (en
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徐玉婷
林政纬
杨智强
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Nexchip Semiconductor Corp
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Nexchip Semiconductor Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14625Optical elements or arrangements associated with the device
    • H01L27/14627Microlenses
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/1464Back illuminated imager structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685Process for coatings or optical elements
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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Abstract

The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor includes: a substrate; the shallow trench isolation structures are arranged in the substrate and divide the substrate into a plurality of photosensitive areas, and the photosensitive areas are distributed on the substrate in an array manner; the first well region is arranged in the photosensitive region; the second well region is arranged on the first well region, and the distance from the second well region to the shallow trench isolation structure is smaller than the distance from the first well region to the shallow trench isolation structure; and a plurality of switches disposed on the substrate. The image sensor and the manufacturing method thereof provided by the invention have the advantages that the production efficiency and performance of the image sensor are improved.

Description

Image sensor and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an image sensor and a manufacturing method thereof.
Background
The image sensor can convert an optical signal into an electrical signal, wherein the CMOS image sensor (CMOS Image Sensors, CIS) has advantages of high integration level, low power supply voltage, low technical threshold and the like, and is widely applied to fields such as photography and photography, security and protection systems, intelligent mobile phones, fax machines, scanners, medical electronics and the like. Therefore, the requirement for image quality is also higher and higher, and dark current is one of the main causes of deterioration of the image sensor, wherein one of the main sources of dark current is dangling bond on the surface of the photosensitive area.
Disclosure of Invention
The invention aims to provide an image sensor and a manufacturing method thereof, by which the manufacturing cost of the image sensor can be reduced, the production efficiency can be improved, and the performance of the image sensor can be improved.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides an image sensor, which at least comprises:
a substrate;
the shallow trench isolation structures are arranged in the substrate and divide the substrate into a plurality of photosensitive areas, and the photosensitive areas are distributed on the substrate in an array manner;
the first well region is arranged in the photosensitive region;
the second well region is arranged on the first well region, and the distance from the second well region to the shallow trench isolation structure is smaller than the distance from the first well region to the shallow trench isolation structure; and
a plurality of switches disposed on the substrate.
In an embodiment of the present invention, the second well region covers the first well region, and a predetermined distance exists between an edge of the second well region and an edge of the first well region.
In an embodiment of the present invention, the predetermined distance is 70 a to 90 a.
In an embodiment of the present invention, the depth of the second well region is one fiftieth to one eighth of the depth of the first well region.
In an embodiment of the present invention, a depth of the first well region is greater than or equal to a depth of the shallow trench isolation structure.
In an embodiment of the invention, the image sensor includes an isolation well region and a deep well region, the isolation well region wraps the shallow trench isolation structure, the deep well region is disposed at the bottom of the first well region, and the depth of the deep well region is equal to the depth of the isolation well region.
Another object of the present invention is to provide a method for manufacturing an image sensor, including:
providing a substrate;
forming a plurality of shallow trench isolation structures in the substrate, wherein the shallow trench isolation structures divide the substrate into a plurality of photosensitive areas, and the photosensitive areas are distributed on the substrate in an array manner;
forming a first well region in the photosensitive region;
forming a second well region on the first well region, wherein the distance from the second well region to the shallow trench isolation structure is smaller than the distance from the first well region to the shallow trench isolation structure; and
a plurality of switches is formed on the substrate.
In an embodiment of the present invention, the method for manufacturing the first well region and the second well region includes the following steps:
forming a photoresist layer on the substrate, and forming a first concave part on the photoresist layer;
injecting first type impurity ions by taking the photoresist layer with the first concave part as a mask to form a first well region;
trimming the photoresist layer, expanding the opening area of the first concave part, and forming a second concave part; and
and implanting second-type impurity ions by taking the photoresist layer with the second concave part as a mask to form a second well region, wherein the types of the second-type impurity ions are different from those of the first-type impurity ions.
In an embodiment of the present invention, the method for forming the second recess includes:
placing the substrate with the photoresist layer of the first recess into a reaction chamber; and
and after the reaction gas is plasmatized, introducing the reaction gas into a reaction chamber to trim the photoresist layer so as to enlarge the opening area of the first concave part and form the second concave part.
In an embodiment of the present invention, the reaction gas includes one or more of oxygen, argon, and a fluorine-containing gas, and the fluorine-containing gas includes one or more of nitrogen trifluoride, carbon tetrafluoride, trifluoromethane, and hexafluoroethane.
In summary, the present invention provides an image sensor and a method for manufacturing the same, which can improve isolation effect between photodiodes, reduce mutual interference between photodiodes, reduce dark current of the image sensor, and improve performance of the image sensor. The adverse effect caused by surface lattice defects can be reduced, and dark current can be reduced. Meanwhile, in the manufacturing process, a photoresist process is saved, the production cost can be reduced, meanwhile, the manufacturing process is simplified, the time is saved, and the production efficiency is improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an array of image sensors in an embodiment.
Fig. 2 is a cross-sectional view of fig. 1 in which a first photoresist layer is formed along A-A.
Fig. 3 is a cross-sectional view of fig. 1 with shallow trenches formed in the A-A direction.
Fig. 4 is a cross-sectional view of the shallow trench isolation structure formed along the A-A direction of fig. 1.
Fig. 5 is a cross-sectional view of the deep well region and the isolation well region formed along the A-A direction of fig. 1.
Fig. 6 is a cross-sectional view of fig. 1 along A-A forming a first recess in a second photoresist layer.
Fig. 7 is a cross-sectional view of the first well region formed along the A-A direction of fig. 1.
Fig. 8 is a cross-sectional view of the first recess trimmed in the direction A-A of fig. 1 to form a second recess.
Fig. 9 is a cross-sectional view of fig. 1 in which a second well region is formed along A-A.
Fig. 10 is a cross-sectional view of the dielectric layer formed in the direction B-B of fig. 1.
Fig. 11 is a cross-sectional view of the switch of fig. 1 formed in the direction B-B.
Fig. 12 is a cross-sectional view of the sidewall structure of fig. 1 formed along the direction B-B.
Description of the reference numerals:
100. an image sensor; 10. a substrate; 101. a first region; 102. a second region; 11. a pad oxide layer; 12. pad nitriding layer; 13. a first photoresist layer; 131. a first opening; 14. shallow trench isolation structures; 141. a shallow trench; 15. a second photoresist layer; 151. a first concave portion; 152. a second concave portion; 16. a first well region; 17. a second well region; 18. a dielectric layer; 19. a side wall structure; 20. a pixel unit; 21. a deep well region; 22. an isolation well region; 110. a charge integration switch; 120. a reset switch; 130. and a signal amplifying switch.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present invention, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
According to the image sensor and the manufacturing method thereof, the number of the suspension bonds on the upper surface of the photosensitive area can be reduced by preparing the high-performance image sensor, the performance of the image sensor is improved, and the production cost is reduced. The image sensor provided by the invention can be widely applied to the fields of photography and photography, security systems, intelligent portable phones, fax machines, scanners, medical electronics and the like.
Referring to fig. 1, in an embodiment of the present invention, a plurality of pixel units 20 are disposed on an image sensor 100, a photodiode is disposed in each pixel unit 20 to form a pixel point, and the plurality of pixel units 20 form a two-dimensional pixel array. In the use process, the object is focused on the pixel array of the image sensor 100 through the imaging lens, each photodiode converts the light intensity of the surface into an electric signal, and the control circuit electrically connected with the photodiodes selects the pixels needing to work, and reads out the electric signals on the pixels. And amplifying the electric signal, denoising and outputting the electric signal.
Referring to fig. 1, in an embodiment of the present invention, on each pixel unit 20, the photosensitive regions are arranged in a hexagonal shape, and a first region 101 and a second region 102 are formed on one side of the photosensitive region. The first area 101 is disposed at one side of the photosensitive area and is disposed in contact with the photosensitive area. In this embodiment, the first area 101 is disposed in an "L" shape, for example, and in other embodiments, the first area 101 may be disposed in other shapes. The second area 102 and the first area 101 are disposed on the same side of the photosensitive area, and the second area 102 is disposed, for example, in a rectangular shape, and the second area 102 is disposed, for example, perpendicular to one end of the first area 101. A control structure is formed on the substrate 10, and includes, for example, a charge integration switch 110, a reset switch 120, and a signal amplification switch 130, wherein the charge integration switch 110 is disposed at the junction of the photosensitive region and the first region 101, the signal amplification switch 130 is disposed on the first region 101, and the reset switch 120 is disposed on the second region 102. During operation of the pixel cell 20, the reset switch 120 may first be controlled to open the reset tube to reset the photodiode. Then sampling is performed, the reset switch 120 is turned off, and the charge integration switch 110 is turned on, so that the photodiode works to generate charges, and an electrical signal is formed to output. When the signal amplification switch 130 is turned on, the electrical signal on the pixel can be amplified.
Referring to fig. 1-2, in an embodiment of the present invention, fig. 2 is a cross-sectional view along A-A of fig. 1. In the present embodiment, the manufacturing process of the image sensor is described by taking a Photodiode (PD) in one pixel unit 20 as an example. First, a substrate 10 is provided, where the substrate 10 may be any suitable semiconductor material, for example, a substrate such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, or silicon wafer, and a stacked structure formed by these semiconductors, or be silicon on insulator, silicon germanium on insulator, and germanium on insulator, which may be specifically selected according to the manufacturing requirements of the image sensor. In the present embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate with an epitaxial structure, and the epitaxial structure is, for example, a homoepitaxial layer. In other embodiments, substrate 10 may be selected from other semiconductor materials, while a doped or undoped semiconductor substrate may be selected.
Referring to fig. 2, in an embodiment of the present invention, a pad oxide layer 11 is formed on a substrate 10, and the pad oxide layer 11 is made of a dense silicon oxide, for example, and the pad oxide layer 11 may be formed on the substrate 10 by a dry oxygen oxidation method, a wet oxygen oxidation method, an In situ vapor deposition method (In-Situ Steam Generation, ISSG), or a chemical vapor deposition (Chemical Vapor Deposition, CVD) method, for example. In this embodiment, the substrate 10 is placed in a furnace tube with a temperature of, for example, 900 ℃ to 1150 ℃, oxygen is introduced into the furnace tube, and the substrate 10 reacts with the oxygen at a high temperature to generate a dense pad oxide layer 11. The thickness of the pad oxide layer 11 is, for example, 10nm to 50nm, specifically, 10nm, 20nm, 30nm, 40nm, 50nm, or the like.
Referring to fig. 2, in an embodiment of the present invention, after the pad oxide layer 11 is formed, a pad nitride layer 12 is formed on the pad oxide layer 11, where the pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide, and in this embodiment, the pad nitride layer 12 is, for example, silicon nitride. Wherein the pad oxide layer 11 serves as a buffer layer to improve the stress between the substrate 10 and the pad nitride layer 12. In the present invention, the pad nitride layer 12 may be formed on the pad oxide layer 11 by, for example, low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD). Specifically, for example, the substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia gas, and the pad nitride layer 12 is deposited by reacting at a pressure of, for example, 2t to 10t and a temperature of, for example, 700 ℃ to 800 ℃. And the thickness of the pad nitride layer 12 can be adjusted by controlling the heating time, and in some embodiments, the thickness of the pad nitride layer 12 is, for example, 40nm to 120nm, specifically, for example, 60nm, 80nm, 100nm, 120nm, etc. The pad nitride layer 12 may protect the substrate 10 from damage during etching.
Referring to fig. 2, in an embodiment of the present invention, a first photoresist layer 13 is formed on the pad nitride layer 12, for example, by spin coating. The first photoresist layer 13 is exposed and developed, and a first opening 131 is formed on the first photoresist layer 13 to locate the shallow trench isolation structure.
Referring to fig. 2 to 3, in an embodiment of the present invention, fig. 3 is a cross-sectional view taken along A-A of fig. 1. After the first photoresist layer 13 is formed, the first photoresist layer 13 with the first opening 131 is used as a mask, and etching is performed in the direction of the substrate 10, so as to remove the pad nitride layer 12, the pad oxide layer 11 and part of the substrate 10 exposed by the first opening 131, thereby forming the shallow trench 141. In the present embodiment, for exampleThe shallow trench 141 is selectively formed by dry etching, and the etching gas includes, for example, chlorine (Cl) 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) And hydrogen bromide (HBr) or the like, or a mixture thereof with oxygen (O 2 ) Is a combination of (a) and (b).
Referring to fig. 3 to 4, in an embodiment of the present invention, fig. 4 is a cross-sectional view of fig. 1 in A-A direction. An insulating medium is deposited within shallow trench 141 to form shallow trench isolation structure 14. Specifically, an insulating medium is deposited within shallow trench 141 until the surface of pad nitride layer 12 is covered. Optionally, the substrate 10 may be annealed in an oxygen atmosphere prior to depositing the insulating medium to form an inner liner oxide layer (not shown) in the shallow trench 141 to reduce leakage. The invention is not limited to the deposition of the insulating medium, and the corresponding insulating medium can be formed by, for example, high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor deposition (High Aspect Ratio Process CVD, HARP-CVD). After the insulating medium is deposited, a high temperature (e.g., 800-1200 ℃) tempering process may be performed to increase the density and stress of the insulating medium. The insulating medium is, for example, silicon oxide with high adaptability to the grinding tool, and in other embodiments, the insulating medium may be an insulating material such as fluorosilicone glass.
Referring to fig. 3 to 4, in an embodiment of the present invention, after forming the insulating medium, the insulating medium is subjected to a planarization process, for example, a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process is used to planarize the insulating medium and a portion of the pad nitride layer 12, so that the heights of the insulating medium and the pad nitride layer 12 are uniform. The pad nitride layer 12 after polishing is then etched and removed, and the invention is not limited to the method of removing the pad nitride layer 12, for example, dry etching, wet etching, or the like. In this embodiment, for example, wet etching is performed with an acid solution, specifically, phosphoric acid with a volume fraction of, for example, 85% -88%, and the pad nitride layer 12 is etched at, for example, 150 ℃ -165 ℃ to form the shallow trench isolation structure 14. After the pad nitride layer 12 is removed, a step is formed between the pad oxide layer 11 and the shallow trench isolation structure 14, and the step height is, for example, 10nm to 20nm.
Referring to fig. 4 to 5, in an embodiment of the present invention, fig. 5 is a cross-sectional view taken along A-A of fig. 1, and after forming the shallow trench isolation structure 14, ion implantation is performed into the substrate 10 to form a plurality of well regions. First, in the substrate 10 between the shallow trench isolation structures 14, impurity ions are implanted with high implantation energy to form deep well regions 21, wherein the impurity ions are P-type impurities such as boron (B), and the depth of the deep well regions 21 is greater than the depth of the shallow trench isolation structures 14. Ion implantation is performed around the shallow trench isolation structure 14 to form an isolation well region 22, the depth of the isolation well region 22 is the same as that of the deep well region 21, and the isolation well region 22 wraps the shallow trench isolation structure 14 so as to prevent the photodiode depletion region from widening towards the isolation structure interface and reduce dark current caused by interface defects. Wherein, the deep well region 21 and the isolation well region 22 are used as isolation between photodiodes, thereby further improving the isolation effect between photodiodes and reducing the mutual interference between photodiodes.
Referring to fig. 5 to 6, in an embodiment of the present invention, fig. 6 is a cross-sectional view along A-A of fig. 1. After forming the deep well region 21 and the isolation well region 22, a second photoresist layer 15 is formed on the substrate 10, the second photoresist layer 15 is exposed and developed, and a first recess 151 is formed on the second photoresist layer 15 to locate a photodiode in a pixel cell. The first recess 151 and the shallow trench isolation structures 14 on both sides have a predetermined distance therebetween, and the edge of the first recess 151 is aligned with the edge of the isolation well region 22.
Referring to fig. 6 to 7, in an embodiment of the present invention, fig. 7 is a cross-sectional view taken along A-A of fig. 1. The first well region 16 is formed by implanting first type impurity ions into the substrate 10 using the second photoresist layer 15 having the first recess 151 as a mask and the pad oxide layer 11 as an ion implantation buffer layer. Wherein the first well region 16 is in contact with the isolation well regions 22 on both sides, and the bottom of the first well region 16 is in contact with the deep well region 21, and the depth of the first well region 16 is greater than or equal to the shallow trench isolationThe depth of the structure 14. In the present embodiment, the first type impurity ions are N-type impurities such As phosphorus (P) or arsenic (As), the implantation energy of the first type impurity ions is 190 KeV-220 KeV, and the doping concentration of the first well region 16 is 1×10 12 atoms/cm 2 ~5×10 12 atoms/cm 2 Also for example 2.4X10 12 atoms/cm 2
Referring to fig. 7 to 8, in an embodiment of the present invention, fig. 8 is a cross-sectional view taken along A-A of fig. 1. After the first well region 16 is formed, the second photoresist layer 15 is trimmed, and a portion of the photoresist layer on the side surface of the first recess 151 is removed to enlarge the opening area, thereby forming the second recess 152. In this embodiment, the substrate 10 with the first recess 151 is placed in a reaction chamber, and a reaction gas, such as nitrogen trifluoride (NF), is plasmatized and then introduced into the reaction chamber, wherein the reaction gas includes one or a mixture of oxygen, argon, or a fluorine-containing gas 3 ) Carbon tetrafluoride (CF) 4 ) Trifluoromethane (CHF) 3 ) Or hexafluoroethane (C) 2 F 6 ) And the like. The plasma is firstly ionized and then is introduced into the reaction chamber, and the plasma has lower energy. During the trimming process of the first recess 151, the temperature of the reaction chamber is, for example, 100 ℃ to 200 ℃, and the etching rate is low due to the low reaction temperature and low energy, and the second photoresist layer 15 is slightly etched in the longitudinal direction and the transverse direction, and the reaction formula is: o (O) 2 +C x H y O z →CO 2 +H 2 And 0, the second photoresist layer 15 is enlarged in the exposed area, and the second concave part 152 is formed so as to meet the requirement of forming a second well region, and meanwhile, one photoresist process is saved, the production cost can be reduced, the manufacturing process is simplified, the time is saved, and the production efficiency is improved.
Referring to fig. 8 to 9, in an embodiment of the present invention, fig. 9 is a cross-sectional view taken along A-A of fig. 1. After the second recess 152 is formed, the distance from the edge of the second recess 152 to the edge of the first well region 16 is, for example, 70 a to 90 a, and is, for example, 75 a, 80 a, 85 a or 90 a, so as to control the size of the second well region. To be provided with a secondThe second photoresist layer 15 of the recess 152 is used as a mask, the pad oxide layer 11 is used as an ion implantation buffer layer, second type impurity ions are implanted into the substrate 10 to form a second well region 17, and the second well region 17 is in contact with the second photoresist layer 15. In the present embodiment, the second type impurity ion is, for example, boron (B) or boron fluoride ion (BF 2 + ) The P-type impurity is such that the implantation energy of the second-type impurity ion is 15 KeV-20 KeV, and the doping concentration of the second well region 17 is 1×10 12 atoms/cm 2 ~2×10 12 atoms/cm 2 Also for example 1.4X10 12 atoms/cm 2 I.e. the second well region 17 is formed on the first well region 16, the depth of the second well region 17 being for example one fiftieth to one eighth of the depth of the first well region 16. The distance from the second well region 17 to the shallow trench isolation structure 14 is smaller than the distance from the first well region 16 to the shallow trench isolation structure 14, and the distance from the edge of the second well region 17 to the edge of the first well region 16 is a predetermined distance, for example, 70 a-90 a. By providing the second well region 17 to cover the first well region 16, and the area of the second well region 17 is larger than that of the first well region 16, the photosensitive region moves down to reduce adverse effects caused by surface lattice defects. Meanwhile, in the ion implantation process, the pad oxide layer 11 also prevents damage caused by high-energy bombardment, so that dark current of the image sensor is further reduced, and performance of the image sensor is improved.
Referring to fig. 1 and 9, in an embodiment of the invention, the doping concentration of the second well region 17 is smaller than that of the first well region 16, so as to form a built-in electric field directed from the first well region 16 to the second well region 17, and under the effect of the built-in electric field, signal electrons generated in the second well region 17 diffuse into the first well region 16, reducing charge accumulation in the second well region 17, and the generated charges are transferred to the charge integration switch 110 through the first well region 16. The second well region 17 and the first well region 16 form a photodiode, so that when the image sensor works, the photodiode is ensured to convert an optical signal into an electric signal, transmission of signal electrons is promoted, adverse effects caused by a transmission edge barrier are eliminated, and image tailing is reduced.
Referring to fig. 9 to 10, in an embodiment of the inventionFig. 10 is a cross-sectional view of fig. 1 in the direction B-B. After the second well region 17 is formed, the pad oxide layer 11 on the substrate 10 is removed. The pad oxide layer 11 is removed by wet etching, for example, and an etching liquid of the wet etching is, for example, a buffer oxide etching liquid (Buffered Oxide Etch, BOE) or hydrofluoric acid, or the like. After removal of the pad oxide, a dielectric layer 18 is formed on the substrate 10, wherein the dielectric layer 18 is, for example, a silicon oxide layer. Dielectric layer 18 is formed by, for example, a dry oxygen oxidation method, a vapor oxidation method, a wet oxygen oxidation method, or the like. In this embodiment, the substrate 10 is placed in a reaction chamber, such as a furnace, the pressure in the furnace is controlled to be 10T-20T, the furnace is heated to 750-1000 ℃, such as 800 ℃, and a small amount of hydrogen (H) 2 ) Oxygen (O) 2 ). The hydrogen and oxygen form a mixture of substances such as water vapor, OH radicals, O radicals, etc. at high temperature and low pressure, and the reaction product of the hydrogen and oxygen does not react with the shallow trench isolation structure 14, so that the substances such as water vapor, OH radicals, O radicals, etc. generated by the reaction of the hydrogen and oxygen react only with silicon on the surface of the substrate 10, thereby forming the dielectric layer 18. By reforming the silicon oxide layer, the quality of the dielectric layer 18 is improved, and leakage of the switch formed later can be reduced.
Referring to fig. 1, 10 and 11, in an embodiment of the present invention, fig. 11 is a cross-sectional view of fig. 1 in the direction B-B. After forming the dielectric layer 18, a polysilicon layer (not shown) is formed on the dielectric layer 18, and a photoresist is coated on the polysilicon layer, and a portion of the photoresist is removed by exposure and development to form a patterned photoresist (not shown). Wherein the patterned photoresist layer covers the locations where the charge integration switch 110, the reset switch 120, and the signal amplification switch 130 are formed. The polysilicon layer in other areas except the charge integration switch 110, the reset switch 120 and the signal amplification switch 130 is removed by using the patterned photoresist layer as a mask, so as to form the charge integration switch 110, the reset switch 120 and the signal amplification switch 130. The charge integration switch 110 is disposed on the second well region 17 of the photodiode and is close to the junction of the photosensitive region and the first region 101. The signal amplifying switch 130 is disposed on the first region 101 and near one side of the second region 102. The reset switch 120 is disposed on the second area 102 and located in the middle of the second area 102, and the central axis of the reset switch 120 and the central axis of the signal amplifying switch 130 are located on the same line.
Referring to fig. 1, 11-12, fig. 12 is a cross-sectional view of fig. 1 in the direction B-B in an embodiment of the invention. After the control structure is formed, sidewall structures 19 are formed on both sides of the charge integration switch 110, the reset switch 120, and the signal amplification switch 130. Specifically, a sidewall dielectric layer (not shown) is formed on the substrate 10, and the material of the sidewall dielectric layer is, for example, silicon oxide, silicon nitride or a stack of silicon oxide and silicon nitride. After forming the sidewall dielectric layer, a patterned photoresist layer (not shown in the figure) is formed on the sidewall dielectric layer, and the patterned photoresist layer is used as a mask, for example, an etching process such as dry etching may be used to remove the sidewall dielectric layers on the charge integration switch 110, the reset switch 120 and the signal amplifying switch 130 and on a part of the substrate 10, and the sidewall dielectric layers on two sides of the charge integration switch 110, the reset switch 120 and the signal amplifying switch 130 are reserved, so that a sidewall structure 19 is formed, and the height of the sidewall structure 19 is identical to the height of the switch. By providing the insulating side wall structure 19, the occurrence of the leakage phenomenon is prevented. In this embodiment, the shape of the sidewall structure 19 is, for example, arc, and in other embodiments, the shape of the sidewall structure 19 may be other shapes, which may be selected according to the manufacturing requirements. After the sidewall structure is formed, the metal silicide blocking layer, the interlayer dielectric, the microlens and other manufacturing processes are performed, and in this embodiment, any manufacturing process for forming the metal silicide blocking layer, forming the interlayer dielectric and the microlens may be used for manufacturing, which will not be described herein. In operation of the image sensor, each photodiode is connected to a floating region (not shown) with a corresponding charge integration switch 110, the photodiodes convert optical signals into electrical signals, and signal electrons are transferred to the floating region through the charge integration switch 110, thereby realizing conversion of optical signals into electrical signals.
In summary, the present invention provides an image sensor and a method for manufacturing the same, in which a photoresist layer is trimmed during the formation of a well region when a photodiode is formed, the opening range of a photoresist layer is enlarged, and a second well region is formed to cover a first well region, so that adverse effects caused by surface lattice defects can be reduced, and dark current can be reduced. Meanwhile, a photoresist process is saved, the production cost can be reduced, the manufacturing process is simplified, the time is saved, and the production efficiency is improved. The obtained image sensor can improve the isolation effect between the photodiodes, reduce the mutual interference between the photodiodes, reduce the dark current of the image sensor and improve the performance of the image sensor.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (10)

1. An image sensor, comprising:
a substrate;
the shallow trench isolation structures are arranged in the substrate and divide the substrate into a plurality of photosensitive areas, and the photosensitive areas are distributed on the substrate in an array manner;
the first well region is arranged in the photosensitive region;
the second well region is arranged on the first well region, and the distance from the second well region to the shallow trench isolation structure is smaller than the distance from the first well region to the shallow trench isolation structure; and
a plurality of switches disposed on the substrate.
2. The image sensor of claim 1, wherein the second well region covers the first well region, and wherein a predetermined distance exists from an edge of the second well region to an edge of the first well region.
3. The image sensor of claim 2, wherein the predetermined distance is 70-90 a.
4. The image sensor of claim 2, wherein the depth of the second well region is one fiftieth to one eighth of the depth of the first well region.
5. The image sensor of claim 1, wherein a depth of the first well region is greater than or equal to a depth of the shallow trench isolation structure.
6. The image sensor of claim 1, wherein the image sensor comprises an isolation well region and a deep well region, the isolation well region wraps the shallow trench isolation structure, the deep well region is disposed at the bottom of the first well region, and the depth of the deep well region is equal to the depth of the isolation well region.
7. A method for manufacturing an image sensor, comprising:
providing a substrate;
forming a plurality of shallow trench isolation structures in the substrate, wherein the shallow trench isolation structures divide the substrate into a plurality of photosensitive areas, and the photosensitive areas are distributed on the substrate in an array manner;
forming a first well region in the photosensitive region;
forming a second well region on the first well region, wherein the distance from the second well region to the shallow trench isolation structure is smaller than the distance from the first well region to the shallow trench isolation structure; and
a plurality of switches is formed on the substrate.
8. The method of fabricating an image sensor of claim 7, wherein the method of fabricating the first well region and the second well region comprises the steps of:
forming a photoresist layer on the substrate, and forming a first concave part on the photoresist layer;
injecting first type impurity ions by taking the photoresist layer with the first concave part as a mask to form a first well region;
trimming the photoresist layer, expanding the opening area of the first concave part, and forming a second concave part; and
and implanting second-type impurity ions by taking the photoresist layer with the second concave part as a mask to form a second well region, wherein the types of the second-type impurity ions are different from those of the first-type impurity ions.
9. The method of manufacturing an image sensor according to claim 8, wherein the method of forming the second concave portion includes:
placing the substrate with the photoresist layer of the first recess into a reaction chamber; and
and after the reaction gas is plasmatized, introducing the reaction gas into a reaction chamber to trim the photoresist layer so as to enlarge the opening area of the first concave part and form the second concave part.
10. The method of manufacturing an image sensor according to claim 9, wherein the reaction gas includes one or a mixture of several of oxygen, argon, and fluorine-containing gas including one or a mixture of several of nitrogen trifluoride, carbon tetrafluoride, trifluoromethane, and hexafluoroethane.
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