CN117855228A - Image sensor and manufacturing method thereof - Google Patents
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- CN117855228A CN117855228A CN202211209863.0A CN202211209863A CN117855228A CN 117855228 A CN117855228 A CN 117855228A CN 202211209863 A CN202211209863 A CN 202211209863A CN 117855228 A CN117855228 A CN 117855228A
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Abstract
The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor includes: a substrate; a photodiode disposed within the substrate; a floating diffusion region disposed within the substrate, the floating diffusion region being disposed in parallel with the photodiode within the substrate; and a transfer gate disposed between the photodiode and the floating diffusion region, the transfer gate wrapping the photodiode or wrapping a portion of the photodiode, the transfer gate extending from the substrate surface into the substrate. The image sensor and the manufacturing method thereof provided by the invention improve the performance of the image sensor.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an image sensor and a manufacturing method thereof.
Background
The complementary metal oxide image sensor (Complementary Metal Oxide Semiconductor Contact Image Sensor, CMOS image sensor) has the advantages of high integration level, low power supply voltage, low technical threshold and the like, and is widely applied to the fields of photography and photography, security systems, consumer electronics, automatic driving, biological recognition, intelligent portable phones, fax machines, scanners, medical electronics and the like.
However, in applications in fields such as high sensitivity requirement and low-light night vision, the prior art is easy to generate image lag (image lag) due to the characteristics of large pixel size, deep injection depth, etc., which results in performance degradation of the CMOS image sensor, and cannot meet the use requirement.
Disclosure of Invention
The invention aims to provide an image sensor and a manufacturing method thereof, and the performance of the image sensor can be improved through the image sensor and the manufacturing method thereof.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides an image sensor, comprising at least:
a substrate;
a photodiode disposed within the substrate;
a floating diffusion region disposed within the substrate, the floating diffusion region being disposed in parallel with the photodiode within the substrate; and
a transfer gate disposed between the photodiode and the floating diffusion region, and the transfer gate wraps around the photodiode or a portion of the photodiode, the transfer gate extending from the substrate surface into the substrate.
In one embodiment of the present invention, the length of the transfer gate is 1/2 to 1 of the perimeter of the photodiode.
In an embodiment of the present invention, the transfer gate wraps at least two adjacent sides of the photodiode.
In one embodiment of the present invention, the transfer gate comprises a vertical gate disposed within an isolation structure outside the photodiode and in contact with the photodiode through a gate oxide.
In an embodiment of the present invention, a depth of the vertical gate is less than or equal to a depth of the photodiode.
In an embodiment of the present invention, the transfer gate includes a planar gate, and the planar gate covers a portion of the isolation structure outside the photodiode and extends onto the photodiode to cover a portion of the photodiode.
Another object of the present invention is to provide a method for manufacturing an image sensor, at least comprising the following steps:
providing a substrate;
forming a photodiode within the substrate;
forming a floating diffusion region in the substrate, wherein the floating diffusion region and the photodiode are arranged in parallel in the substrate; and
a transfer gate is formed between the photodiode and the floating diffusion region, and wraps around the photodiode or around a portion of the photodiode, the transfer gate including a vertical gate extending from the substrate surface into the substrate.
In an embodiment of the present invention, the method further includes:
forming a first sacrificial layer on the substrate;
forming a second sacrificial layer on the first sacrificial layer;
etching the second sacrificial layer, the first sacrificial layer and part of the substrate to form a groove; and
and depositing an isolation medium in the groove to form an isolation structure, wherein the isolation structure is flush with the second sacrificial layers on two sides.
In an embodiment of the present invention, a horizontal channel of the transfer gate is formed between the photodiode and the floating diffusion region, and the isolation structures are disposed on two sides of the horizontal channel.
In an embodiment of the present invention, the method further includes:
forming a photoresist layer on the second sacrificial layer and the isolation structure, wherein the photoresist layer exposes the horizontal channel of the transfer gate, part of the isolation structure on two sides of the horizontal channel, the photodiode covered by the transfer gate and the isolation structure covered by the transfer gate; and
and taking the photoresist layer and part of the second sacrificial layer on the substrate as masks, and etching the isolation structure in a self-aligned manner to form a groove.
In an embodiment of the present invention, the method further includes:
after forming the groove, removing the second sacrificial layer; and
and forming a first well region and a second well region in the substrate by taking the first sacrificial layer as an ion implantation buffer layer, wherein the second well region is arranged on the first well region so as to form a photodiode.
In an embodiment of the present invention, the method further includes:
removing the first sacrificial layer;
forming a gate oxide layer on the substrate and the exposed surface of the substrate of the groove;
forming a gate material layer in the recess and on the substrate; and
and removing part of the gate material layer on the substrate to form the transfer gate.
In summary, the image sensor and the manufacturing method thereof provided by the invention can self-align the position of the vertical grid electrode, reduce the etching damage of the horizontal channel of the transfer grid electrode, and reduce the dark current. And electrons in the photodiode are fully transferred, so that the image residual shadow phenomenon is reduced, and the full well capacity of the image sensor is improved. The mutual interference between the photodiodes can be reduced, and the definition is improved. And the structure of the transfer grid can be applied to image sensors with various pixel structure changes, so that the performance of the image sensor is improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an image sensor according to an embodiment.
Fig. 2 is a schematic diagram of an image sensor according to another embodiment.
Fig. 3 is a schematic diagram of an image sensor according to another embodiment.
Fig. 4 is a schematic perspective view of a transfer gate according to an embodiment.
Fig. 5 is a schematic view of the isolation structure formed in the A-A direction of fig. 3.
Fig. 6 is a schematic view of the isolation structure formed in the direction B-B of fig. 3.
FIG. 7 is a schematic view of the isolation structure formed in the direction D-D of FIG. 3.
Fig. 8 is a top view of an isolation structure and active area on a substrate.
FIG. 9 is a schematic diagram of the second photoresist layer formed in the A-A direction in FIG. 3.
FIG. 10 is a schematic diagram of the second photoresist layer formed in the B-B direction in FIG. 3.
FIG. 11 is a schematic diagram of the second photoresist layer formed in the direction D-D in FIG. 3.
Fig. 12 is a schematic view of fig. 3 in a direction A-A to form a first groove.
Fig. 13 is a schematic view of forming a second groove in the direction B-B of fig. 3.
Fig. 14 is a schematic view of forming a second groove in the direction D-D of fig. 3.
Fig. 15 is a schematic view of the well region formed in the B-B direction of fig. 3.
Fig. 16 is a schematic view of the well region formed in the D-D direction of fig. 3.
Fig. 17 is a schematic diagram of forming a gate oxide layer in A-A direction in fig. 3.
Fig. 18 is a schematic view of forming a gate oxide layer in the B-B direction of fig. 3.
Fig. 19 is a schematic view of the gate oxide layer formed in the direction D-D in fig. 3.
Fig. 20 is a schematic view illustrating formation of a gate material layer and a third photoresist layer in A-A direction in fig. 3.
Fig. 21 is a schematic view of forming a gate material layer and a third photoresist layer in the B-B direction of fig. 3.
Fig. 22 is a schematic view of forming a gate material layer and a third photoresist layer in the D-D direction of fig. 3.
Fig. 23 is a schematic view of fig. 3 forming a transfer gate in the A-A direction.
Fig. 24 is a schematic view of the transfer gate formed in the direction B-B of fig. 3.
Fig. 25 is a schematic diagram of the transfer gate formed in the direction D-D of fig. 3.
Fig. 26 is a schematic view of the sidewall structure formed in the A-A direction in fig. 3.
Fig. 27 is a schematic view of forming a sidewall structure in the direction B-B in fig. 3.
Fig. 28 is a schematic view of forming a sidewall structure in the direction D-D in fig. 3.
Description of the reference numerals:
10. a substrate; 11. an isolation structure; 12. an active region; 13. a photodiode; 14. a floating diffusion region; 15. a transfer gate; 16. a reset tube; 17. a source follower; 18. a row selection tube; 110. a first sacrificial layer; 120. a second sacrificial layer; 130. a first photoresist layer; 131. a first opening; 132. a second opening; 140. a second photoresist layer; 141. a first concave portion; 142. a second concave portion; 150. a gate oxide layer; 151. a first groove; 152. a second groove; 153. a vertical gate; 154. a planar gate; 161. a gate material layer; 170. a third photoresist layer; 180. a side wall structure; 101. a first well region; 102. a second well region; 104. a first isolation well region; 105. and a second isolation well region.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present invention, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
As shown in fig. 1 to 3, the present invention is not limited in the kind of image sensor, for illustrating the present application, the image sensor provided in the present embodiment is, for example, a CMOS image sensor of a 4T structure, and the image sensor includes a photodiode 13, a floating diffusion region 14, a transfer gate 15, a reset tube 16, a source follower tube 17, and a row select tube 18, and the floating diffusion region 14, the reset tube 16, the source follower tube 17, and the row select tube 18 are disposed on a substrate 10. Wherein the photodiode 13 is in an off state with the transfer gate 15 during integration, and the transfer gate 15 is opened after the electron accumulation is completed, and the electron is transferred into the floating diffusion region 14 via the transfer gate 15 and is read out. The transfer grid 15 wraps or partially wraps the photodiode 13, electrons can be transferred into the floating diffusion region 14 in time, image hysteresis is reduced, the obtained CMOS image sensor is high in sensitivity, and the pixel size is large, so that the CMOS image sensor can be widely applied to fields of high sensitivity requirements, low-light night vision and the like.
As shown in fig. 1 to 4, in an embodiment of the present invention, the top structure of the transfer gate 15 is, for example, a "C", "L" or ring shape. The size of the transfer gate 15 is, for example, 1/2-1 of the circumference of the photodiode 13, and the transfer gate 15 wraps at least two adjacent sides of the photodiode 13. The transfer gate 15 includes a vertical gate, as shown in fig. 4, and the depth of the vertical gate is less than or equal to the depth of the photodiode 13, and electrons are transferred to the vertical gate nearby in the electron transfer process, and are transferred to the floating diffusion region 14 through the transfer gate 15 rapidly, so that electrons can be transferred completely, image sticking phenomenon is reduced, and full well capacity of the image sensor is improved.
Referring to fig. 5 to 7, in an embodiment of the present invention, fig. 5 is a cross-sectional view of fig. 3 in A-A direction, fig. 6 is a cross-sectional view of fig. 3 in B-B direction, and fig. 7 is a cross-sectional view of fig. 3 in D-D direction. In the present embodiment, a Photodiode (PD) in the image sensor is taken as an example, a process of manufacturing the image sensor is described, and a top view structure of the transfer gate is, for example, "C". First, a substrate 10 is provided, where the substrate 10 may be any suitable semiconductor material, for example, a substrate such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, or silicon wafer, and a stacked structure formed by these semiconductors, or be silicon on insulator, silicon germanium on insulator, and germanium on insulator, which may be specifically selected according to the manufacturing requirements of the image sensor. In the present embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate with an epitaxial structure, and the epitaxial structure is, for example, a homoepitaxial layer.
Referring to fig. 5 to fig. 7, in an embodiment of the present invention, a first sacrificial layer 110 is formed on a substrate 10, and the first sacrificial layer 110 is made of a material such as dense silicon oxide, for example, the first sacrificial layer 110 may be formed on the substrate 10 by a thermal oxidation method or an in situ vapor growth method. In this embodiment, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900-1150 ℃, oxygen is introduced into the furnace tube, the substrate 10 reacts with the oxygen at a high temperature to generate a dense first sacrificial layer 110, and the thickness of the first sacrificial layer 110 is, for example, 1-20 nm. After the first sacrificial layer 110 is formed, a second sacrificial layer 120 is formed on the first sacrificial layer 110, the second sacrificial layer 120 being, for example, silicon nitride or a mixture of silicon nitride and silicon oxide, and the second sacrificial layer 120 being, for example, silicon nitride in this embodiment. Wherein the first sacrificial layer 110 serves as a buffer layer to improve stress between the substrate 10 and the second sacrificial layer 120. In the present invention, the second sacrificial layer 120 may be formed on the first sacrificial layer 110 by, for example, low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD). In some embodiments, the thickness of the second sacrificial layer 120 is, for example, 10nm to 300nm, and is, for example, 110 nm. The second sacrificial layer 120 may protect the substrate 10 at the transfer gate horizontal channel from damage during etching.
Referring to fig. 5 to 7, in an embodiment of the invention, a first photoresist layer 130 is formed on the second sacrificial layer 120. A first opening 131 and a second opening 132 are provided on the first photoresist layer 130 through a process of exposure development or the like. Wherein the first opening 131 exposes a portion of the second sacrificial layer 120 in the direction of the portion A-A, the second opening 132 exposes a portion of the second sacrificial layer 120 in the directions of the portions B-B and D-D, and the first opening 131 and the second opening 132 are used to position the isolation structures at different positions. Taking the first photoresist layer 130 as a mask, quantitatively removing the second sacrificial layer 120 under the first photoresist layer 130 by using dry etching, wet etching or etching methods of combining dry etching and wet etching and the like, and quantitatively removing the first sacrificial layer 110 and part of the substrate 10 by taking the second sacrificial layer 120 as the mask to obtain a groove. In the present embodiment, for example, a shallow trench is formed by dry etching, and the etching gas is, for example, chlorine (Cl) 2 ) Fluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) Hydrogen bromide (HBr) or oxygen (O) 2 ) One or a combination of several of the following. EngravingAfter the etching is completed, the first photoresist layer 130 is removed, and the first photoresist layer 130 is removed, for example, by oxygen plasma removal or wet removal.
Referring to fig. 8 to 11, in an embodiment of the present invention, fig. 8 is a top view of an isolation structure and an active region, fig. 9 is a cross-sectional view of fig. 3 in A-A direction, fig. 10 is a cross-sectional view of fig. 3 in a B-B direction, and fig. 11 is a cross-sectional view of fig. 3 in a D-D direction. After forming the trench, an isolation medium, such as an insulating material, such as silicon oxide, is deposited in the trench, such as by high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor deposition (High Aspect Ratio Process CVD, HARP-CVD). After the isolation medium deposition is completed, a planarization process such as chemical mechanical polishing (Chemical Mechanical Polishing, CMP) is performed to place the isolation medium and the top of the second sacrificial layer 120 on the same plane, thereby forming a plurality of isolation structures 11. In the present embodiment, the depth of the isolation structure 11 in the well region is, for example, 200nm to 1100nm. By providing a plurality of isolation structures 11, the substrate 10 is divided into a region where the isolation structures 11 are located and an active region 12, and a photodiode or other semiconductor device or the like is provided over the active region 12. The plurality of photodiodes in the image sensor or other semiconductor devices are isolated by the isolation structure 11, so that the mutual interference among the semiconductor devices is reduced, and the performance of the image sensor is improved.
Referring to fig. 9 to 11, in an embodiment of the invention, after the isolation structure 11 is formed, a second photoresist layer 140 is formed on the second sacrificial layer 120 and the isolation structure 11, and a plurality of recesses are formed on the second photoresist layer 140 by exposing and developing processes to position the vertical gate. The recesses include a first recess 141 and a second recess 142, wherein the first recess 141 exposes a portion of the isolation structure 11 and the second sacrificial layer 120 between adjacent isolation structures 11 in the A-A direction. The second recess 142 exposes a portion of the isolation structure 11 and a portion of the second sacrificial layer 120 formed on the photodiode region in the B-B and D-D directions. I.e. the second photoresist layer 140 exposes the horizontal channel of the transfer gate in the A-A direction and isolation structures 11 on both sides of the horizontal channel, and the transfer gate wraps aroundAnd then taking the second photoresist layer 140 and the second sacrificial layer 120 as masks, quantitatively removing part of the isolation structure 11 by using self-aligned dry etching, wet etching or etching modes such as dry etching and wet etching combined with each other, and forming grooves. In the present embodiment, for example, a shallow trench is formed by dry etching, and the etching gas is, for example, tetrafluoromethane (CF) 4 ) One or a combination of a plurality of types of trifluoromethane, difluoromethane, nitrogen trifluoride, and the like, for example, a mixed gas of tetrafluoromethane and trifluoromethane, has a relatively large etching selectivity for the isolation structure 11 and the second sacrificial layer 120. After the etching is completed, the second photoresist layer 140 is removed, and the second photoresist layer 140 is removed, for example, by oxygen plasma removal or wet removal.
Referring to fig. 1, 12 to 14, in an embodiment of the present invention, fig. 12 is a cross-sectional view of fig. 3 in A-A direction, fig. 13 is a cross-sectional view of fig. 3 in B-B direction, and fig. 14 is a cross-sectional view of fig. 3 in D-D direction. The formed grooves include a first groove 151 and a second groove 152, wherein the first groove 151 is located at both sides of the transfer gate horizontal channel C and is located in the isolation structure 11. The second grooves 152 are in the isolation structures 11 on the same side of the photodiode 13 in the B-B direction and the D-D direction. In the etching process, the transfer gate horizontal channel C takes the second sacrificial layer 120 as a mask, self-aligned etching is realized in the etching process, and the hard mask blocks to ensure that the channel cannot be damaged by etching, so that dark current transfer is reduced. The depth of the grooves in the substrate 10 is, for example, 1-1000 nm, and the depth of the grooves can be selected according to different manufacturing requirements.
Referring to fig. 15 to 16, in an embodiment of the present invention, fig. 15 is a cross-sectional view of fig. 3 in the direction B-B, and fig. 16 is a cross-sectional view of fig. 3 in the direction D-D. After forming the recess, the second sacrificial layer 120 on the substrate 10 is removed, and the second sacrificial layer 120 is removed, for example, by a wet process, and a wet etching solution, for example, hot phosphoric acid or the like. After the second sacrificial layer 120 is removed, a portion of the isolation structure 11 is removed, and the isolation structure 11 is removed, for example, by a wet process, and a wet etching solution, for example, hydrofluoric acid, is used, and after the reaction is completed, the isolation structure 11 is level with the first sacrificial layers 110 on both sides. Then, ion implantation is carried out to form a plurality of well regions. First, impurity ions are implanted outside the isolation structure 11 to form a first isolation well region 104 and a second isolation well region 105, and the impurity ions of the first isolation well region 104 and the second isolation well region 105 are P-type impurities such as boron (B). In this embodiment, the first isolation well region 104 wraps the isolation structure 11, the second isolation well region 105 wraps the first isolation well region 104, and the doping concentration of the first isolation well region 104 is greater than that of the second isolation well region 105, so as to prevent the photodiode depletion region from widening towards the isolation structure interface, and reduce dark current caused by interface defects. The second isolation well region 105 serves as isolation between photodiodes, further improves isolation between photodiodes, and reduces mutual interference between photodiodes.
Referring to fig. 15 to 16, in an embodiment of the present invention, in the direction D-D of fig. 3, in the substrate 10 between the isolation structures 11, first type impurity ions are implanted into the buffer layer by using the first sacrificial layer 101 as an ion implantation buffer layer, so as to form a first well region 101, and the first well region 101 contacts with a second isolation well region 105 on one side. The first well region 101 is in contact with the second isolation well region 105 on one side in the B-B direction of fig. 3. Impurity ions of a second type are implanted on the first well region 101 at a low implantation energy to form a second well region 102, and the second well region 102 is formed on the first well region 101 due to the difference in implantation energy, i.e., the depth of the first well region 101 is greater than the depth of the second well region 102. Wherein the widths of the first well region 101 and the second well region 102 are equal, e.g. larger than 10 μm, i.e. the size of the photodiode is larger than 10 μm. The depth of the first well region 101 is smaller than the depth of the second isolation well region 105, and is, for example, one eighth to one tenth of the depth of the second isolation well region 105, and the second well region 102 is, for example, one eighth to one third of the depth of the first well region 101. In this embodiment, the first type impurity ion is different from the second type impurity ion, wherein the first type impurity ion is an N-type impurity such As phosphorus (P) or arsenic (As), and the second type impurity ion is a P-type impurity such As boron (B), that is, the doping types of the first well region 101 and the second well region 102 are different. In other embodiments, the first type impurity ions may be P-type impurities, and the second type impurity ions may be N-type impurities, which may be selected according to the manufacturing requirements of the image sensor. In this embodiment, the doping concentration of the formed second well region 102 is ensured to be greater than that of the first well region 101, a built-in electric field directed to the second well region 102 by the first well region 101 is formed, and by setting the second well region 102 with high doping concentration, the depletion region of the first well region 101 is prevented from widening towards the surface of the substrate 10, and dark current caused by dangling bonds on the surface of the substrate 10 is reduced.
Referring to fig. 17 to 19, in an embodiment of the present invention, fig. 17 is a cross-sectional view of fig. 3 in A-A direction, fig. 18 is a cross-sectional view of fig. 3 in B-B direction, and fig. 19 is a cross-sectional view of fig. 3 in D-D direction. After forming the isolation well region, the first sacrificial layer 110 and a portion of the isolation structure 11 on the substrate 10 are removed. And the first sacrificial layer 110 and the isolation structure 11 are removed, for example, by a wet process, and a wet etching solution, for example, hydrofluoric acid or the like, after the reaction is completed, the isolation structure 11 is flush with the substrate 10 on both sides. In other embodiments, removal may be performed in other ways. After the removal, a gate oxide layer 150 is formed on the surface of the substrate 10, the material of the gate oxide layer 150 is, for example, silicon oxide, and the thickness of the gate oxide layer 150 is, for example, 1 to 15nm. The gate oxide layer 150 is formed by, for example, a thermal oxidation method, chemical vapor deposition, physical vapor deposition (Physical Vapor Deposition, PVD), or the like. In this embodiment, the gate oxide layer 150 is formed, for example, by an In-situ vapor generation (In-situ Stream Generation, ISSG) method, and during the reaction, oxygen containing a small amount of vapor is introduced, and at 900-1100 ℃, a large amount of oxygen radicals are produced, which react with bare silicon to produce silicon dioxide, but not with silicon oxide, so that the gate oxide layer 150 is formed on the surface of the substrate 10 and on the exposed substrate 10 In the first and second grooves 151 and 152. The gate oxide layer 150 formed by the in-situ vapor generation method has few in-vivo defects and relatively small interface state density, and is beneficial to improving the performance of the device.
Referring to fig. 20 to 22, in an embodiment of the present invention, fig. 20 is a cross-sectional view of fig. 3 in A-A direction, fig. 21 is a cross-sectional view of fig. 3 in B-B direction, and fig. 22 is a cross-sectional view of fig. 3 in D-D direction. After forming the gate oxide layer 150, a gate material layer 161 is formed in the recess until the gate material layer 161 covers the substrate 10. In this embodiment, the gate material layer 161 is, for example, a polysilicon layer, and the polysilicon layer may be doped polysilicon or undoped polysilicon, and the doping type may be P-type or N-type. The thickness of the gate material layer 161 on the substrate 10 is, for example, 100-400 nm, and in other embodiments, the thickness of the gate material layer 161 may be set according to actual needs. A third photoresist layer 170 is formed on the gate material layer 161, and the third photoresist layer 170 covers the gate material layer 161 where the transfer gate is required to be formed.
Referring to fig. 23 to 25, in an embodiment of the present invention, fig. 23 is a cross-sectional view of fig. 3 in A-A direction, fig. 24 is a cross-sectional view of fig. 3 in B-B direction, and fig. 25 is a cross-sectional view of fig. 3 in D-D direction. The third photoresist layer 170 is used as a mask, and then the gate material layer 161 and the gate oxide layer 150 are etched by, for example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process to form the transfer gate 15. In this embodiment, for example, the gate material layer 161 and the gate oxide layer 150 are anisotropically etched by a dry etching process, and the gate oxide layer 150 is etched by changing an etching gas after the etching of the gate material layer 161 is completed. After the etching is completed, the third photoresist layer 170 is removed, and the third photoresist layer 170 is removed, for example, by oxygen plasma removal or wet removal.
Referring to fig. 17, 18, and 23-25, in an embodiment of the present invention, a portion of the transfer gate 15 is located in the first recess 151 and the second recess 152 and extends toward the isolation structures 11 and the substrate 10 on both sides of the recess. Wherein the transfer gate 15 comprises a planar gate 154, the planar gate 154 covering a portion of the substrate 10 and a portion of the isolation structure 11, i.e. the transfer gate 15 covers a portion of the photodiode and the isolation structure 11 around the photodiode. The transfer gate 15 further comprises a vertical gate 153, i.e. the gate material layer within the first recess 151 and the second recess 152 is defined as a vertical gate 153, wherein the depth of the vertical gate 153 is less than or equal to the depth of the photodiode. By providing the vertical gate 153, electrons within the photodiode can be transferred nearby into the vertical gate 153, collected by the vertical gate 153, transported rapidly within the planar gate 154, and transported to the floating diffusion region. Electrons are completely transferred, image afterimage phenomenon is reduced, and the full well capacity of the COMS image sensor is improved.
Referring to fig. 25, in one embodiment of the present invention, after forming the transfer gate 15, in the D-D direction of fig. 3, first type impurity ions are implanted with low implantation energy into a side substrate of the transfer gate 15 opposite to the first well region 101 and the second well region 102 to form the floating diffusion region 14. I.e., the ion implantation type of the floating diffusion region 14 is the same as that of the first well region 101, and the ion implantation depth of the floating diffusion region 14 is on the order of the ion implantation depth of the second well region 102. In the present embodiment, the size of the floating diffusion region 14 is, for example, one fortieth to one fifth of the size of the first well region 101. The sensitivity of the image sensor can be improved by reducing the ratio of the size of the floating diffusion region 14 to the size of the first well region 101.
Referring to fig. 26 to 28, in an embodiment of the present invention, fig. 26 is a cross-sectional view of fig. 3 in A-A direction, fig. 27 is a cross-sectional view of fig. 3 in B-B direction, and fig. 28 is a cross-sectional view of fig. 3 in D-D direction. After the transfer gate 15 is formed, sidewall structures 180 are formed on both sides of the transfer gate 15, specifically, sidewall dielectric layers (not shown) are formed on the transfer gate 15, the isolation structure 11 and the substrate 10, and the sidewall dielectric layers are made of, for example, silicon oxide, silicon nitride or a stack of silicon oxide and silicon nitride. After forming the sidewall dielectric layer, for example, an etching process such as dry etching may be used to remove the sidewall dielectric layer on the transfer gate 15, part of the isolation structure 11 and part of the substrate 10, and the sidewall dielectric layers on both sides of the transfer gate 15 are retained, so as to form the sidewall structure 180. And the height of the side wall structure 180 is consistent with the height of the transfer grid 15, the width of the side wall structure 180 is gradually increased from the top to the bottom of the transfer grid 15, and the electric leakage phenomenon is prevented by arranging the insulating side wall structure 180. In this embodiment, the shape of the side wall structure 180 is, for example, arc, and in other embodiments, the shape of the side wall structure 180 may be other shapes, which may be selected according to the manufacturing requirements. In operation of the image sensor, each photodiode is connected to the floating diffusion region 14 through the transfer gate 15, and the photodiodes convert optical signals into electrical signals, and signal electrons are transferred to the floating diffusion region 14 through the transfer gate 15, thereby achieving conversion of optical signals into electrical signals. In the present invention, the fabrication method and structure of the transfer gate 15 can be applied to CMOS image sensors with 5T structure, 6T structure, 7T structure, 8T and more pixel structure variations, for improving the performance of the CMOS image sensor. After forming the sidewall structures, the fabrication of the dielectric layer, the metal interconnection structure, the color filter, etc. may be continued on the substrate 10 and the gate structure, and the fabrication method may be a general fabrication method of the dielectric layer, the metal interconnection structure, and the microlens, which will be described herein, and the backside illumination (Back side illumination, BSI) or front side illumination (Front side illumination, FSI) process may be selected in the fabrication process of the image sensor.
In summary, the present invention provides an image sensor and a method for manufacturing the same, in which, in the manufacturing process, after forming an isolation trench, a groove is formed to locate a vertical gate, and in the etching process, a second sacrificial layer is used as a mask to transfer a horizontal channel of the gate, so that self-aligned etching is realized in the etching process, the hard mask blocks the channel from being damaged by etching, and dark current is reduced. Meanwhile, the depth of the vertical grid electrode is smaller than or equal to that of the photodiode, the transfer grid electrode wraps or partially wraps the photodiode, electrons are completely transferred, image afterimage phenomenon is reduced, and the full-well capacity of the image sensor is improved. And the application range of the transfer grid is wide, and the performance of the image sensor can be improved.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (12)
1. An image sensor, comprising at least:
a substrate;
a photodiode disposed within the substrate;
a floating diffusion region disposed within the substrate, the floating diffusion region being disposed in parallel with the photodiode within the substrate; and
a transfer gate disposed between the photodiode and the floating diffusion region, and the transfer gate wraps around the photodiode or a portion of the photodiode, the transfer gate extending from the substrate surface into the substrate.
2. The image sensor of claim 1, wherein the transfer gate has a length of 1/2 to 1 of the photodiode perimeter.
3. The image sensor of claim 1, wherein the transfer gate wraps around at least two adjacent sides of the photodiode.
4. The image sensor of claim 1, wherein the transfer gate comprises a vertical gate disposed within an isolation structure outside the photodiode and in contact with the photodiode through a gate oxide.
5. The image sensor of claim 4, wherein a depth of the vertical gate is less than or equal to the photodiode depth.
6. The image sensor of claim 1, wherein the transfer gate comprises a planar gate that covers a portion of the isolation structure outside the photodiode and extends onto the photodiode, covering a portion of the photodiode.
7. A method for manufacturing an image sensor, comprising at least the steps of:
providing a substrate;
forming a photodiode within the substrate;
forming a floating diffusion region in the substrate, wherein the floating diffusion region and the photodiode are arranged in parallel in the substrate; and
a transfer gate is formed between the photodiode and the floating diffusion region, and wraps around the photodiode or around a portion of the photodiode, the transfer gate including a vertical gate extending from the substrate surface into the substrate.
8. The method of manufacturing an image sensor of claim 7, further comprising:
forming a first sacrificial layer on the substrate;
forming a second sacrificial layer on the first sacrificial layer;
etching the second sacrificial layer, the first sacrificial layer and part of the substrate to form a groove; and
and depositing an isolation medium in the groove to form an isolation structure, wherein the isolation structure is flush with the second sacrificial layers on two sides.
9. The method of manufacturing an image sensor according to claim 8, wherein a horizontal channel of the transfer gate is formed between the photodiode and the floating diffusion region, and the isolation structures are disposed on both sides of the horizontal channel.
10. The method of manufacturing an image sensor of claim 9, further comprising:
forming a photoresist layer on the second sacrificial layer and the isolation structure, wherein the photoresist layer exposes the horizontal channel of the transfer gate, part of the isolation structure on two sides of the horizontal channel, the photodiode covered by the transfer gate and the isolation structure covered by the transfer gate; and
and taking the photoresist layer and part of the second sacrificial layer on the substrate as masks, and etching the isolation structure in a self-aligned manner to form a groove.
11. The method of manufacturing an image sensor of claim 10, further comprising:
after forming the groove, removing the second sacrificial layer; and
and forming a first well region and a second well region in the substrate by taking the first sacrificial layer as an ion implantation buffer layer, wherein the second well region is arranged on the first well region so as to form a photodiode.
12. The method of manufacturing an image sensor of claim 11, further comprising:
removing the first sacrificial layer;
forming a gate oxide layer on the substrate and the exposed surface of the substrate of the groove;
forming a gate material layer in the recess and on the substrate; and
and removing part of the gate material layer on the substrate to form the transfer gate.
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