CN117936556A

CN117936556A - Image sensor and manufacturing method thereof

Info

Publication number: CN117936556A
Application number: CN202211262453.2A
Authority: CN
Inventors: 赵庆贺; 范春晖; 李岩; 张莉玮
Original assignee: Hefei Haitu Microelectronics Co ltd
Current assignee: Hefei Haitu Microelectronics Co ltd
Priority date: 2022-10-14
Filing date: 2022-10-14
Publication date: 2024-04-26

Abstract

The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor includes: a substrate; a photodiode disposed within the substrate; a floating diffusion region disposed within the substrate; a transfer transistor disposed on the substrate between the photodiode and the floating diffusion region to connect or disconnect the photodiode and the floating diffusion region; and a row selection tube arranged on the substrate at one side far away from the transmission transistor, wherein the grid electrode of the row selection tube is of a ring-shaped grid electrode structure. By the image sensor and the manufacturing method thereof, the high-quality image sensor is obtained.

Description

Image sensor and manufacturing method thereof

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to an image sensor and a manufacturing method thereof.

Background

In the preparation process of the complementary metal oxide image sensor (Complementary Metal Oxide Semiconductor Image Sensor, CMOS image sensor), the existing semiconductor equipment can be used for manufacturing, the external investment is reduced, the integration level of the CMOS image sensor is higher, the cost is low, the performance requirements of high pixels, wide dynamic range, high sensitivity and the like can be realized, and the complementary metal oxide image sensor can be widely applied to various fields of consumer electronics, automatic driving, biological identification, security protection and the like.

As the size of functional transistors in CMOS image sensors decreases, electrons are easier from one functional transistor to another, and dark current is generated as technology nodes develop more severely, affecting image quality. One of the main sources of dark current is leakage between transistors in an image sensor, including leakage between Photodiodes (PDs) and between PDs and other transistors, where the leakage between PDs can be avoided by Isolation layer injection (Isolation) or transmission transistor threshold voltage adjustment (TX Vt), etc., and the leakage between PDs and other transistors is difficult to avoid, thus causing serious image quality problems.

Disclosure of Invention

The invention aims to provide an image sensor and a manufacturing method thereof, and the image sensor and the manufacturing method thereof can reduce parameters of dark current and obtain an image sensor with high image quality.

In order to solve the technical problems, the invention is realized by the following technical scheme:

The invention provides an image sensor, comprising at least:

A substrate;

A photodiode disposed within the substrate;

a floating diffusion region disposed within the substrate;

A transfer transistor disposed on the substrate between the photodiode and the floating diffusion region to connect or disconnect the photodiode and the floating diffusion region; and

And the row selection tube is arranged on the substrate at one side far away from the transmission transistor, and the grid electrode of the row selection tube is of a ring-shaped grid electrode structure.

In an embodiment of the present invention, the annular gate structure is one of a circular ring, an elliptical ring, a square ring, a rectangular ring, a polygonal ring, or a combination of a polygonal ring and a circular ring.

In one embodiment of the present invention, an isolation structure is provided between the row select tube and the photodiode for isolation.

In one embodiment of the invention, a portion of the ring-shaped gate structure is located on the isolation structure between the row select tube and the photodiode.

In one embodiment of the present invention, a portion of the annular gate structure spans the isolation structure between the row select tubes and the photodiodes and over a portion of the active area where the row select tubes are located.

In an embodiment of the present invention, the image sensor further includes a reset tube and a source follower tube, the reset tube and the source follower tube being disposed between the transfer transistor and the row selection tube, the source follower tube being disposed near the row selection tube.

In an embodiment of the present invention, the image sensor further includes a first isolation structure and a second isolation structure, the first isolation structure is located between the reset tube and the photodiode and between the source follower tube and the photodiode, and the second isolation structure is located between the row select tube and the photodiode.

In an embodiment of the present invention, the size of the second isolation structure is 1.2 to 1.5 times that of the first isolation structure.

In an embodiment of the invention, the image sensor further includes a discharge tube, a gate of the discharge tube is in a ring-shaped gate structure, and the discharge tube and the row selection tube are located at two adjacent sides of the photodiode.

The invention also provides a manufacturing method of the image sensor, which at least comprises the following steps:

providing a substrate;

forming a photodiode within the substrate;

Forming a transfer transistor on the substrate;

Forming a floating diffusion region in the substrate, and the transfer transistor being disposed between a photodiode and the floating diffusion region to connect or disconnect the photodiode and the floating diffusion region; and

And forming a row selection tube on the substrate at one side far away from the transmission transistor, wherein the grid electrode of the row selection tube is of a ring-shaped grid electrode structure.

In summary, the present invention provides an image sensor and a method for manufacturing the same, which can form a depletion region at the bottom of an isolation structure between a photodiode and a row selection tube, thereby blocking electrons from flowing to the photodiode, reducing dark current, and obtaining a CMOS image sensor with high image quality. Meanwhile, the transmission of the source electrode or the drain electrode of the row selection tube is facilitated, the distance between electrons and the photodiode can be increased, and the generation of dark current is further reduced.

Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an image sensor according to an embodiment.

Fig. 2 is a circuit configuration diagram of an image sensor in an embodiment.

Fig. 3 is a cross-sectional view of the first photoresist layer formed in the A-A direction of fig. 1.

Fig. 4 is a cross-sectional view of the isolation structure formed in the A-A direction of fig. 1.

Fig. 5 is a cross-sectional view of the well region formed in the A-A direction of fig. 1.

Figure 6 is a cross-sectional view of the gate and sidewall structure formed in the direction A-A of figure 1.

Fig. 7 is a cross-sectional view of the depletion region structure in the A-A direction of fig. 1.

Fig. 8 is a schematic diagram of an image sensor according to another embodiment.

Fig. 9 is a cross-sectional view of the gate and sidewall structure formed in the direction B-B of fig. 8.

Fig. 10 is a cross-sectional view of the depletion region structure in the B-B direction of fig. 8.

Fig. 11 is a schematic diagram of an image sensor according to another embodiment.

Fig. 12 is a cross-sectional view of the first photoresist layer formed in the C-C direction of fig. 11.

Fig. 13 is a cross-sectional view of the first photoresist layer formed in the direction C1-C1 of fig. 11.

Fig. 14 is a cross-sectional view of the isolation structure formed in the direction C-C of fig. 11.

Fig. 15 is a cross-sectional view of the isolation structure formed in the direction C1-C1 of fig. 11.

Fig. 16 is a cross-sectional view of the gate and sidewall structure formed in the direction C-C of fig. 11.

Fig. 17 is a schematic diagram of an image sensor according to another embodiment.

Fig. 18 is a circuit configuration diagram of an image sensor in another embodiment.

Description of the reference numerals:

100. A substrate; 101. a first well region; 102. a second well region; 11. an isolation structure; 111. a first isolation structure; 112. a second isolation structure; 12. an active region; 110. a pad oxide layer; 120. pad nitriding layer; 130. a first photoresist layer; 131. a first opening; 132. a second opening; 140. a gate oxide layer; 150. a gate material layer; 160. a side wall structure; 170. a heavily doped region; 180. an electron depletion region.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

In the present application, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.

Referring to fig. 1 to 2, in an embodiment of the present invention, an image sensor, such as a CMOS image sensor of a 4T structure, is provided, and the image sensor includes a photodiode PD (Photo Diode), a floating diffusion FD, a transfer transistor TX, a reset transistor RX, a source follower SF, and a row select line SEL, wherein the floating diffusion FD, the reset transistor RX, the source follower SF, and the row select line SEL are disposed on a substrate 100. The substrate 100 includes an isolation structure 11 and an active region 12, and a photodiode PD, a floating diffusion FD, a transfer transistor TX, a reset transistor RX, a source follower SF, and a row select transistor SEL are disposed on the active region 12. In this embodiment, the active region 12 is disposed in a "U" shape, for example, with the photodiode PD disposed at one side of the "U", the transfer transistor TX and the floating diffusion FD are disposed at the bottom of the "U", the transfer transistor TX is disposed between the photodiode PD and the floating diffusion FD, the reset tube RX, the source follower SF, and the row select tube SEL are disposed side by side at the other side of the "U", the reset tube RX is disposed near the floating diffusion FD, the source follower SF is disposed near the reset tube RX, and the row select tube SEL is disposed near the source follower SF. The width of the active region 12 where the reset tube RX, the source follower tube SF and the row select tube SEL are located is smaller than the width of the active region 12 where the photodiode PD is located, and the reset tube RX, the source follower tube SF, the row select tube SEL and the photodiode PD are isolated by the isolation structure 11.

Referring to fig. 1 to 2, in an embodiment of the present invention, a photodiode PD may convert an optical signal into an electrical signal. When the transfer transistor TX is turned on in response to the transfer signal, electrons after photoelectric conversion in the photodiode PD are transferred out and temporarily stored in the node capacitance of the floating diffusion FD. The output end of the reset tube RX is electrically connected to one end of the transmission transistor TX, the other end of the reset tube RX is electrically connected to the power voltage VDD_PIXEL, and the grid electrode of the reset tube RX is electrically connected to the reset signal. When the reset tube RX is turned on in response to the reset signal, a signal of a connection point of an output terminal of the reset tube RX and a gate terminal of the source follower tube SF is reset to a power supply voltage vdd_pixel at the other end of the reset tube RX. Then the reset signal is turned off, and the connection point of the reset tube RX and the gate end of the source follower SF is kept lower than the voltage value of the other end of the reset tube RX due to the channel charge injection effect and clock feed-through, and no ground path exists at the connection point of the reset tube RX and the gate end of the source follower SF. The row select tube SEL is connected in series with the source follower tube SF, and one end of the source follower tube SF is electrically connected to the power voltage vdd_pixel, and one end of the row select tube SEL is a signal output end. The output end of the row selection tube SEL is connected with a tail current source, the potential of the tail current source is the lowest compared with other areas, the tail current source is close to the photodiode PD, electrons follow to transfer from a low potential to a high potential area, electrons are easy to transmit to the photodiode PD, dark current is generated, and therefore impurity signals are caused, and photographing quality is affected. According to the invention, the grid electrode of the row selection tube SEL is set to be a ring-shaped grid electrode, and the electron depletion region is formed at the bottom of the isolation structure, so that the generation of dark current can be reduced, and a high-quality CMOS image sensor can be obtained.

Referring to fig. 1 and 3, in an embodiment of the present invention, an image sensor includes photodiodes and other semiconductor devices arranged in an array. In this embodiment, a process of manufacturing the image sensor will be described by taking one photodiode and a transistor on one side of the photodiode in the image sensor as an example, and a cross-sectional view in the A-A direction of fig. 1 will be described by way of example. Wherein fig. 3 is a cross-sectional view of fig. 1 in the direction A-A. The substrate 100 is provided first, wherein the substrate 100 may be any suitable semiconductor material, for example, a substrate such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire or silicon wafer, and a stacked structure formed by these semiconductors, or may be silicon on insulator, silicon germanium on insulator, or the like, which may be specifically selected according to the manufacturing requirements of the image sensor. In the present embodiment, the substrate 100 is, for example, a silicon wafer semiconductor substrate.

Referring to fig. 3, in an embodiment of the present invention, a pad oxide layer 110 is formed on a substrate 100, and the pad oxide layer 110 is disposed on the substrate 100. Specifically, the pad oxide layer 110 is an insulating material such as dense silicon oxide, and the pad oxide layer 110 may be formed on the substrate 100 by any one of a dry oxygen oxidation method, a wet oxygen oxidation method, and an in-situ vapor growth method, for example. In one embodiment, for example, the substrate 100 is placed in a furnace tube at a temperature of, for example, 900 ℃ to 1150 ℃, oxygen is introduced, the substrate 100 reacts with oxygen at a high temperature to generate a dense pad oxide layer 110, and the quality of the produced pad oxide layer 110 is better. The thickness of the pad oxide layer 110 is, for example, 8nm to 15nm, specifically, 8nm, 10nm, 12nm, or the like.

Referring to fig. 3, in an embodiment of the present invention, after forming the pad oxide layer 110, a pad nitride layer 120 is formed on the pad oxide layer 110, where the pad nitride layer 120 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide, and in this embodiment, the pad nitride layer 120 is, for example, silicon nitride. Wherein the pad oxide layer 110 serves as a buffer layer to improve the stress between the substrate 100 and the pad nitride layer 120. In the present invention, the pad nitride layer 120 may be formed on the pad oxide layer 110 by, for example, low pressure chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition (PECVD)). In some embodiments, pad nitride layer 120 has a thickness of, for example, 10nm to 300nm, and for example, 110 nm. The pad nitride layer 120 may protect the substrate 100 from damage during etching.

Referring to fig. 3, in an embodiment of the present invention, a first photoresist layer 130 is formed on the pad nitride layer 120. A first opening 131 is provided on the first photoresist layer 130 through a process such as exposure and development. The first opening 131 exposes a portion of the pad nitride layer 120 in the A-A direction, and is used for positioning the isolation structures at different positions. Taking the first photoresist layer 130 as a mask, quantitatively removing the pad nitride layer 120, the pad oxide layer 110 and part of the substrate 100 under the first photoresist layer 130 by using dry etching, wet etching or etching methods of combining dry etching and wet etching, and the like, so as to obtain a trench. In this embodiment, for example, a shallow trench is formed by dry etching, and the etching gas is, for example, one or a combination of several of chlorine (Cl ₂), trifluoromethane (CHF ₃), difluoromethane (CH ₂F₂), nitrogen trifluoride (NF ₃), sulfur hexafluoride (SF ₆), hydrogen bromide (HBr), and oxygen (O ₂). After the etching is completed, the first photoresist layer 130 is removed, and the first photoresist layer 130 is removed, for example, by oxygen plasma removal or wet removal.

Referring to fig. 1, 3-4, in an embodiment of the present invention, fig. 4 is a cross-sectional view of fig. 1 in A-A direction. After forming the trench, an isolation medium, such as an insulating material, such as silicon oxide, is deposited in the trench, such as by high density plasma chemical vapor deposition (HIGH DENSITY PLASMA CVD, HDP-CVD) or high aspect Ratio chemical vapor deposition (HIGH ASPECT Ratio Process CVD, HARP-CVD). After the isolation medium deposition is completed, a planarization process such as chemical mechanical Polishing (CHEMICAL MECHANICAL CMP) is performed to locate the isolation medium and the top of the pad nitride layer 120 on the same plane, and the pad nitride layer 120 and a portion of the isolation medium are removed early by etching, so as to form a plurality of isolation structures 11. In the present embodiment, the depth of the isolation structure 11 in the substrate 100 is, for example, 200nm to 1100nm. The isolation structure 11 divides the substrate 100 into an isolation region and an active region 12, the active region 12 is arranged in a "U" shape, for example, and the isolation structure 11 in the middle of the "U" will isolate the reset transistor RX, the source follower transistor SF, and the row select transistor SEL from the photodiode PD. That is, by providing the plurality of isolation structures 11, the plurality of photodiodes in the image sensor or the plurality of photodiodes and other semiconductor devices are isolated, so that the mutual interference between the semiconductor devices is reduced, and the performance of the image sensor is improved.

Referring to fig. 4 to 5, in an embodiment of the present invention, fig. 5 is a cross-sectional view of fig. 1 in A-A direction. After the isolation structure 11 is formed, the first well region 101 is formed by implanting first type impurity ions with high implantation energy using the pad oxide layer 110 as an ion implantation buffer layer. Impurity ions of a second type are implanted on the first well region 101 at a low implantation energy to form a second well region 102, and the second well region 102 is formed on the first well region 101 due to the difference in implantation energy, i.e., the depth of the first well region 101 is greater than the depth of the second well region 102. The widths of the first well region 101 and the second well region 102 are equal, and the second well region 102 is, for example, one eighth to one third of the depth of the first well region 101.

Referring to fig. 5, in an embodiment of the present invention, the first type impurity ions are different from the second type impurity ions, wherein the first type impurity ions are N-type impurities such As phosphorus (P) or arsenic (As), and the second type impurity ions are P-type impurities such As boron (B), that is, the doping types of the first well region 101 and the second well region 102 are different. In other embodiments, the first type impurity ions may be P-type impurities, and the second type impurity ions may be N-type impurities, which may be selected according to the manufacturing requirements of the image sensor. In this embodiment, the doping concentration of the formed second well region 102 is ensured to be greater than that of the first well region 101, a built-in electric field directed to the second well region 102 by the first well region 101 is formed, the depletion region of the first well region 101 is prevented from widening towards the surface of the isolation structure 11 by arranging the second well region 102 with high doping concentration, the number of dangling bonds formed on the surface of the isolation structure 11 is reduced, dark current of the image sensor is reduced, and generated electrons are conveyed to the floating diffusion region through the transfer gate by the first well region 101. In the present invention, impurity ions different from the first well region 101 may be injected around the isolation structure 11 to form an isolation well region, so as to improve the isolation effect of the isolation structure 11, and in this embodiment, the isolation well region is not shown for clarity of the picture.

Referring to fig. 5 to 6, in an embodiment of the present invention, fig. 6 is a cross-sectional view of fig. 1 in A-A direction. After the well region is formed, the pad oxide layer 110 on the surface of the substrate 100 is removed, for example, by a wet process, and the gate oxide layer 140 is reformed. The material of the gate oxide layer 140 is, for example, silicon oxide, and the thickness of the gate oxide layer 140 is, for example, 5-15 nm. The gate oxide layer 140 is formed by, for example, thermal oxidation, chemical vapor deposition, or physical vapor deposition (Physical Vapor Deposition, PVD), or the like. In this embodiment, the gate oxide layer 140 is formed, for example, by an In-situ vapor generation (In-situ Stream Generation, ISSG) method, and the gate oxide layer 140 is formed on the surface of the substrate 100. The gate oxide layer 140 formed by the in-situ vapor generation method has few in-vivo defects and relatively small interface state density, and is beneficial to improving the performance of the image sensor.

Referring to fig. 6 and 7, in an embodiment of the present invention, after forming the gate oxide layer 140, a gate material layer 150 is formed on the gate oxide layer 140 and the isolation structure 11. In this embodiment, the gate material layer 150 is, for example, a polysilicon layer, and the polysilicon layer may be doped polysilicon or undoped polysilicon, and the doping type may be P-type or N-type. The thickness of the gate material layer 150 on the substrate 100 is, for example, 100-400 nm, and in other embodiments, the thickness of the gate material layer 150 may be set according to actual needs. A patterned photoresist layer is formed on the gate material layer 150, the patterned photoresist layer is used as a mask, and then the gate material layer 150 and the gate oxide layer 140 are etched by, for example, a dry etching process, a wet etching process, or a combination of the dry etching process and the wet etching process, and the remaining gate material layer 150 and gate oxide layer 140 are defined as a gate electrode. In this embodiment, the annular gate structure 17 of the row selection tube is shown, and the shape of the annular gate structure 17 is, for example, one of a circular ring, an elliptical ring, a square ring, a rectangular ring, a polygonal ring, or a combination of a polygonal ring and a circular ring, for example, an annular runway formed by two straight and two semicircular arcs, wherein a part of the annular gate structure 17 is located on the active region of the row selection tube, a part of the annular gate structure 17 is located on the isolation structure 11 around the row selection tube, and wraps around the active region of the row selection tube to form an electron depletion region 180 at the bottom of the isolation structure 11 around the row selection tube, so as to prevent electrons from being transmitted from the row selection tube to the adjacent photodiodes. In the present invention, the annular gate structure 17 may be a closed annular shape or an open annular shape, so that a part of the annular gate structure 17 is located on the active region where the row selection tube is located, and a part of the annular gate structure is located on the isolation structure 11 around the row selection tube.

Referring to fig. 6, in an embodiment of the present invention, after forming the gate, sidewall structures 160 are formed on both sides of the gate, specifically, sidewall dielectric layers (not shown) are formed on the gate, the isolation structures 11 and the substrate 100, and the sidewall dielectric layers are made of, for example, silicon oxide, silicon nitride or a stack of silicon oxide and silicon nitride. After forming the sidewall dielectric layer, for example, an etching process such as dry etching may be used to remove the gate, part of the isolation structure 11 and part of the sidewall dielectric layer on the substrate 100, and the sidewall dielectric layers on two sides of the gate are retained to form the sidewall structure 160. And the height of the side wall structure 160 is consistent with that of the grid, the width of the side wall structure 160 is gradually increased from the top to the bottom of the grid, and the electric leakage phenomenon is prevented by arranging the insulating side wall structure 160. In this embodiment, the shape of the sidewall structure 160 is, for example, arc, and in other embodiments, the shape of the sidewall structure 160 may be other shapes, which may be selected according to the manufacturing requirements.

Referring to fig. 1, 6-7, fig. 7 is a cross-sectional view of fig. 1 along A-A in an embodiment of the present invention. Ion implantation is performed in the active region 12 in the annular gate structure 17 to form a heavily doped region 170 as a source/drain doped region. In other transistor regions, doping is performed as well to form source/drain doped regions, and at the same time, a region floating diffusion region PD is also formed in the active region between the output transistor TX and the reset transistor RX. When the image sensor works, the output end of the row selection tube SEL is connected with a tail current source, the potential is the lowest, but the annular grid electrode structure 17 positioned on the isolation structure 11 forms a field effect transistor effect, and the electron depletion region 180 is formed at the bottom of the isolation structure 11, so that electrons can be restrained from flowing to a photodiode PD region, dark current is restrained from being generated, and the performance of the image sensor is improved. And the voltage connected to the annular gate structure 17 on the row selection tube SEL is regulated and controlled to control the depth and the size of the electron depletion region 180, so as to control dark current and meet the use requirements of image sensors with different structures and different sizes.

Referring to fig. 8 to 10, in an embodiment of the present invention, fig. 8 is a schematic structural diagram of another image sensor according to the present invention, and fig. 9 and 10 are cross-sectional views of fig. 8 in the direction B-B. The gate of the row select transistor SEL is a ring gate structure 17, and two sides of the ring gate structure 17 span the isolation structures 11 and part of the active region 12 on two sides of the select transistor SEL. Specifically, during the formation of the annular gate structure 17, the position of the annular gate structure 17 is adjusted, and the annular gate structure 17 spans over a portion of the isolation structure 11 and a portion of the active region 12. The formation of the sidewall structures 160 and the heavily doped regions 170 is the same as in the previous embodiment and will not be described here. When the image sensor works, the output end of the row selection tube SEL is connected with a tail current source, the potential is the lowest, but the effect of the field effect transistor formed by the annular grid electrode structure 17 on the isolation structure 11 is enhanced, the area forming the electron depletion region 180 at the bottom of the isolation structure 11 is increased, dark current blocking is more effective, transmission between the source electrode and the drain electrode of the row selection tube SEL is facilitated, and therefore the performance of the image sensor is further improved.

Referring to fig. 11, in an embodiment of the present invention, a schematic structural diagram of another image sensor is provided, wherein the gate of the row selection tube SEL is configured as a ring-shaped gate structure 17, and the width of the active region where the row selection tube SEL is located is reduced, and the distance between the row selection tube SEL and the photodiode is increased while the ring-shaped gate structure 17 is formed. The process of fabricating the image sensor will be described with reference to fig. 11, which is a sectional view taken along the C-C direction.

Referring to fig. 11 to 13, in an embodiment of the present invention, fig. 12 is a cross-sectional view of fig. 11 in the direction C-C, and fig. 13 is a cross-sectional view of fig. 11 in the direction C1-C1. A first photoresist layer 130 is formed on the pad nitride layer 120. A first opening 131 and a second opening 132 are provided on the first photoresist layer 130 through a process of exposure development or the like. The first opening 131 exposes the pad nitride layer 120 between the photodiode PD and the reset tube RX and the source follower tube SF, the second opening 132 exposes the pad nitride layer 120 between the photodiode PD and the row select tube SEL, and the size of the second opening 132 is, for example, 1.2 to 1.5 times the size of the first opening 131. That is, by increasing the size of the isolation structure between the row select transistor SEL and the photodiode PD, the size of the active region of the select transistor SEL is reduced, the distance between the row select transistor SEL and the photodiode PD is increased, and at the same time, the distance between the photodiode PD and the reset transistor RX and the source follower transistor SF is not increased, so that the size of the image sensor is not increased. Taking the first photoresist layer 130 as a mask, quantitatively removing the pad nitride layer 120, the pad oxide layer 110 and part of the substrate 100 under the first photoresist layer 130 by using dry etching, wet etching or etching methods of combining dry etching and wet etching, and the like, so as to obtain a trench. In this embodiment, for example, a shallow trench is formed by dry etching, and the etching gas is, for example, one or a combination of several of chlorine, trifluoromethane, difluoromethane, nitrogen trifluoride, sulfur hexafluoride, hydrogen bromide, oxygen, or the like. After the etching is completed, the first photoresist layer 130 is removed, and the first photoresist layer 130 is removed, for example, by oxygen plasma removal or wet removal.

Referring to fig. 11, 14 and 15, in an embodiment of the present invention, fig. 14 is a cross-sectional view of fig. 11 in the direction C-C, and fig. 15 is a cross-sectional view of fig. 11 in the direction C1-C1. After forming the trench, an isolation medium, such as an insulating material, such as silicon oxide, is deposited in the trench, such as by high density plasma chemical vapor deposition (HIGH DENSITY PLASMA CVD, HDP-CVD) or high aspect Ratio chemical vapor deposition (HIGH ASPECT Ratio Process CVD, HARP-CVD). After the isolation medium deposition is completed, for example, a planarization process such as Chemical Mechanical Polishing (CMP) is performed to locate the isolation medium and the top of the pad nitride layer 120 on the same plane, and then the pad nitride layer 120 and a portion of the isolation medium are removed by etching to form a plurality of isolation structures, where the isolation structures include a first isolation structure 111 and a second isolation structure 112, the first isolation structure 111 is located between the photodiode PD and the reset tube RX and the source follower tube SF, and the second isolation structure 112 is located between the photodiode PD and the row select tube SEL. That is, by providing the first and second isolation structures 111 and 112, the distance between the adjacent photodiodes PD and the row select tube SEL is increased, that is, the path of electrons from the row select tube SEL to the photodiodes PD is increased, so that more electrons are depleted, thereby achieving the purpose of reducing dark current.

Referring to fig. 11, 15-16, fig. 16 is a cross-sectional view of fig. 11 along the direction C-C in an embodiment of the invention. After the isolation structure is formed, the forming process of the well region, the gate electrode, the side wall structure and the heavily doped region is identical to the forming process described above, which is not described herein. In the present embodiment, on the one hand, the distance between the photodiode PD and the row selection tube SEL is large, and on the other hand, the gate of the row selection tube SEL is a ring-shaped gate structure 17, so that dark current generation is suppressed from both sides, and the present embodiment can be applied to an image sensor with high integration level, and image quality of the image sensor is improved. In the present invention, the ring gate structure 17 of the row select tube SEL can also be applied to CMOS image sensors of 5T structure, 6T structure, 7T structure, 8T and more pixel structure variations for improving the performance of the CMOS image sensor. After the heavily doped region is formed, the fabrication of the dielectric layer, the metal interconnect structure, the color filter, etc. may be continued on the substrate 100 and the gate electrode, and the fabrication method may be a general fabrication method of the dielectric layer, the metal interconnect structure, and the microlens, which will not be described herein, and the backside illuminated (Back side illumination, BSI) or front side illuminated (Front side illumination, FSI) process may be selected in the fabrication process of the image sensor.

Referring to fig. 17 to 18, in another embodiment of the present invention, a CMOS image sensor of an 8T structure of a global shutter (global shutter) is provided, and the image sensor includes a photodiode PD, a floating diffusion FD, a transfer transistor TX, a reset transistor RX, a first source follower SF1, a discharge transistor PC, a first sampling tube S1, a second sampling tube S2, a second source follower SF2, and a row selection transistor SEL. The layout of the photodiode PD, the floating diffusion FD, the transfer transistor TX, the reset tube RX, the first source follower SF1 and the discharge tube PC is the same as that of the CMOS image sensor of the 4T structure, and the first sampling tube S1, the second sampling tube S2, the second source follower SF2, and the row selection tube SEL are disposed on the other side from the photodiode PD and on the side of the discharge tube PC away from the floating diffusion FD. In the present embodiment, the discharge tube PC and the row selection tube SEL are isolated from the photodiode PD by the isolation structure 11, and the gates of the discharge tube PC and the row selection tube SEL are provided in a ring-shaped gate structure, and a part of the ring-shaped gate structure is provided on the isolation structure 11 between the discharge tube PC and the row selection tube SEL and the photodiode PD.

Referring to fig. 15 to 16, in an embodiment of the invention, a discharge tube PC is connected in series with a first source follower SF1, one end of the first source follower SF1 is electrically connected to a power voltage vdd_pixel, and one end of the discharge tube PC is electrically connected to a ground terminal and is in a low potential region. The circuit further includes a signal voltage sampling capacitor C1 and a reset voltage sampling capacitor C2. One end of the signal voltage sampling capacitor C1 is electrically connected to the common end of the first source follower tube SF1 and the discharge tube PC through the first sampling tube S1, and one end of the reset voltage sampling capacitor C2 is electrically connected to the common end of the signal voltage sampling capacitor C1 and the first sampling tube S1 through the second sampling tube S2. The second source follower SF2 is connected in series with the row select tube SEL, and the gate of the second source follower M7 is electrically connected to the common terminal of the second sampling tube S2 and the reset voltage sampling capacitor C2, one end of the second source follower SF2 is electrically connected to the power supply voltage vdd_pixel, and one end of the row select tube SEL is a signal output terminal. In the CMOS image sensor, the discharge tube PC and the row selection tube SEL are both in a low potential region and are closer to the photodiode PD, and the gates of the discharge tube PC and the row selection tube SEL are set to have a ring gate structure, and an electron depletion region is formed at the bottom of the isolation structure, so that dark current can be reduced, and a CMOS image sensor with high image quality can be obtained.

In summary, the present application provides an image sensor and a method for manufacturing the same, in which the gate of a row selection tube located on a low potential region is set to be a ring gate structure, and when the image sensor is operated, an electron depletion region is formed at the bottom of an isolation structure, so that dark current can be reduced, and a CMOS image sensor with high image quality can be obtained. By straddling the isolation structure and the active region with the annular gate structure, the effect of the field effect transistor can be enhanced more effectively, electrons are prevented from flowing to the photodiode, and the transmission of the source electrode or the drain electrode of the row selection transistor is facilitated. By reducing the size of the active region where the row select tube is located, the distance from electrons to the photodiode is equivalently increased, and the generation of dark current is further reduced by matching with the annular grid structure. The image sensor and the manufacturing method thereof provided by the application can be applied to CMOS image sensors with different pixel structure changes, and the image performance of the CMOS image sensor is improved.

The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims

1. An image sensor, comprising at least:

A substrate;

A photodiode disposed within the substrate;

a floating diffusion region disposed within the substrate;

2. The image sensor of claim 1, wherein the annular gate structure is one of a circular ring, an oval ring, a square ring, a rectangular ring, a polygonal ring, or a combination of a polygonal ring and a circular ring.

3. The image sensor of claim 1, wherein an isolation structure is provided between the row select tube and the photodiode for isolation.

4. The image sensor of claim 3 wherein a portion of the ring-shaped gate structure is located on the isolation structure between the row select tube and the photodiode.

5. The image sensor of claim 3 wherein a portion of the annular gate structure spans the isolation structure between the row select tubes and the photodiodes and a portion of the active area where the row select tubes are located.

6. The image sensor of claim 1, further comprising a reset tube and a source follower tube, the reset tube and the source follower tube being disposed between the pass transistor and the row select tube, the source follower tube being disposed proximate the row select tube.

7. The image sensor of claim 6, further comprising a first isolation structure and a second isolation structure, the first isolation structure being located between the reset tube and the photodiode and the source follower tube and the photodiode, the second isolation structure being located between the row select tube and the photodiode.

8. The image sensor of claim 7, wherein the second isolation structure has a size that is 1.2-1.5 times the size of the first isolation structure.

9. The image sensor of claim 1, further comprising a discharge tube, wherein a gate of the discharge tube is a ring-shaped gate structure, and wherein the discharge tube and the row select tube are located on adjacent sides of the photodiode.

10. A method for manufacturing an image sensor, comprising at least the steps of:

providing a substrate;

forming a photodiode within the substrate;

Forming a transfer transistor on the substrate;