CN115513241A - Image sensor and manufacturing method thereof - Google Patents
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- CN115513241A CN115513241A CN202211286294.XA CN202211286294A CN115513241A CN 115513241 A CN115513241 A CN 115513241A CN 202211286294 A CN202211286294 A CN 202211286294A CN 115513241 A CN115513241 A CN 115513241A
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor includes: a substrate; an isolation structure disposed on the substrate; the epitaxial layer is arranged on the substrate and wraps the isolation structure, and the height of the epitaxial layer is flush with that of the isolation structure; and a photodiode disposed within the epitaxial layer. By the image sensor and the manufacturing method thereof, the high-quality image sensor with low dark current is obtained.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an image sensor and a manufacturing method thereof.
Background
Complementary Metal Oxide Semiconductor Image sensors (CMOS Image sensors) have the advantages of high integration level, low voltage of power supply, low technical threshold, and the like, and are widely used in various fields such as consumer electronics, automatic driving, biological identification, security, and the like. Therefore, image quality requirements for CMOS image sensors are also increasing, and dark current is one of the main causes of deterioration of image sensor performance.
In the manufacturing process of an image sensor, especially in the STI (Shallow Trench Isolation) etching process, plasma bombards a substrate, which may cause serious damage at an etching interface, resulting in interface defects. These defects can trap charges to create dangling bonds, which in turn generate carriers that are not generated by photon conversion, resulting in dark current, resulting in degradation of image quality. By optimizing the measures of P-type isolation, STI depth, annealing repair, STI filling conductive material negative pressure and the like, the dark current can be improved, but damage to STI etching is not eliminated, and the improvement of the dark current is limited.
Disclosure of Invention
The invention aims to provide an image sensor and a manufacturing method thereof, and the image sensor and the manufacturing method thereof can avoid an STI (shallow trench isolation) etching process and improve the imaging quality of the image sensor.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides an image sensor, at least comprising:
a substrate;
an isolation structure disposed on the substrate;
the epitaxial layer is arranged on the substrate and wraps the isolation structure, and the height of the epitaxial layer is flush with that of the isolation structure;
a photodiode disposed within the epitaxial layer.
In an embodiment of the present invention, the isolation structure includes a second dielectric layer and a first dielectric layer, the first dielectric layer is disposed on the substrate, and the second dielectric layer is disposed on the first dielectric layer.
In an embodiment of the present invention, the isolation structure includes an oxide pillar, and the oxide pillar is disposed on the second dielectric layer.
In an embodiment of the present invention, the epitaxial layer is a homogeneous epitaxial layer, and the thickness of the epitaxial layer is 50nm to 3000nm.
In an embodiment of the invention, the image sensor further includes a transfer gate disposed on the epitaxial layer, and one side of the transfer gate is in contact with one side of the photodiode.
In an embodiment of the present invention, the image sensor further includes a floating diffusion region disposed within the epitaxial layer, and one side of the floating diffusion region is in contact with the other side of the transfer gate.
Another object of the present invention is to provide a method for manufacturing an image sensor, which at least includes the following steps:
providing a substrate;
forming an isolation structure on the substrate;
forming an epitaxial layer on the substrate, wherein the epitaxial layer wraps the isolation structure, and the height of the epitaxial layer is flush with that of the isolation structure; and
a photodiode is formed within the epitaxial layer.
In an embodiment of the present invention, the method for manufacturing the image sensor further includes:
forming a first dielectric layer on the substrate; and
and forming a first deep well region in the substrate by taking the first dielectric layer as an injection protective layer.
In an embodiment of the present invention, a method for forming the isolation structure includes:
forming a second dielectric layer on the first dielectric layer;
forming a third dielectric layer on the second dielectric layer;
etching part of the third dielectric layer to the second dielectric layer to form an oxide column;
changing etching conditions, and etching part of the second dielectric layer to the first dielectric layer; and
and etching part of the first dielectric layer by a wet method to form the isolation structure.
In an embodiment of the present invention, a high etching selectivity ratio is provided between the first dielectric layer and the substrate, between the first dielectric layer and the second dielectric layer, and between the third dielectric layer and the second dielectric layer.
In summary, the present invention provides an image sensor and a method for manufacturing the same, which reduces the interface damage between the isolation structure and the epitaxial layer, reduces the dark current of the image sensor, and improves the imaging quality of the image sensor. The deep well region is formed before homoepitaxy, so that the energy of ion implantation is reduced, the substrate lattice defect caused by the ion implantation can be reduced, and the performance of the image sensor is improved.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of an image sensor according to an embodiment.
Fig. 2 isbase:Sub>A cross-sectional view of fig. 1 atbase:Sub>A-base:Sub>A wherebase:Sub>A first dielectric layer is formed.
Fig. 3 isbase:Sub>A cross-sectional view of fig. 1 taken alongbase:Sub>A-base:Sub>A to formbase:Sub>A deep well region.
Fig. 4 isbase:Sub>A cross-sectional view of fig. 1 withbase:Sub>A second dielectric layer formed in the directionbase:Sub>A-base:Sub>A.
Fig. 5 isbase:Sub>A cross-sectional view of fig. 1 withbase:Sub>A third dielectric layer formed in the directionbase:Sub>A-base:Sub>A.
FIG. 6 isbase:Sub>A cross-sectional view of FIG. 1 showingbase:Sub>A first patterned photoresist layer formed in the direction A-A.
Fig. 7 isbase:Sub>A cross-sectional view of fig. 1 taken alongbase:Sub>A-base:Sub>A direction to form an oxide pillar.
Fig. 8 isbase:Sub>A cross-sectional view of fig. 1 taken alongbase:Sub>A-base:Sub>A to form an isolation structure.
Fig. 9 isbase:Sub>A cross-sectional view of fig. 1 taken alongbase:Sub>A-base:Sub>A to form an epitaxial layer.
Fig. 10 isbase:Sub>A cross-sectional view of fig. 1 showing the formation ofbase:Sub>A well region in the directionbase:Sub>A-base:Sub>A.
FIG. 11 isbase:Sub>A cross-sectional view of the gate material layer and the second patterned photoresist layer formed in the direction A-A of FIG. 1.
Fig. 12 isbase:Sub>A cross-sectional view of fig. 1 showing the formation ofbase:Sub>A transfer gate and sidewall structures in the directionbase:Sub>A-base:Sub>A.
Fig. 13 isbase:Sub>A cross-sectional view of fig. 1 inbase:Sub>A directionbase:Sub>A-base:Sub>A to formbase:Sub>A floating diffusion region.
Description of reference numerals:
10. a substrate; 101. a first well region; 102. a second well region; 103. a first isolation well region; 104. a second isolated well region; 11. a photodiode; 12. a floating diffusion region; 13. a transfer gate; 14. a reset tube; 15. a source follower tube; 16. a row selection pipe; 111. a first dielectric layer; 112. a second dielectric layer; 120. a deep well region; 130. a third dielectric layer; 140. a first patterned photoresist layer; 150. oxidizing the column; 151. an isolation structure; 160. an epitaxial layer; 170. oxidizing the sacrificial layer; 180. a gate oxide layer; 190. a gate material layer; 191. a second patterned photoresist layer; 200. and (5) a side wall structure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the drawings provided in this embodiment are only for schematically illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings and not drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may be more complicated.
In the present invention, it should be noted that, as the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, their indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present application and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first" and "second," if any, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, the present invention is not limited to the kind of image sensor, and for explaining the present application, the image sensor provided in the present embodiment is, for example, a CMOS image sensor with a 4T structure, and the image sensor includes a photodiode 11, a floating diffusion region 12, a transfer gate 13, a reset tube 14, a source follower tube 15, and a row selection tube 16; a floating diffusion region 12, a reset tube 14, a source follower tube 15 and a row select tube 16 are provided on the substrate 10. Here, the photodiode 11 is in a closed state during integration, the transfer gate 13 is opened after the accumulation of electrons is completed, and the electrons are transferred into the floating diffusion region 12 via the transfer gate 13 and then read out. The image sensor further comprises an isolation structure 151, wherein the isolation structure 151 is arranged between the photodiode 11 and other electronic components, the isolation structure 151 and the epitaxial layer on the substrate 10 are in the same height, and the isolation structure 151 is used for isolation. The image sensor provided by the invention is isolated through the isolation structure, so that the interface defect caused by the formation of the shallow trench isolation structure is avoided, the generation of dark current is reduced, and the imaging quality of the image sensor is improved.
Referring to fig. 1 to 2, in an embodiment of the invention, an image sensor includesbase:Sub>A plurality of photodiodes and other electronic components, in the embodiment,base:Sub>A manufacturing process of the image sensor is described by takingbase:Sub>A Photodiode (PD) in the image sensor as an example, andbase:Sub>A cross-sectional view of fig. 1 inbase:Sub>A-base:Sub>A direction is described as an example. Wherein fig. 2 isbase:Sub>A sectional view in the directionbase:Sub>A-base:Sub>A of fig. 1. First, a substrate 10 is provided, wherein the substrate 10 may be any suitable semiconductor material, for example, a substrate such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, or silicon wafer, a stacked structure composed of these semiconductors, or silicon on insulator, silicon germanium on insulator, or germanium on insulator, and the like, and may be specifically selected according to the manufacturing requirements of the image sensor. In the present embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate.
Referring to fig. 2, in an embodiment of the invention, a first dielectric layer 111 is formed on the substrate 10, and the first dielectric layer 111 is disposed on the substrate 10. Specifically, the first dielectric layer 111 is, for example, an insulating material such as dense silicon oxide, and the first dielectric layer 111 may be formed on the substrate 10 by any one of methods such as a dry oxygen oxidation method, a wet oxygen oxidation method, and an in-situ water vapor growth method, for example. In an embodiment, for example, the substrate 10 is placed in a furnace tube at a temperature of 900 ℃ to 1150 ℃, oxygen is introduced, the substrate 10 reacts with the oxygen at a high temperature, and the first dense dielectric layer 111 is generated, and the quality of the generated first dielectric layer 111 is good. The thickness of the first dielectric layer 111 is, for example, 8nm to 15nm, specifically, 8nm, 10nm, or 12 nm.
Referring to fig. 2 to 3, in an embodiment of the invention, fig. 3 isbase:Sub>A sectional view of fig. 1 inbase:Sub>A direction ofbase:Sub>A-base:Sub>A. After the first dielectric layer 111 is formed, the deep well region 120 is formed by using the first dielectric layer 111 as an injection protection layer. The deep well region 120 is formed inside the substrate 10 and is disposed away from the first dielectric layer 111. Specifically, the first dielectric layer 111 is used as an implantation protection layer, the implantation energy is, for example, 20KeV to 800KeV, and the implantation impurity is, for example, boron (B) or Boron Fluoride (BF) 2 + ) The P-type impurities are waited to form a deep well region 120 for isolating substrate noise and further isolating crosstalk between different electronic components. By arranging the first dielectric layer 111 as an implantation protection layer, monocrystalline silicon lattice defects in the substrate 10 caused by ion implantation are reduced, and dark current can be reduced. At the same time, composed ofThe deep well region 120 is formed before homoepitaxy, so that the energy of ion implantation is reduced, substrate lattice defects caused by ion implantation can be reduced, and the performance of the image sensor can be improved.
Referring to fig. 3 to 4, in an embodiment of the invention, fig. 4 isbase:Sub>A sectional view taken alongbase:Sub>A directionbase:Sub>A-base:Sub>A in fig. 1. After the formation of the deep well region 120, a second dielectric layer 112 is formed on the first dielectric layer 111, and the second dielectric layer 112 is, for example, an insulating material with a large etching selectivity ratio to the first dielectric layer 111, such as silicon nitride. In the present invention, the second dielectric layer 112 may be formed on the first dielectric layer 111 by, for example, LPCVD (Low Pressure Chemical Vapor Deposition). Specifically, for example, the substrate 10 with the first dielectric layer 111 is placed in a furnace tube filled with dichlorosilane and ammonia gas, and reacted at a pressure of, for example, 2T to 10T and at a temperature of, for example, 700 ℃ to 800 ℃ to deposit the second dielectric layer 112. The thickness of the second dielectric layer 112 can be adjusted by controlling the heating time, and the thickness of the second dielectric layer 112 is, for example, 15nm to 25nm, specifically, 15nm, 18nm, 20nm, 22nm, or 24 nm. Second dielectric layer 112 may protect substrate 10 from the etch process involved in the formation of the oxide pillar.
Referring to fig. 4 to 5, in an embodiment of the invention, fig. 5 isbase:Sub>A sectional view of fig. 1 inbase:Sub>A direction ofbase:Sub>A-base:Sub>A. After forming the second dielectric layer 112, a third dielectric layer 130 is formed on the second dielectric layer 112, and the third dielectric layer 130 is an insulating layer such as silicon dioxide. In the present embodiment, the third dielectric layer 130 is formed by a Chemical Vapor Deposition (CVD), a Low-pressure CVD (LPCVD), a Plasma Enhanced CVD (PECVD), or the like. In the present embodiment, for example, tetraethoxysilane (TEOS) and oxygen (O) 2 ) As a reactant, a third dielectric layer 130 is formed on the second dielectric layer 112 using a plasma enhanced chemical vapor deposition method. Specifically, the flow rate of the oxygen gas may be, for example, 1000sccm to 3000sccm, the flow rate of the tetraethoxysilane liquid may be, for example, 400mgm to 1000mgm, and the radio frequency power may be, for example, 500W to 900W. Of the third dielectric layer 130 formedThe coverage is good, the mobility of the surface of tetraethyl orthosilicate (TEOS) is high, low-density areas or cavities can be avoided, and the quality of the third dielectric layer 130 is improved. The thickness of the third dielectric layer 130 is determined according to the thickness of the epitaxial layer required subsequently, i.e. the sum of the thicknesses of the third dielectric layer 130, the second dielectric layer 112 and the first dielectric layer 111 is equal to the thickness of the epitaxial layer formed subsequently. In one embodiment of the present invention, the thickness of the third dielectric layer 130 is, for example, 30nm to 3000nm.
Referring to fig. 5 to 6, in an embodiment of the invention, fig. 6 isbase:Sub>A sectional view taken alongbase:Sub>A directionbase:Sub>A-base:Sub>A in fig. 1. After the third dielectric layer 130 is formed, a photoresist layer is formed on the third dielectric layer 130, and an exposure and development process is performed on the photoresist layer to form a first patterned photoresist layer 140, where the first patterned photoresist layer 140 is used to position the oxide pillar 150. The third dielectric layer 130 is etched using the first patterned photoresist layer 140 as a mask to form an oxide pillar 150.
Referring to fig. 6 to 7, in an embodiment of the invention, fig. 7 isbase:Sub>A sectional view taken alongbase:Sub>A directionbase:Sub>A-base:Sub>A in fig. 1. After the first patterned photoresist layer 140 is formed, for example, dry etching is performed toward the substrate 10 to remove the third dielectric layer 130 outside the first patterned photoresist layer 140, so as to form the oxide pillar 150. And the etching gas may be, for example, chlorine (Cl) 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Carbon tetrafluoride (SF) 4 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) Or hydrogen bromide (HBr) or the like. In the etching process, the second dielectric layer 112 is used as an etching stop layer. After the third dielectric layer 130 is etched to the second dielectric layer 112, the etching conditions, such as the etching gas, the etching gas ratio or the etching power, are changed to etch the second dielectric layer 112, and the first dielectric layer 111 is used as an etching stop layer for the second dielectric layer 112. In this example, the gas for etching the third dielectric layer 130 is, for example, a mixed gas of carbon tetrafluoride and trifluoromethane, and the gas for etching the second dielectric layer 112 is, for example, a mixed gas of trifluoromethane and difluoromethane. After the etching is completed, the remaining first patterned photoresist layer 140 is removed, and the first patterned photoresist layer 140 is, for example, etched byAnd removing oxygen plasma or wet method, and removing part of the first dielectric layer 111 by wet etching. In the specific production, etching gas selection is performed according to the materials of the first dielectric layer 111, the second dielectric layer 112 and the third dielectric layer 130, so that the different layers are ensured to have larger etching selection ratio. In other embodiments, a wet etching process or a combination of a wet etching process and a dry etching process may be selected to remove a portion of second dielectric layer 112 and a portion of third dielectric layer 130. By arranging the second dielectric layer 112, an over-etching phenomenon is prevented from occurring in the process of forming the oxide pillar 150, and the substrate is prevented from being damaged by etching the first dielectric layer 111 or the substrate 10.
Referring to fig. 7 to 8, fig. 8 isbase:Sub>A sectional view taken alongbase:Sub>A-base:Sub>A direction of fig. 1 according to an embodiment of the present invention. After the oxide pillar 150 is formed, the first dielectric layer 111 outside the oxide pillar 150 is removed, for example, by wet etching, and the surface of the substrate 10 is exposed. The wet etching solution is one or a mixture of hydrofluoric acid (HF), buffered silicon oxide etching solution (BOE), buffered hydrofluoric acid (BHF) and the like. The thickness of the first dielectric layer 111 is small, the wet etching time is short, and the etching selection ratio of the etching liquid to the first dielectric layer 111 and the substrate 10 is large, so that the substrate 10 can be prevented from being scratched by dry etching, the damage to the substrate 10 is reduced, and the dark current condition of the image sensor is improved. After the etching of the first dielectric layer 111 is completed, the remaining first dielectric layer 111 and the remaining second dielectric layer 112 below the oxide pillar 150 and the oxide pillar 150 define an isolation structure 151 for isolating different electronic components in the image sensor. The method for forming the isolation structure 151 provided by the invention does not need the forming process of the shallow trench isolation structure, and avoids the interface defect caused by the etching damage of the shallow trench isolation structure, thereby reducing the dark current caused by the interface defect.
Referring to fig. 8 to 9, in an embodiment of the invention, fig. 9 isbase:Sub>A sectional view taken alongbase:Sub>A directionbase:Sub>A-base:Sub>A in fig. 1. After the isolation structure 151 is formed, an epitaxial layer 160 is formed on the substrate 10 through an epitaxial process, the epitaxial layer 160 wraps the isolation structure 151, and the height of the epitaxial layer 160 is flush with the height of the isolation structure 151. Specifically, the epitaxial layer 160 is formed by, for example, vapor phase epitaxial growth or vacuum epitaxyThe epitaxial layer 160 and the substrate 10 are formed by, for example, homoepitaxy, a liquid phase epitaxial growth method, or the like. In the present embodiment, the epitaxial layer 160 is formed by, for example, a vapor phase epitaxial growth method, and the epitaxial layer 160 is, for example, single crystal silicon. Specifically, a silicon source, such as dichlorosilane (SiH), is reacted at an elevated temperature to form the epitaxial layer 160 2 Cl 2 ) Trichlorosilane (SiHCl) 3 ) Tetrachlorosilane (SiCl) 4 ) Silane (SiH) 4 ) Etc. and during deposition, for example, hydrogen gas is introduced to react, and the reaction temperature is controlled at 950-1250 deg.c. By controlling the reaction time, it is ensured that the height of the epitaxial layer 160 is flush with the height of the isolation structure 151. In the production process, according to the requirements of the manufactured image sensor, the preset thickness of the epitaxial layer is determined, then the isolation structure 151 with the same thickness as the preset thickness is formed, and finally the epitaxial layer 160 flush with the isolation structure 151 is deposited, namely the thickness of the epitaxial layer can be adjusted in advance to meet the manufacturing requirements of different image sensors. By forming the isolation structure 151 first and then forming the epitaxial layer, the shallow trench isolation structure process is avoided, and the generation of dark current can be reduced. In an embodiment of the present invention, the thickness of the epitaxial layer 160 is, for example, 50nm to 3000nm, and the anti-electronic-interference capability of the image sensor can be improved by adjusting the thickness of the epitaxial layer 160.
Referring to fig. 9 to 10, in an embodiment of the invention, fig. 10 isbase:Sub>A sectional view taken alongbase:Sub>A directionbase:Sub>A-base:Sub>A in fig. 1. After the epitaxial layer 160 is formed, a sacrificial oxide layer 170 is formed on the surface of the epitaxial layer 160, the sacrificial oxide layer 170 is made of, for example, silicon oxide, and the sacrificial oxide layer 170 has a thickness of, for example, 1nm to 15nm. The sacrificial oxide layer 170 is formed by, for example, a thermal oxidation method, chemical Vapor Deposition (cvd), physical Vapor Deposition (PVD), or the like. In the present embodiment, the sacrificial oxide layer 170 is formed, for example, by an In-situ steam Generation (ISSG) method, in which oxygen containing a small amount of steam is introduced during the reaction process, and a large amount of oxygen radicals are generated at 900 to 1100 ℃, and the oxygen radicals react with exposed silicon to form silicon dioxide, but the oxygen radicals do not react with silicon oxide, so that the sacrificial oxide layer 170 is formed on the surface of the epitaxial layer 160.
Referring to fig. 10, in an embodiment of the invention, after forming the sacrificial oxide layer 170, ion implantation is performed to form a plurality of well regions. First, impurity ions are implanted outside the isolation structure 151 to form the first isolation well 103 and the second isolation well 104, and the impurity ions of the first isolation well 103 and the second isolation well 104 are P-type impurities such as boron (B). In the present embodiment, the first isolation well 103 wraps the isolation structure 151, the second isolation well 104 wraps the first isolation well 103, and the depth of the second isolation well 104 extends to the deep well 120, so as to ensure the isolation effect. The doping concentration of the first isolation well region 103 is greater than that of the first well region 101, so that the depletion region of the photodiode is prevented from widening to the interface of the isolation structure, and dark current caused by interface defects is reduced. The second isolation well region 104 serves as isolation between the photodiodes, so that the isolation effect between the photodiodes is further improved, and mutual interference between the photodiodes is reduced.
Referring to fig. 10, in an embodiment of the invention, in the epitaxial layer 160 between the isolation structures 151, a first type impurity ion is implanted using the sacrificial oxide layer 170 as an ion implantation buffer layer to form a first well region 101, and the first well region 101 contacts with a second isolation well region 104 on one side. The second type impurity ions are implanted into the first well region 101 with low implantation energy to form the second well region 102, and the second well region 102 is formed on the first well region 101 due to different implantation energies, that is, the depth of the first well region 101 is greater than that of the second well region 102, and the depth of the first well region 101 may be greater than that of the epitaxial layer 160, or less than that of the epitaxial layer 160, or equal to that of the epitaxial layer 160, specifically according to the manufacturing requirements. The widths of the first well region 101 and the second well region 102 are equal, for example, 0.5 μm to 5 μm, that is, the size of the photodiode is 0.5 μm to 5 μm. The second well region 102 is, for example, one hundred and fifty to one third of the depth of the first well region 101. In the present embodiment, the first type impurity ions are different in type from the second type impurity ions, wherein the first type impurity ions are, for example, N-type impurities such As phosphorus (P) or arsenic (As), and the second type impurity ions are, for example, P-type impurities such As boron (B), that is, the doping types of the first well region 101 and the second well region 102 are different. In other embodiments, the first type impurity ions may also be P-type impurities, and the second type impurity ions may be N-type impurities, which may be selected according to the manufacturing requirements of the image sensor. In this embodiment, the doping concentration of the formed second well region 102 is ensured to be greater than that of the first well region 101, a built-in electric field pointing from the first well region 101 to the second well region 102 is formed, and by arranging the second well region 102 with high doping concentration, the depletion region of the first well region 101 is prevented from widening towards the surface of the epitaxial layer 160, and the dark current caused by the dangling bond on the surface of the epitaxial layer 160 is reduced. And the sacrificial layer 170 is oxidized to reduce the damage to the epitaxial layer 160 during the ion implantation process, thereby further reducing the generation of dark current.
Referring to fig. 10 to 11, in an embodiment of the invention, fig. 11 isbase:Sub>A sectional view taken alongbase:Sub>A-base:Sub>A direction of fig. 1. After the formation of the plurality of well regions, the surface of the epitaxial layer 160 is removed by, for example, a wet process to form a sacrificial oxide layer 170, and the gate oxide layer 180 is formed again. The material of the gate oxide layer 180 is, for example, silicon oxide, and the thickness of the gate oxide layer 180 is, for example, 5nm to 15nm. The gate oxide layer 180 is formed by, for example, a thermal oxidation method, a chemical Vapor Deposition (cvd), a Physical Vapor Deposition (PVD), or the like. In the present embodiment, the gate oxide layer 180 is formed by, for example, an In-situ steam Generation (ISSG) method, and the formed gate oxide layer 180 is located on the surface of the epitaxial layer 160. The gate oxide layer 180 formed by the in-situ steam generation method has few in-vivo defects and a relatively small interface state density, and is beneficial to improving the performance of the image sensor.
Referring to fig. 11, in an embodiment of the invention, after forming the gate oxide layer 180, a gate material layer 190 is formed on the gate oxide layer 180 and the isolation structure 151. In the present embodiment, the gate material layer 190 is, for example, a polysilicon layer, and the polysilicon layer may be doped polysilicon or undoped polysilicon, and the doping type may be P type or N type. The thickness of the gate material layer 190 on the epitaxial layer 160 is, for example, 100nm to 400nm, and in other embodiments, the thickness of the gate material layer 190 may be set according to actual requirements. A second patterned photoresist layer 191 is formed on the gate material layer 190, one side of the second patterned photoresist layer 191 is aligned with the edge of the second well 102, and the other side of the second patterned photoresist layer 191 extends away from the second well 102 to cover the gate material layer 190 where the transfer gate is to be formed.
Referring to fig. 11 to 12, in an embodiment of the invention, fig. 12 isbase:Sub>A sectional view taken alongbase:Sub>A directionbase:Sub>A-base:Sub>A in fig. 1. With the second patterned photoresist layer 191, the gate material layer 190 is then etched by, for example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process to form the transfer gate 13. In this embodiment, the gate material layer 190 is anisotropically etched using, for example, a dry etching process. After the etching is completed, the second patterned photoresist layer 191 is removed, and the second patterned photoresist layer 191 is removed, for example, by oxygen plasma or wet method.
Referring to fig. 12, in an embodiment of the invention, after the transfer gate 13 is formed, sidewall structures 200 are formed on two sides of the transfer gate 13, and specifically, a sidewall dielectric layer (not shown) is formed on the transfer gate 13, the isolation structure 151 and the epitaxial layer 160, and the material of the sidewall dielectric layer is, for example, silicon oxide, silicon nitride or a stacked layer of silicon oxide and silicon nitride. After the formation of the sidewall dielectric layer, for example, dry etching and other etching processes may be used to remove the sidewall dielectric layer on the transfer gate 13, part of the isolation structure 151 and part of the epitaxial layer 160, and the sidewall dielectric layers on both sides of the transfer gate 13 are retained to form the sidewall structure 200. The height of the side wall structure 200 is the same as that of the transfer gate 13, the width of the side wall structure 200 is gradually increased from the top to the bottom of the transfer gate 13, and the insulating side wall structure 200 is arranged to prevent the electric leakage phenomenon. In this embodiment, the shape of the sidewall structure 200 is, for example, an arc shape, and in other embodiments, the shape of the sidewall structure 200 may also be other shapes, which may be selected according to the manufacturing requirements.
Referring to fig. 12 to 13, in an embodiment of the invention, fig. 13 isbase:Sub>A sectional view taken alongbase:Sub>A directionbase:Sub>A-base:Sub>A in fig. 1. After the sidewall structure 200 is formed, the first type impurity ions are implanted with low implantation energy into the epitaxial layer 160 on the other side of the transfer gate 13 opposite to the first well region 101 and the second well region 102, so as to form the floating diffusion region 12. That is, the ion implantation type of the floating diffusion region 12 is the same as that of the first well region 101, and the ion implantation depth of the floating diffusion region 12 is equal to that of the second well region 102 in order of magnitude. In the present embodiment, the width of the floating diffusion region 12 is, for example, one tenth to one third of the width of the first well region 101. The sensitivity of the image sensor can be improved by reducing the ratio of the size of the floating diffusion region 12 to the size of the first well region 101. During the operation of the image sensor, each photodiode is connected to the floating diffusion region 12 through the transfer gate 13, the photodiode converts an optical signal into an electrical signal, and signal electrons are transmitted to the floating diffusion region 12 through the transfer gate 13, thereby realizing the conversion of the optical signal into the electrical signal. The isolation structure 151 is used for isolating adjacent semiconductor components, and in the present invention, the manufacturing method and structure of the isolation structure 151 may be applied to CMOS image sensors with 5T structure, 6T structure, 7T structure, 8T structure and more pixel structure changes, so as to improve the performance of the CMOS image sensor. After the floating diffusion region 12 is formed, the fabrication of the dielectric layer, the metal interconnection structure, the color filter, and the like may be continued on the epitaxial layer 160 and the transfer gate 13, and the fabrication method may adopt a general fabrication method of the dielectric layer, the metal interconnection structure, and the microlens, which will not be described herein, and the image sensor may select a Back Side Illumination (BSI) process or a Front Side Illumination (FSI) process during the fabrication process.
In summary, the invention provides an image sensor and a manufacturing method thereof, by forming an isolation structure on a substrate, and then forming an epitaxial layer on the substrate, where the epitaxial layer is flush with the isolation structure, a shallow trench isolation structure process is avoided, interface damage between the isolation structure and the epitaxial layer is reduced, dark current of the image sensor is reduced, and imaging quality of the image sensor is improved. In the process of forming the isolation structure, a first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially formed on the substrate, and the third dielectric layer, the second dielectric layer and the first dielectric layer are sequentially etched, so that the damage to the surface of the substrate is reduced, and the dark current of the image sensor is further reduced.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. An image sensor, characterized by comprising at least:
a substrate;
an isolation structure disposed on the substrate;
the epitaxial layer is arranged on the substrate and wraps the isolation structure, and the height of the epitaxial layer is flush with that of the isolation structure;
a photodiode disposed within the epitaxial layer.
2. The image sensor of claim 1, wherein the isolation structure comprises a second dielectric layer and a first dielectric layer, the first dielectric layer disposed on the substrate, the second dielectric layer disposed on the first dielectric layer.
3. The image sensor of claim 2, wherein the isolation structure comprises an oxide pillar disposed on the second dielectric layer.
4. The image sensor of claim 1, wherein the epitaxial layer is a homoepitaxial layer and the epitaxial layer is 50nm to 3000nm thick.
5. The image sensor of claim 1, further comprising a transfer gate disposed on the epitaxial layer, and wherein a side of the transfer gate contacts a side of the photodiode.
6. The image sensor of claim 5, further comprising a floating diffusion region disposed within the epitaxial layer, wherein one side of the floating diffusion region is in contact with another side of the transfer gate.
7. A method for manufacturing an image sensor is characterized by at least comprising the following steps:
providing a substrate;
forming an isolation structure on the substrate;
forming an epitaxial layer on the substrate, wherein the epitaxial layer wraps the isolation structure, and the height of the epitaxial layer is flush with that of the isolation structure; and
a photodiode is formed within the epitaxial layer.
8. The method of claim 7, wherein the method further comprises:
forming a first dielectric layer on the substrate; and
and forming a first deep well region in the substrate by taking the first dielectric layer as an injection protective layer.
9. The method for manufacturing the image sensor according to claim 8, wherein the method for forming the isolation structure comprises:
forming a second dielectric layer on the first dielectric layer;
forming a third dielectric layer on the second dielectric layer;
etching part of the third dielectric layer to the second dielectric layer to form an oxide column;
changing etching conditions, and etching part of the second dielectric layer to the first dielectric layer; and
and etching part of the first dielectric layer by a wet method to form the isolation structure.
10. The method of claim 9, wherein a high etch selectivity is provided between the first dielectric layer and the substrate, between the first dielectric layer and the second dielectric layer, and between the third dielectric layer and the second dielectric layer.
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