CN116936593A - Image sensor and manufacturing method thereof - Google Patents
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- CN116936593A CN116936593A CN202311139638.9A CN202311139638A CN116936593A CN 116936593 A CN116936593 A CN 116936593A CN 202311139638 A CN202311139638 A CN 202311139638A CN 116936593 A CN116936593 A CN 116936593A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 238000009792 diffusion process Methods 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 19
- ILRRQNADMUWWFW-UHFFFAOYSA-K aluminium phosphate Chemical compound O1[Al]2OP1(=O)O2 ILRRQNADMUWWFW-UHFFFAOYSA-K 0.000 claims description 4
- WSMQKESQZFQMFW-UHFFFAOYSA-N 5-methyl-pyrazole-3-carboxylic acid Chemical compound CC1=CC(C(O)=O)=NN1 WSMQKESQZFQMFW-UHFFFAOYSA-N 0.000 claims description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 3
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 142
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 239000012535 impurity Substances 0.000 description 14
- 150000004767 nitrides Chemical class 0.000 description 12
- 238000001039 wet etching Methods 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 4
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000000725 suspension Substances 0.000 description 4
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 3
- 229910018503 SF6 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000003014 reinforcing effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 3
- 229960000909 sulfur hexafluoride Drugs 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- -1 or the like Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14623—Optical shielding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14625—Optical elements or arrangements associated with the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
Abstract
The application discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor includes: a substrate; a photodiode disposed within the substrate; a transfer tube disposed on the substrate, the transfer tube including a transfer gate, one side of the transfer gate being aligned with an edge of the photodiode; an enhancement trench is disposed within the substrate below the transfer gate, and the enhancement trench is disposed in contact with the photodiode; a piezoelectric layer arranged on the side wall and the bottom of the enhancement groove and the bottom of one side of the transfer grid close to the photodiode; and a floating diffusion region disposed within the substrate on a side of the transfer gate opposite the photodiode. The image sensor and the manufacturing method thereof can improve the photoelectric charge transfer efficiency and reduce the dark current of the image sensor.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to an image sensor and a manufacturing method thereof.
Background
The complementary metal oxide semiconductor image sensor (Complementary Metal Oxide Semiconductor Image Sensor, CMOS image sensor) has the advantages of high integration level, low power supply voltage, low technical threshold and the like, and is widely applied to the fields of consumer electronics, automatic driving, biological recognition or security protection and the like. There is an increasing demand for image quality, and dark current is an important cause of deterioration in image quality. The dangling bond below the side wall is one of the main sources of dark current, and passivation of the dangling bond is a technological difficulty. At present, when dark current is reduced by passivating a suspension bond below a side wall, photoelectric charge transfer efficiency is reduced due to high-dose P-type injection below the side wall, the purpose of reducing dark current by fully passivating the suspension bond is not achieved due to low-dose P-type injection below the side wall, and development and application of an image sensor are limited.
Disclosure of Invention
The application aims to provide an image sensor and a manufacturing method thereof, by which the photoelectric charge transfer efficiency can be improved and the dark current of the image sensor can be reduced.
In order to solve the technical problems, the application is realized by the following technical scheme:
the application provides an image sensor, comprising at least:
a substrate;
a photodiode disposed within the substrate;
a transfer tube disposed on the substrate, the transfer tube including a transfer gate, one side of the transfer gate being aligned with an edge of the photodiode;
an enhancement trench is disposed within the substrate below the transfer gate, and the enhancement trench is disposed in contact with the photodiode;
a piezoelectric layer arranged on the side wall and the bottom of the enhancement groove and the bottom of one side of the transfer grid close to the photodiode; and
a floating diffusion region disposed within the substrate on a side of the transfer gate opposite the photodiode.
In an embodiment of the present application, the material of the piezoelectric layer includes at least one of zirconium dioxide, lithium niobate, lithium tantalate, or aluminum phosphate.
In one embodiment of the present application, the thickness of the piezoelectric layer is 10nm to 20nm.
In an embodiment of the present application, the image sensor further includes a gate oxide layer disposed on the substrate and sidewalls and bottom of the enhancement trench, and the piezoelectric layer is disposed on the gate oxide layer.
In one embodiment of the present application, the photodiode includes a first well region, and one side of the transfer gate is aligned with an edge of the first well region.
In an embodiment of the present application, sidewall structures are disposed on two sides of the transfer gate.
In an embodiment of the present application, the photodiode includes a second well region disposed on the first well region, wherein a side of the second well region away from the transfer gate is aligned with an edge of the first well region, and a side of the second well region close to the transfer gate is aligned with an edge of the sidewall structure
In an embodiment of the present application, a depth of the second well region is equal to a depth of the enhancement trench.
Another object of the present application is to provide a method for manufacturing an image sensor, at least comprising the following steps:
providing a substrate;
forming a photodiode within the substrate;
forming an enhancement trench in the substrate, the enhancement trench being disposed in contact with the photodiode;
forming a piezoelectric layer on the sidewalls and bottom of the enhancement trench and on the photodiode;
forming a transfer tube on the substrate, the transfer tube comprising a transfer gate, one side of the transfer gate being aligned with an edge of the photodiode, and the transfer gate being disposed over the enhancement trench, removing the piezoelectric layer in an area other than the transfer gate; and
a floating diffusion region is formed within the substrate on a side of the transfer gate opposite the photodiode.
In an embodiment of the application, the method for manufacturing the image sensor includes the following steps:
forming an isolation structure in the substrate;
forming a first well region between adjacent isolation structures;
forming the enhancement trench in the substrate, wherein one side of the enhancement trench is in contact with the first well region;
forming a gate oxide layer on the substrate and in the enhancement trench;
forming the piezoelectric layer on the oxide layer;
etching the piezoelectric layer, and reserving the piezoelectric layer in the first well region and the enhancement groove; and
the transfer gate is formed on the substrate, one side of the transfer gate is aligned with an edge of the first well region, and the piezoelectric layer of the region outside the transfer gate is removed.
In an embodiment of the present application, the manufacturing method further includes the following steps:
forming side wall structures on two sides of the transfer grid electrode; and
and forming a second well region on the first well region.
In summary, the image sensor and the manufacturing method thereof provided by the application can generate compressive stress when the transfer tube is closed, and the width of the forbidden band of monocrystalline silicon below the side wall structure can be increased by the compressive stress to passivate the dangling bond and reduce dark current, so that high-dose P-type ions do not need to be injected below the side wall structure, and the influence on charge transmission is avoided. Meanwhile, the length of a channel of the transfer tube is increased, and electric leakage is reduced. The isolation well region can prevent the depletion region of the photodiode from widening towards the interface of the isolation structure, and dark current caused by interface defects is reduced. The isolation effect between the photodiodes can be further improved, and the mutual interference between the photodiodes can be reduced. The application of the second well region with high doping concentration in combination with the enhancement groove and the piezoelectric material can ensure that the dangling bond on the surface of the substrate is passivated, the dark current is improved, the increase of the potential barrier height of the source region of the transfer tube caused by the second type impurity ion implantation at the bottom of the side wall structure is avoided, and the transfer efficiency of the photo-charges is not influenced. Thereby ensuring transfer efficiency of photo-charges and improving performance of the image sensor while reducing dark current.
Of course, it is not necessary for any one product to practice the application to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an image sensor according to an embodiment.
Figure 2 is a cross-sectional view of the positioning isolation structure of figure 1 along the A-A direction.
Figure 3 is a cross-sectional view of the isolation structure and first well region formed along the direction A-A of figure 1.
Fig. 4 is a cross-sectional view of the positioning reinforcement groove along the A-A direction of fig. 1.
Fig. 5 is a cross-sectional view of the enhancement trench, gate oxide layer and piezoelectric layer formed along the A-A direction of fig. 1.
Fig. 6 is a cross-sectional view of the piezoelectric layer of fig. 1 after etching in the A-A direction.
Fig. 7 is a cross-sectional view of fig. 1 with a layer of gate material formed in the direction A-A.
Fig. 8 is a cross-sectional view of the transfer gate formed along the A-A direction of fig. 1.
Fig. 9 is a cross-sectional view of the sidewall structure, floating diffusion region, and second well region formed along the A-A direction of fig. 1.
Fig. 10 is a cross-sectional view of the protective layer formed along A-A in fig. 1.
FIG. 11 is a cross-sectional view of the image sensor shown in FIG. 1 taken along the A-A direction in one embodiment.
Fig. 12 is a potential diagram of the image sensor of fig. 11 in operation.
Fig. 13 is a potential diagram of an embodiment of an image sensor operating without the enhancement trench and the piezoelectric layer at the bottom of the transfer gate and with high dose of the second type impurity ions under the sidewall structure.
Description of the reference numerals:
10. a substrate; 101. a first well region; 102. a second well region; 103. an isolation well region; 11. an isolation structure; 12. a photodiode; 13. a transfer tube; 14. a floating diffusion region; 15. a reset tube; 16. a source follower; 17. a row selection tube; 110. a pad oxide layer; 120. pad nitriding layer; 130. a first photoresist layer; 131. a first opening; 132. a second photoresist layer; 133. a second opening; 140. reinforcing the trench; 150. a gate oxide layer; 160. a piezoelectric layer; 171. a gate material layer; 170. a transfer gate; 180. a side wall structure; 181. a side wall dielectric layer; 190. a protective layer; 200. an interlayer dielectric layer; 21. a first conductive plug; 22. and a second conductive plug.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present application, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
Referring to fig. 1 and 12, the image sensor is not limited in kind, and for illustrating the present application, the image sensor provided in this embodiment is, for example, a CMOS image sensor of a 4T structure, and the image sensor includes a photodiode 12, a transfer tube 13, a floating diffusion 14, a reset tube 15, a source follower tube 16, a row select tube 17, and the like, which are disposed on a substrate 10. The photodiode 12 is in a closed state during integration, the transfer tube 13 is opened after the electron accumulation is completed, and the electrons are transmitted into the floating diffusion region 14 through the transfer tube 13 and are read out.
Referring to fig. 1 to 10, in an embodiment of the present application, fig. 2 to 10 are sectional views of fig. 1 in A-A direction. In the present embodiment, a cross-sectional view of the image sensor in the A-A direction is taken as an example, and a process of manufacturing the image sensor is described. First, a substrate 10 is provided, where the substrate 10 may be any suitable semiconductor material, for example, a substrate such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, or silicon wafer, and a stacked structure formed by these semiconductors, or be silicon on insulator, silicon germanium on insulator, and germanium on insulator, which may be specifically selected according to the manufacturing requirements of the image sensor. In the present embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate.
Referring to fig. 2, in an embodiment of the present application, a pad oxide layer 110 is formed on a substrate 10, and the pad oxide layer 110 is made of a material such as dense silicon oxide, for example, the pad oxide layer 110 may be formed on the substrate 10 by a thermal oxidation method or an in situ vapor growth method. In this embodiment, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900-1150 ℃, oxygen is introduced into the furnace tube, the substrate 10 reacts with oxygen at a high temperature to produce a dense pad oxide layer 110, and the thickness of the pad oxide layer 110 is, for example, 10-30 nm. After the pad oxide layer 110 is formed, a pad nitride layer 120 is formed on the pad oxide layer 110, wherein the pad nitride layer 120 is, for example, silicon nitride or a mixed layer of silicon nitride and silicon oxide, and in this embodiment, the pad nitride layer 120 is, for example, silicon nitride. Wherein the pad oxide layer 110 serves as a buffer layer to improve the stress between the substrate 10 and the pad nitride layer 120. In the present application, the pad nitride layer 120 may be formed on the pad oxide layer 110 by, for example, low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD). In some embodiments, pad nitride layer 120 has a thickness of, for example, 50nm to 150nm, and for example, 110 nm.
Referring to fig. 2 to 3, in an embodiment of the application, a first photoresist layer 130 is formed on the pad nitride layer 120. A plurality of first openings 131 are formed on the first photoresist layer 130 through processes such as exposure and development, and the first openings 131 are used for positioning the isolation structures. The pad nitride layer 120 exposed by the first opening 131 is quantitatively removed by using the first photoresist layer 130 as a mask and using dry etching, wet etching or etching methods combining dry etching and wet etching, and then the pad oxide layer 110 and a part of the substrate 10 are removed in situ by using the pad nitride layer 120 as a mask, so as to obtain a shallow trench (not shown in the figure), wherein the shallow trench is located below the first opening 131. In the present embodiment, for example, a shallow trench is formed by dry etching, and the etching gas is, for example, chlorine (Cl) 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) Or hydrogen bromide (HBr), or the like, or a combination of one or more of them and oxygen (O 2 ) Is a mixture of (a) and (b). And cleaning the etching byproducts by wet etching after the etching is finished.
Referring to fig. 2 to 3, in an embodiment of the present application, fig. 3 is a cross-sectional view of fig. 1 in A-A direction. An isolation medium (not shown) such as an insulating material, for example, silicon oxide, is deposited in the shallow trench by, for example, high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor deposition (High Aspect Ratio Process CVD, HARP-CVD). After the isolation medium deposition is completed, a planarization process such as chemical mechanical polishing (Chemical Mechanical Polishing, CMP) is performed to place the isolation medium and the top of the pad nitride layer 120 on the same plane, forming a plurality of isolation structures 11. After forming the isolation structures 11, the pad nitride layer 120 on the substrate 10 is removed, and the pad nitride layer 120 is removed, for example, by a wet process, and the wet etching solution is, for example, hot phosphoric acid or the like. In this embodiment, the depth of the isolation structure 11 in the substrate 10 is, for example, 200nm to 400nm. By providing a plurality of isolation structures 11, the photodiodes or other semiconductor devices are isolated. The plurality of photodiodes in the image sensor or other semiconductor devices are isolated by the isolation structure 11, so that the mutual interference among the semiconductor devices is reduced, and the performance of the image sensor is improved.
Referring to fig. 3, in an embodiment of the present application, after forming the isolation structure 11, ion implantation is performed into the substrate to form a plurality of well regions. Specifically, a patterned photoresist layer (not shown) is formed, and an isolation well region 103 is formed around the isolation structure 11, where the impurity ions in the isolation well region 103 are P-type impurities such as boron (B). By forming the isolation well region 103, the photodiode depletion region is prevented from widening towards the isolation structure interface, and dark current caused by interface defects is reduced. Meanwhile, the isolation effect between the photodiodes can be further improved, and the mutual interference between the photodiodes is reduced.
Referring to fig. 3, in an embodiment of the present application, after forming the isolation well region 103, a patterned photoresist layer (not shown) is formed on the substrate 10 again, and the first type impurity ions, such As N-type impurities including phosphorus (P) or arsenic (As), are implanted into the first well region 101 by using the patterned photoresist layer As a mask and using the pad oxide layer 110 As an ion implantation buffer layer. The first well region 101 is disposed between adjacent isolation structures 11, and one side of the first well region 101 contacts with one isolation well region 103, and the other side of the first well region is a predetermined distance from the other isolation well region 103, so as to form a transfer gate and a floating diffusion region.
Referring to fig. 3 to 5, in an embodiment of the present application, fig. 4 and 5 are sectional views of fig. 1 in A-A direction. After the first well region 101 is formed, a second photoresist layer 132 is formed on the pad oxide layer 110 and the isolation structure 11, and a second opening 133 is formed on the second photoresist layer 132 through processes such as exposure and development, and the second opening 133 is used to locate the enhancement trench 140. Wherein one side of the second opening 133 is located above the substrate 10 where the first well region 101 is not located, and one side is aligned with an edge of the first well region 101 within the substrate 10. Taking the second photoresist layer 132 as a mask, quantitatively removing the pad oxide layer 110 and part of the substrate 10 exposed by the second photoresist layer 132 by using dry etching, wet etching or etching methods of combining dry etching and wet etching, and the like, thereby obtaining the enhanced trench 140. In this embodiment, for example, the reinforcing groove is formed by dry etching, and the etching gas is, for example, one or a combination of several of chlorine, trifluoromethane, difluoromethane, nitrogen trifluoride, sulfur hexafluoride, hydrogen bromide, or the like, or a mixture of them and oxygen. And cleaning the etching byproducts by wet etching after the etching is finished. The depth of the enhancement trench 140 is smaller than the depth of the shallow trench, and may be specifically selected according to the manufacturing requirements. By forming the reinforcing grooves 140, the compressive stress effect can be enhanced while increasing the transfer tube channel length and reducing leakage.
Referring to FIG. 5, in one embodiment of the present application, after the enhancement trench 140 is formed, the pad oxide layer 110 on the surface of the substrate 10 is removed, and the gate oxide layer 150 is regrown by 5nm to 10 nm. The gate oxide layer 150 is also formed on the sidewall and the bottom of the enhancement trench 140, and the gate oxide layer 150 is, for example, a silicon oxide layer, and the gate oxide layer 150 may be formed by, for example, a thermal oxidation method or an in-situ vapor growth method. The pad oxide layer 110 is removed, for example, by wet etching, and the wet etching liquid is, for example, hydrofluoric acid or a buffered oxide etching liquid (Buffered Oxide Etch, BOE) or the like. In other embodiments, removal may be performed in other ways.
Referring to fig. 5, in one embodiment of the present application, after regrowing the gate oxide layer 150, a piezoelectric layer 160 is formed on the gate oxide layer 150. The material of the piezoelectric layer 160 includes, for example, zirconium dioxide (ZrO 2 ) Lithium niobate (LiNbO) 3 ) Lithium tantalate (LiTaO) 3 ) Or aluminum phosphate (AlPO) 4 ) At least one of the piezoelectric materials is provided, and the thickness of the piezoelectric layer 160 is, for example, 10nm to 20nm. The piezoelectric layer 160 is formed by, for example, atomic layer deposition (Atomic Layer Deposition, ALD), metal-organic vapor deposition (Metal-Organic Chemical Vapor Deposition, MOCVD), chemical vapor deposition (cvd), or physical vapor deposition (Physical Vapor Deposition, PVD), and the like, and may be selected according to the manufacturing requirements.
Referring to fig. 5 to 6, in an embodiment of the present application, fig. 6 is a cross-sectional view of fig. 1 in A-A direction. After the piezoelectric layer 160 is formed, a patterned photoresist layer (not shown) is formed on the piezoelectric layer 160, and covers the first well region 101 and the piezoelectric layer 160 on the enhancement trench 140. The patterned photoresist layer is used as a mask, and the piezoelectric layer 160 located in the area outside the patterned photoresist layer and the enhancement trench 140 is quantitatively removed by using dry etching, wet etching or etching methods such as dry etching and wet etching combined with each other, that is, only the piezoelectric layer 160 located on the first well region 101 and in the enhancement trench 140 is remained. After the etching is completed, the patterned photoresist layer is removed, for example, by oxygen plasma removal or wet removal.
Referring to fig. 1, 6-8, in an embodiment of the present application, fig. 7 and 8 are cross-sectional views of fig. 1 in A-A direction. After the piezoelectric layer 160 is etched, a gate material layer 171 is formed on the substrate 10 and in the enhancement trench 140, where the gate material layer 171 is, for example, polysilicon or a metal material, and the polysilicon is a doped polysilicon layer or an undoped polysilicon, and the metal material may be magnesium, aluminum, nickel, copper, gold, silver, a TiAl-based alloy, titanium carbide, tantalum carbide, tungsten silicide, or an alloy of several materials. After forming the gate material layer 171, a patterned photoresist layer (not shown) is formed on the gate material layer 171, and the gate material layer is etched, for example, by dry etching, using the patterned photoresist layer as a mask, to form the transfer gate 170, and the transfer gate 170 is used to form the transfer tube 13 in a subsequent manufacturing process. In this embodiment, the transfer gate 170 is formed on the enhancement trench 140, with one side aligned with the edge of the first well region 101, i.e., one side of the transfer gate 170 is aligned with the edge of a photodiode to be formed later, and the other side extends toward the substrate 10 on the side away from the first well region 101, covering a portion of the gate oxide layer 150 on the substrate 10, and the transfer gate 170 has a predetermined distance from the isolation structure 11 on the side away from the first well region 101 for providing a floating diffusion region. During the etching of the gate material layer 171, the piezoelectric layer 160 outside the transfer gate 170 is etched away. I.e., the piezoelectric layer 160 is formed on the sidewalls and bottom of the enhancement trench 140 and on the bottom of the transfer gate 170 near one side of the photodiode.
Referring to fig. 8, in an embodiment of the present application, during the process of forming the transfer gate 170, the piezoelectric layer 160 is etched simultaneously when the gate material layer is etched, but at the side of the transfer gate 170 close to the photodiode, the piezoelectric layer 160 is partially under the transfer gate 170, and the piezoelectric layer 160 may generate a compressive stress when the transfer tube is closed (gate plus negative pressure), so that the forbidden band width of monocrystalline silicon under the sidewall structure is increased to passivate the dangling bonds by the compressive stress. Meanwhile, high-dose P-type ions do not need to be injected below the side wall structure, and charge transmission is not affected.
Referring to fig. 8 to 9, in an embodiment of the present application, fig. 9 is a cross-sectional view of fig. 1 in A-A direction. A sidewall structure 180 is formed on both sides of the transfer gate 170, specifically, a sidewall dielectric layer 181 is formed on the transfer gate 170, the isolation structure 11 and the gate oxide layer 150, and the material of the sidewall dielectric layer 181 is, for example, a silicon oxide and silicon nitride stacked material, and the contact layer with the substrate 10 and the transfer gate 170 is silicon oxide. After forming the sidewall dielectric layer 181, for example, an etching process such as dry etching may be used to remove the transfer gate 170, part of the isolation structure 11, and part of the silicon nitride layer on the substrate 10, and the sidewall dielectric layer 181 on the photodiode, the sidewall dielectric layer 181 on the side of the transfer gate 170 away from the photodiode, and part of the sidewall dielectric layer 181 on the isolation structure 11 are reserved. On both sides of the transfer gate 170, the height of the sidewall structure 180 is identical to the height of the transfer gate 170, and the width of the sidewall structure 180 gradually increases from top to bottom of the transfer gate 170, so that the leakage phenomenon is prevented by providing the insulating sidewall structure 180. In this embodiment, the shape of the side wall structure 180 is, for example, arc, and in other embodiments, the shape of the side wall structure 180 may be other shapes, which may be selected according to the manufacturing requirements.
Referring to fig. 9, in an embodiment of the present application, after forming the sidewall structure 180, a high dose of second type impurity ions is implanted into the first well region 101 with a low implantation energy to form a second well region 102 with a high doping concentration, and the second well region 102 is formed on the first well region 101 due to different implantation energies, i.e. the depth of the first well region 101 is greater than the depth of the second well region 102. Wherein, a side of the second well region 102 away from the transfer gate 170 is aligned with an edge of the first well region 101, a side of the second well region 101 close to the transfer gate 170 is aligned with an edge of the sidewall structure 180, i.e. aligned with an edge of the sidewall structure 180 away from the transfer gate 170, i.e. the bottom of the sidewall structure 180 is not provided with the second well region 102, and a width of the first well region 101 is larger than a width of the second well region 102. The depth of the first well region 101 is less than or equal to the depth of the isolation well region 103, the depth of the second well region 102 is, for example, one hundredth to one fiftieth of the depth of the first well region 101, and the depth of the second well region 102 is, for example, equal to the depth of the enhancement trench 140. In this embodiment, the second type impurity ions are P-type impurities such as boron (B), that is, the doping types of the first well region 101 and the second well region 102 are different. Wherein, the doping concentration of the formed second well region 102 is ensured to be larger than that of the first well region 101, a built-in electric field directed to the second well region 102 by the first well region 101 is formed, and by arranging the second well region 102 with high doping concentration, the broadening of the depletion region of the first well region 101 towards the surface of the substrate 10 is avoided, and the dark current caused by the dangling bond on the surface of the substrate 10 is reduced. By forming the second well region 102 after forming the sidewall structure 180, it is ensured that the dangling bonds on the surface of the substrate are passivated, dark current is improved, and meanwhile, the increase of the barrier height of the source region of the transfer tube caused by the second type impurity ion implantation at the bottom of the sidewall structure is avoided, and the transfer efficiency of photo-charges is not affected. Meanwhile, due to the arrangement of the piezoelectric layer, the suspension bond can be passivated by increasing the forbidden bandwidth of monocrystalline silicon below the side wall through compressive stress, and the suspension bond on the surface of the photodiode below the side wall structure is passivated, so that dark current is reduced, and the performance of the image sensor is improved.
Referring to fig. 9, in an embodiment of the present application, after forming the second well region 102, impurity ions are implanted at a low implantation energy into the substrate 10 at one side of the transfer gate 170 opposite to the first well region 101 and the second well region 102, thereby forming the floating diffusion region 14. The ion implantation type of the floating diffusion region 14 is the same as that of the first well region 101, and the ion implantation depth of the floating diffusion region 14 and the ion implantation depth of the second well region 102 are on the order of magnitude. Wherein the size of the floating diffusion region 14 is smaller than the size of the first well region 101, and the sensitivity of the image sensor is improved by reducing the ratio of the size of the floating diffusion region 14 to the size of the first well region 101.
Referring to fig. 9 to 10, in an embodiment of the present application, fig. 10 is a cross-sectional view of fig. 1 in A-A direction. After forming the floating diffusion region 14, a protective layer 190 is formed on the substrate, the protective layer 190 covering the transfer gate 170, the sidewall dielectric layer 181, the sidewall structure 180, the isolation structure 11, and the like. In this embodiment, the protective layer 190 includes, for example, a barrier layer and a contact hole etching stop layer (not shown in the figure), and the contact hole etching stop layer is provided on the barrier layer. The blocking layer is formed by chemical vapor deposition, for example, and has a thickness of 20 nm-30 nm to protect the photodiode, the transfer gate, the floating diffusion region, and the like. After forming the barrier layer, a contact etch stop layer is formed on the substrate 10, the contact etch stop layer covering the barrier layer. The contact hole etching stop layer is, for example, a silicon nitride layer, and is formed, for example, by chemical vapor deposition or the like, and the thickness of the contact hole etching stop layer is, for example, 40nm to 60nm.
Referring to fig. 10 to 11, in an embodiment of the present application, fig. 11 is a cross-sectional view of fig. 1 in A-A direction. After the protective layer 190 is formed, an interlayer dielectric layer 200 (Inter layer dielectric, ILD) is formed on the protective layer 190, the interlayer dielectric layer 200 is, for example, a silicon oxide layer, and the interlayer dielectric layer 200 is formed by, for example, chemical vapor deposition or high density plasma chemical vapor deposition method. After the interlayer dielectric layer 200 is formed, planarization is performed to ensure that the surfaces of the interlayer dielectric layer 200 are in the same plane, and the thickness of the interlayer dielectric layer 200 is, for example, 300nm to 800nm. The interlayer dielectric layer 200 is etched to form a plurality of openings (not shown) in the interlayer dielectric layer 200, and a conductive material is deposited in the openings, for example, a metal material is deposited in the openings by a physical vapor deposition process or a sputtering process, for example, a titanium/titanium nitride barrier layer and tungsten metal are deposited, thereby forming conductive plugs. The conductive plugs include a first conductive plug 21 and a second conductive plug 22, wherein the first conductive plug 21 is connected to the transfer gate 170 and the second conductive plug 22 is connected to the floating diffusion region 14 to connect the transfer gate 170 and the floating diffusion region 14 to a circuit. In the present application, the fabrication method and structure of the transfer gate 170 can also be applied to CMOS image sensors with 5T structure, 6T structure, 7T structure, 8T and more pixel structure variations, for improving the performance of the CMOS image sensor.
Referring to fig. 12 to 13, in an embodiment of the present application, fig. 12 is a potential diagram of the CMOS image sensor shown in fig. 11 when the CMOS image sensor is in operation, and fig. 13 is a potential diagram of the CMOS image sensor in operation when the bottom of the transfer gate is not provided with the enhancement trench and the piezoelectric layer and the high dose of the second type impurity ions is located under the sidewall structure. When the image sensor provided by the application works, the photodiode PD is connected with the floating diffusion area FD through the transfer tube Tx, the photodiode converts an optical signal into an electric signal, and photo-generated electrons are transmitted to the floating diffusion area FD through the transfer tube Tx, so that the conversion from the optical signal to the electric signal is realized. Specifically, in the first stage (Step 1), the transfer tube Tx is turned off, the initial potential barrier of the transfer tube Tx is high, the photodiode PD performs photoelectric conversion, photo-generated electrons are accumulated in the photodiode PD, and the photo-generated electrons cannot cross the transfer tube Tx into the floating diffusion FD. In the second stage (Step 2), to start the transfer stage, the transfer tube Tx is opened, and the photo-generated electrons start to be transferred into the floating diffusion FD through the transfer tube Tx, at which time the potential of the transfer tube Tx is between the photodiode PD and the floating diffusion FD, and the photo-generated electrons can be rapidly transferred into the floating diffusion FD. In the third stage (Step 3), in order to complete the transfer, the transfer tube Tx is opened and the photo-generated electrons are completely transferred into the floating diffusion FD, and no photo-generated electrons remain in the photodiode PD and the photo-generated electrons are completely transferred into the floating diffusion FD. In the fourth stage (Step 4), the transfer tube Tx is turned off and the potential of the transfer tube Tx is restored to the original state for the transfer completion stage. According to the CMOS image sensor provided by the application, the increase of the barrier height of the source region of the transfer tube caused by the second type impurity ion implantation at the bottom of the side wall structure can be avoided, the phenomenon that part of photo-generated electrons remain in the photodiode PD in the third stage can be avoided, and the photo-charge transfer efficiency is improved, so that the imaging quality of the image sensor is improved.
In summary, the present application provides an image sensor and a method for manufacturing the same, in which an enhancement trench and a piezoelectric layer are disposed on a side of a transfer gate near a photodiode, the piezoelectric layer can generate compressive stress when the transfer tube is closed, and the compressive stress can increase the forbidden bandwidth of monocrystalline silicon under a sidewall structure to passivate a dangling bond. Meanwhile, high-dose P-type ions do not need to be injected below the side wall structure, and charge transmission is prevented from being influenced. The enhancement groove can enhance the effect of compressive stress, and meanwhile, the channel length of the transfer tube is increased, and the electric leakage is reduced. By forming the isolation well region, the photodiode depletion region can be prevented from widening towards the isolation structure interface, and dark current caused by interface defects is reduced. Meanwhile, the isolation effect between the photodiodes can be further improved, and the mutual interference between the photodiodes is reduced. By forming the second well region after the side wall structure is formed, passivation of the hanging bond on the surface of the substrate can be ensured, dark current is improved, meanwhile, increase of barrier height of the source region of the transfer tube caused by second type impurity ion implantation at the bottom of the side wall structure is avoided, and transfer efficiency of photo-charges is not affected. Meanwhile, the arrangement of the piezoelectric layer ensures that dangling bonds on the surface of the photodiode below the side wall structure are passivated, so that dark current is reduced, and the performance of the image sensor is improved.
The embodiments of the application disclosed above are intended only to help illustrate the application. The examples are not intended to be exhaustive or to limit the application to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best understand and utilize the application. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (11)
1. An image sensor, comprising at least:
a substrate;
a photodiode disposed within the substrate;
a transfer tube disposed on the substrate, the transfer tube including a transfer gate, one side of the transfer gate being aligned with an edge of the photodiode;
an enhancement trench is disposed within the substrate below the transfer gate, and the enhancement trench is disposed in contact with the photodiode;
a piezoelectric layer arranged on the side wall and the bottom of the enhancement groove and the bottom of one side of the transfer grid close to the photodiode; and
a floating diffusion region disposed within the substrate on a side of the transfer gate opposite the photodiode.
2. The image sensor of claim 1, wherein the material of the piezoelectric layer comprises at least one of zirconium dioxide, lithium niobate, lithium tantalate, or aluminum phosphate.
3. The image sensor of claim 1, wherein the piezoelectric layer has a thickness of 10nm to 20nm.
4. The image sensor of claim 1, further comprising a gate oxide layer disposed on the substrate and sidewalls and bottom of the enhancement trench, the piezoelectric layer disposed on the gate oxide layer.
5. The image sensor of claim 1, wherein the photodiode comprises a first well region, and wherein one side of the transfer gate is aligned with an edge of the first well region.
6. The image sensor of claim 5, wherein the transfer gate is provided with sidewall structures on both sides.
7. The image sensor of claim 6, wherein the photodiode comprises a second well region disposed on the first well region, and wherein a side of the second well region remote from the transfer gate is aligned with an edge of the first well region and a side proximate to the transfer gate is aligned with an edge of the sidewall structure.
8. The image sensor of claim 7, wherein a depth of the second well region is equal to a depth of the enhancement trench.
9. A method for manufacturing an image sensor, comprising at least the steps of:
providing a substrate;
forming a photodiode within the substrate;
forming an enhancement trench in the substrate, the enhancement trench being disposed in contact with the photodiode;
forming a piezoelectric layer on the sidewalls and bottom of the enhancement trench and on the photodiode;
forming a transfer tube on the substrate, the transfer tube comprising a transfer gate, one side of the transfer gate being aligned with an edge of the photodiode, and the transfer gate being disposed over the enhancement trench, removing the piezoelectric layer in an area other than the transfer gate; and
a floating diffusion region is formed within the substrate on a side of the transfer gate opposite the photodiode.
10. The method of manufacturing an image sensor according to claim 9, characterized in that the method of manufacturing an image sensor comprises the steps of:
forming an isolation structure in the substrate;
forming a first well region between adjacent isolation structures;
forming the enhancement trench in the substrate, wherein one side of the enhancement trench is in contact with the first well region;
forming a gate oxide layer on the substrate and in the enhancement trench;
forming the piezoelectric layer on the oxide layer;
etching the piezoelectric layer, and reserving the piezoelectric layer in the first well region and the enhancement groove; and
the transfer gate is formed on the substrate, one side of the transfer gate is aligned with an edge of the first well region, and the piezoelectric layer of the region outside the transfer gate is removed.
11. The method of manufacturing an image sensor of claim 10, further comprising the steps of:
forming side wall structures on two sides of the transfer grid electrode; and
and forming a second well region on the first well region.
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