CN116072703B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN116072703B
CN116072703B CN202310042319.XA CN202310042319A CN116072703B CN 116072703 B CN116072703 B CN 116072703B CN 202310042319 A CN202310042319 A CN 202310042319A CN 116072703 B CN116072703 B CN 116072703B
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region
oxide layer
semiconductor device
gate
substrate
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CN116072703A (en
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汪华
杨宗凯
陈信全
程洋
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Nexchip Semiconductor Corp
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Nexchip Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The semiconductor device includes: a substrate comprising an active region and an isolation region; a gate oxide layer disposed on the substrate; the grid electrode structure is arranged on the grid electrode oxide layer, and a first preset distance is reserved between the grid electrode oxide layer at the interface of the active region and the isolation region and the grid electrode structure at one side of the grid electrode structure far away from the isolation region; the source doping region is arranged in the active region at one side of the grid structure; and the drain doping region is arranged in the active region at the other side of the grid structure. The semiconductor device and the manufacturing method thereof provided by the invention have the advantages that the yield and the performance of the semiconductor device are improved.

Description

Semiconductor device and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor device and a manufacturing method thereof.
Background
In the manufacturing process of the semiconductor chip, after the gate oxide layer is formed, the etching process for removing part of the gate oxide layer is usually wet etching, the gate oxide layer in the removed area is etched, the wet etching has high selectivity and good uniformity, the bottom of the material is not damaged, but the isotropy is easy to cause serious side etching in the reserved area of the gate oxide layer, and the performance and the product yield of the device are affected.
In forming an asymmetric Metal-oxide semiconductor field effect transistor (MOS), for example, an asymmetric junction device (MOS), an interface of a gate oxide layer at a source end spans an Active Area (AA) and a shallow trench isolation structure (Shallow Trench Isolation, STI), and due to a height difference between the AA and the STI, side etching of the gate oxide layer is serious during a process, resulting in a short circuit between a subsequent gate structure and a substrate, thereby affecting a yield of the semiconductor device.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, by which the yield of the semiconductor device is improved and the performance of the semiconductor device is improved.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides a semiconductor device including:
a substrate comprising an active region and an isolation region;
a gate oxide layer disposed on the substrate;
the grid electrode structure is arranged on the grid electrode oxide layer, and a first preset distance is reserved between the grid electrode oxide layer at the interface of the active region and the isolation region and the grid electrode structure at one side of the grid electrode structure far away from the isolation region;
the source doping region is arranged in the active region at one side of the grid structure; and
the drain doping region is arranged in the active region at the other side of the grid structure.
In an embodiment of the present invention, the first preset distance is 0.8 μm to 1.1 μm.
In an embodiment of the present invention, a second preset distance is provided between the gate oxide layer and the gate structure between the active region and the isolation region on a side of the gate structure away from the isolation region.
In an embodiment of the present invention, the second preset distance is 0.1 μm to 0.3 μm.
In an embodiment of the present invention, the shape of the isolation region is a "U" shape or a "concave" shape.
In an embodiment of the present invention, the gate structure extends to two sides of the isolation region in a channel width direction, and two ends of the gate structure cover a portion of the isolation region.
In an embodiment of the present invention, the semiconductor device further includes a sidewall structure, the sidewall structure is disposed on two sides of the gate structure, and the sidewall structure is disposed on the gate oxide layer.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
providing a substrate, wherein the substrate comprises an active region and an isolation region;
forming a gate oxide layer on the substrate;
forming a gate structure on the gate oxide layer, wherein a first preset distance is reserved between the gate structure and the gate oxide layer at the interface of the active region and the isolation region at one side of the gate structure away from the isolation region;
forming a source doping region in the active region at one side of the grid structure; and
and forming a drain doping region in the active region at the other side of the gate structure.
In an embodiment of the present invention, after the source doping region and the drain doping region are formed, the shallow trench isolation structures of the gate oxide layer and the isolation region are etched to form an oxide layer region.
In an embodiment of the present invention, the oxide layer region wraps around the gate structure and a region between the gate structure and the isolation region.
In summary, the present invention provides a semiconductor device and a method for manufacturing the same, which increase the distance from the gate oxide layer at the interface between the isolation region and the active region to the gate structure, so as to avoid device failure caused by the defect of the gate oxide layer in the semiconductor device, and improve the yield of the semiconductor device. In the manufacturing process, no extra process step is needed, the device layout is improved under the condition that the area of the semiconductor device is unchanged, the manufacturing cost is not increased, and meanwhile, the performance of the semiconductor device is improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a top view of a semiconductor device according to an embodiment.
Fig. 2 is a schematic view of fig. 1 in a direction A-A to form a first photoresist layer.
FIG. 3 is a schematic diagram of the first photoresist layer formed along the direction B-B in FIG. 1.
Fig. 4 is a schematic view of the shallow trench formation along A-A in fig. 1.
Fig. 5 is a schematic view of the shallow trench formation along the direction B-B in fig. 1.
FIG. 6 is a schematic diagram of the shallow trench isolation structure of FIG. 1 along the A-A direction.
Fig. 7 is a schematic diagram of the shallow trench isolation structure formed along the direction B-B in fig. 1.
Fig. 8 is a top view of a shallow trench isolation structure and an active region in one embodiment.
Fig. 9 is a schematic diagram of forming a gate oxide layer along A-A in fig. 1.
Fig. 10 is a schematic diagram of forming a gate oxide layer along the direction B-B in fig. 1.
Fig. 11 is a schematic diagram of the gate structure formed along A-A in fig. 1.
Fig. 12 is a schematic view of the doped region formed along the A-A direction in fig. 1.
Fig. 13 is a schematic view of the doped region formed in the direction B-B in fig. 1.
FIG. 14 is a top view of an embodiment of etching a gate oxide layer using a second photoresist layer as a mask.
Fig. 15 is a schematic view of fig. 1 after etching the gate oxide layer in the direction A-A.
Fig. 16 is a schematic diagram of fig. 1 after etching the gate oxide layer in the direction B-B.
Fig. 17 is a schematic view of forming a sidewall structure along A-A in fig. 1.
Fig. 18 is a schematic view of the salicide block layer formed along the A-A direction of fig. 1.
Fig. 19 is a schematic view of the self-aligned silicide blocking layer formed along the direction B-B of fig. 1.
Fig. 20 is a schematic view of the electrode formed along A-A in fig. 1.
Fig. 21 is a schematic view of the electrode formed in the direction B-B of fig. 1.
Description of the reference numerals:
10. a substrate; 11. a pad oxide layer; 12. pad nitriding layer; 13. a first photoresist layer; 131. a first opening; 141. a shallow trench; 14. shallow trench isolation structures; 15. a gate oxide layer; 151. a second photoresist layer; 152. an oxide layer region; 16. a gate structure; 171. a first doped region; 172. a second doped region; 18. a side wall structure; 181. a second opening; 19. a salicide block layer; 20. an interlayer dielectric layer; 21. a source electrode; 22. a gate; 23. and a drain electrode.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present invention, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
The semiconductor device and the manufacturing method thereof provided by the invention have the advantages that the layout of the semiconductor device is designed, the device failure caused by the defect of the grid electrode oxide layer in the semiconductor device can be avoided, and the yield of the semiconductor device is improved. And the manufacturing method is simple, the layout of the semiconductor device is improved under the condition that the area of the semiconductor device is unchanged, and the manufacturing cost is low. The obtained semiconductor device can be widely applied to various fields of communication, traffic, energy, medicine, household appliances, aerospace and the like.
Referring to fig. 1, in an embodiment of the present invention, a patterned device is illustrated, and isolation between adjacent patterned devices or between a patterned device and other semiconductor devices is performed on the same substrate, for example, by a shallow trench isolation structure. The substrate 10 is provided first, and the substrate 10 may be any material suitable for forming, for example, a semiconductor material formed of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer, or other III/V compound, etc., and a stacked structure formed of these semiconductor materials, or a silicon on insulator, a stacked silicon on insulator, a silicon germanium on insulator, a germanium on insulator, etc. The material of the substrate 10 is not limited in the present invention, and the substrate 10 may be a P-doped semiconductor substrate or an N-doped semiconductor substrate, and in this embodiment, the substrate 10 is, for example, a P-doped silicon substrate.
Referring to fig. 1 to 3, in an embodiment of the present invention, fig. 2 is a cross-sectional view of fig. 1 in A-A direction, and fig. 3 is a cross-sectional view of fig. 1 in B-B direction. The pad oxide layer 11 is formed on the substrate 10, the pad oxide layer 11 being, for example, a material such as dense silicon oxide, and the pad oxide layer 11 may be formed on the substrate 10 by, for example, a dry oxygen oxidation method, a wet oxygen oxidation method, an In-situ vapor growth method (In-Situ Steam Generation, ISSG), or a chemical vapor deposition (Chemical Vapor Deposition, CVD) method. In this embodiment, the pad oxide layer 11 is, for example, a silicon oxide layer, and the substrate 10 is placed in a furnace tube at a temperature of, for example, 950 ℃ to 1150 ℃ and oxygen mixed with a small amount of hydrogen is introduced, so that the substrate 10 reacts with the oxygen at a high temperature to generate a dense pad oxide layer 11. The thickness of the pad oxide layer 11 is, for example, 70nm to 100nm, specifically 70nm, 80nm, 90nm, 100nm, or the like.
Referring to fig. 2 to 3, in an embodiment of the present invention, after forming the pad oxide layer 11, a pad nitride layer 12 is formed on the pad oxide layer 11, and the pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. Wherein the pad oxide layer 11 serves as a buffer layer to improve the stress between the substrate 10 and the pad nitride layer 12. In the present invention, the pad nitride layer 12 may be formed on the pad oxide layer 11 by, for example, low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or the like. Specifically, for example, the substrate 10 with the pad oxide layer 11 is placed in a furnace filled with dichlorosilane and ammonia gas, and the pad nitride layer 12 is deposited by reacting at a pressure of, for example, 2t to 10t and a temperature of, for example, 700 ℃ to 800 ℃. Wherein the pad nitride layer 12 and the pad oxide layer 11 are formed, for example, in the same device, i.e., after the formation of the pad oxide layer 11, the device parameters are controlled to form the pad nitride layer 12, so as to simplify the manufacturing process. The thickness of the pad nitride layer 12 is 70nm to 90nm, specifically 70nm, 80nm, 900nm, or the like, for example. The pad nitride layer 12 protects the substrate 10 and the pad oxide layer 11 from processes such as chemical mechanical polishing planarization (Chemical Mechanical Polishing, CMP) involved in the fabrication of shallow trench isolation structures. And the pad nitride layer 12 can be used as a mask in the shallow trench formation process, and protects the substrate 10 and the pad oxide layer 11 at other positions from being damaged when the substrate 10 is etched.
Referring to fig. 2 to 3, in an embodiment of the present invention, a first photoresist layer 13 may be formed on the pad nitride layer 12 by, for example, spin coating. The first photoresist layer 13 is exposed and developed, and a first opening 131 is formed on the first photoresist layer 13 to locate the shallow trench isolation structure. In this embodiment, the first opening 131 is disposed, for example, in a "U" shape or a "concave" shape, and the substrate in the "U" shape or the "concave" shape opening is used to dispose the gate structure and the doped region.
Please refer to fig. 4-5, in the followingIn an embodiment of the present invention, fig. 4 is a cross-sectional view of fig. 1 in A-A direction, and fig. 5 is a cross-sectional view of fig. 1 in B-B direction. Etching is performed in the direction of the substrate 10 by using the first photoresist layer 13 with the first opening 131 as a mask, and the pad nitride layer 12, the pad oxide layer 11 and a part of the substrate 10 exposed by the first opening 131 are removed to form a shallow trench 141. In the present embodiment, for example, the shallow trench 141 is selectively formed by dry etching, and the etching gas includes, for example, chlorine (Cl) 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) And hydrogen bromide (HBr) or the like, or a mixture thereof with oxygen (O 2 ) Is a combination of (a) and (b).
Referring to fig. 6 to 7, in an embodiment of the present invention, fig. 6 is a cross-sectional view of fig. 1 in A-A direction, and fig. 7 is a cross-sectional view of fig. 1 in B-B direction. An insulating medium is deposited within shallow trench 141 to form shallow trench isolation structure 14. Specifically, an insulating medium is deposited within shallow trench 141 until the surface of pad nitride layer 12 is covered. Optionally, the substrate 10 may be annealed in an oxygen atmosphere prior to depositing the insulating medium to form an inner liner oxide layer (not shown) in the shallow trench 141 to reduce leakage. The invention is not limited to the deposition of the insulating medium, and the corresponding insulating medium can be formed by, for example, high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor deposition (High Aspect Ratio Process CVD, HARP-CVD). After the insulating medium is deposited, a high temperature (e.g., 800-1200 ℃) tempering process may be performed to increase the density and stress of the insulating medium. The insulating medium is, for example, silicon oxide with high adaptability to the grinding tool, and in other embodiments, the insulating medium may be an insulating material such as fluorosilicone glass.
Referring to fig. 6 to 8, fig. 8 is a top view of a shallow trench isolation structure and a substrate in an embodiment of the invention. After forming the insulating medium, the insulating medium is subjected to a planarization process, for example, a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process is used to planarize the insulating medium and a portion of the pad nitride layer 12 so that the heights of the insulating medium and the pad nitride layer 12 are uniform. The pad nitride layer 12 after polishing is then etched and removed, and the invention is not limited to the method of removing the pad nitride layer 12, for example, dry etching, wet etching, or the like. In this embodiment, for example, wet etching is performed using an acid solution, specifically phosphoric acid with a volume fraction of, for example, 85% -88%, and the pad nitride layer 12 is etched at, for example, 150 ℃ -165 ℃. After removing the pad nitride layer 12, the pad oxide layer 11 is removed by replacing the etching solution, for example, by replacing it with hydrofluoric acid or buffered oxide etching solution (Buffered Oxide Etch, BOE), so that a step is formed between the substrate 10 and the shallow trench isolation structure 14, and the step height is 10nm to 20nm, for example. After the shallow trench isolation structure 14 is formed, the region of the substrate 10 where the shallow trench isolation structure 14 is located is defined as an isolation region, and the remaining region is defined as an active region, i.e., the isolation region is configured, for example, in a "U" shape or a "concave" shape.
Referring to fig. 9 to 10, in an embodiment of the present invention, fig. 9 is a cross-sectional view of fig. 1 in A-A direction, and fig. 10 is a cross-sectional view of fig. 1 in B-B direction. After forming the shallow trench isolation structure 14, a gate oxide layer 15 is formed on the substrate 10 through a thermal oxidation process. In this embodiment, the gate oxide layer 15 is formed, for example, by an in-situ vapor growth method, and the thickness of the formed gate oxide layer 15 is, for example, 8nm to 15nm. In the process of forming the gate oxide layer 15, the shallow trench isolation structure 14 area is not affected, the original thickness is maintained, and the thickness of the gate oxide layer 15 is smaller than the step height between the shallow trench isolation structure 14 and the substrate 10. By reforming the gate oxide layer 15, the effect of front-end process fluctuations on the device is repaired and prevented.
Referring to FIG. 11, in an embodiment of the present invention, FIG. 11 is a cross-sectional view of FIG. 1 in the direction A-A. After the gate oxide layer 15 is formed, a gate material layer (not shown) is formed on the gate oxide layer 15. The gate material layer is, for example, a polysilicon layer, and the polysilicon layer may be P-type doped or N-type doped, and the doping type of the gate material layer is different from the doping type of the substrate 10. In this embodiment, the gate material layer is, for example, N-type doped polysilicon, and the thickness of the gate material layer is, for example, 300nm to 400nm, and in other embodiments, the thickness of the gate material layer may be set according to actual needs. A patterned photoresist layer (not shown) is formed on the gate material layer, and the gate material layer is etched, for example, by a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process, with the patterned photoresist layer as a mask, and in this embodiment, the gate material layer is sequentially anisotropically etched, for example, by a dry etching process, to form the gate structure 16. In which, in the A-A direction of fig. 1, the dimension of the gate structure 16 on the active region is defined as a channel length (channel length), in the B-B direction of fig. 1, the dimension of the gate structure 16 on the active region is defined as a channel width (channel width), the gate structure 16 extends to both sides of the isolation region in the channel width direction, and both ends of the gate structure 16 cover part of the isolation region.
Referring to fig. 12 to 13, in an embodiment of the present invention, fig. 12 is a cross-sectional view of fig. 1 in A-A direction, and fig. 13 is a cross-sectional view of fig. 1 in B-B direction. After forming the gate structure 16, doped regions are formed in the substrate 10 on either side of the gate structure 16 to serve as source and drain doped regions for the semiconductor device. The doped region includes a first doped region 171 and a second doped region 172, and the doping types of the first doped region 171 and the second doped region 172 are the same and opposite to the doping type of the substrate 10. In this embodiment, the doping ions of the first doping region 171 and the second doping region 172 are, for example, N-type ions such As phosphorus (P) or arsenic (As), where the first doping region 171 serves As a source doping region of the semiconductor device and the second doping region 172 serves As a drain doping region of the semiconductor device. The gate oxide layer 15 can protect the substrate 10 from damage during ion implantation.
Referring to fig. 1, 14-16, fig. 14 is a top view of the second photoresist layer, fig. 15 is a cross-sectional view in A-A direction of fig. 1, and fig. 16 is a cross-sectional view in B-B direction of fig. 1. In one embodiment of the present invention, after the doped region is formed, a portion of gate oxide layer 15 is removed. Specifically, a second photoresist layer 151 is formed on the substrate 10, where the second photoresist layer 151 locates the remaining gate oxide layer 15 and the shallow trench isolation structure 14, and the second photoresist layer 151 also exposes the gate oxide layer 15 at a later formation drain position. The second photoresist layer 151 is used as a mask, and the gate oxide layer 15 and part of the shallow trench isolation structure 14 in the region outside the second photoresist layer 151 are removed by dry etching or wet etching. In this embodiment, the gate oxide layer 15 and a portion of the shallow trench isolation structure 14 are removed, for example, by wet etching, and the gate oxide layer 15 and a portion of the shallow trench isolation structure 14 remaining on the substrate 10 are defined as an oxide layer region 152, and the oxide layer region 152 wraps around the gate structure 16, and a region between the gate structure 16 and the isolation region. The oxide region 152 forms a second opening 181 on the second doped region 172 to locate the drain.
Referring to fig. 1, 14-16, after the etching of the gate oxide layer 15 is completed, a remaining oxide layer region 152 spans over the shallow trench isolation structure 14 and the active region and covers a portion of the active region in the channel width direction of the gate structure 16, and a first preset distance d1 is provided between the gate oxide layer 15 and the gate structure 16 at the interface between the active region and the shallow trench isolation structure 14, where the first preset distance d1 is, for example, 0.8 μm to 1.1 μm. The remaining oxide layer region 152 covers a portion of the shallow trench isolation structure 14 in the direction of the channel length of the gate structure 16 and extends in the direction of the gate structure 16 until a portion of the substrate 10 on a side of the gate structure 16 remote from the shallow trench isolation structure 14. The gate oxide layer 15 and the gate structure 16 have a second predetermined distance d2 therebetween, and the second predetermined distance d2 is, for example, 0.1 μm to 0.3 μm. I.e., the gate structure 16 is on the active region on the side remote from the shallow trench isolation structure 14, the gate oxide 15 on the active region is at a different distance from the gate structure 16. By increasing the distance from the gate oxide layer 15 at the interface of the shallow trench isolation structure 14 and the active region to the gate structure 16, the gate oxide layer under the gate structure 16 can be prevented from being drilled and etched in the direction of the channel width of the gate structure 16, the semiconductor leakage phenomenon is reduced, and the yield of the semiconductor device is improved. Meanwhile, in the manufacturing process, only the exposure range of the second photoresist layer is required to be modified, no additional process steps are required to be added, the size of the semiconductor device is not changed, the manufacturing cost is not increased, and meanwhile, the performance of the semiconductor device is improved.
Referring to fig. 17, in an embodiment of the present invention, after removing a portion of the gate oxide layer, a sidewall dielectric layer (not shown) is formed on the substrate 10 and the gate structure 16, and the material of the sidewall dielectric layer is, for example, silicon oxide, silicon nitride or a stack of silicon oxide and silicon nitride. After forming the sidewall dielectric layer, for example, the gate structure 16, the shallow trench isolation structure 14 and a portion of the sidewall dielectric layer on the gate oxide layer 15 may be removed by using an etching process such as dry etching or wet etching, so as to retain the sidewall dielectric layers on both sides of the gate structure 16. The remained side wall dielectric layer is defined as a side wall structure 18, the height of the side wall structure 18 is consistent with that of the grid electrode structure 16, the width of the side wall structure 18 is gradually increased from the top to the bottom of the grid electrode structure 16, and the insulating side wall structure 18 is arranged to prevent the prepared semiconductor device from generating electric leakage. In this embodiment, the shape of the sidewall structure 18 is, for example, arc, and in other embodiments, the shape of the sidewall structure 18 may be triangular or L-shaped.
Referring to fig. 18 to 19, in an embodiment of the present invention, fig. 18 is a cross-sectional view of fig. 1 in A-A direction, and fig. 19 is a cross-sectional view of fig. 1 in B-B direction. After forming the sidewall structures 18, a Self-Aligned Block (SAB) 19 is formed on the first doped region 171, the second doped region 172 and the gate structure 16, i.e., the Self-Aligned Block 19 covers the first doped region 171, a portion of the second doped region 172 and the top of the gate structure 16. The salicide block layer 19 is, for example, a metal silicide such as nickel silicide (NiSi) or cobalt silicide (CoSi) to reduce the contact resistance between the subsequent metal lines and the semiconductor device. Specifically, a metal material, such as titanium, cobalt, or nickel, is deposited on the substrate 10 and the gate structure 16, and the metal material reacts with silicon in the substrate 10 and the gate structure 16 by a rapid annealing process to form a metal silicide, and finally, unreacted metal material is removed.
Referring to fig. 1, 20 to 21, in an embodiment of the present invention, fig. 20 is a cross-sectional view of fig. 1 in A-A direction, and fig. 21 is a cross-sectional view of fig. 1 in B-B direction. After the salicide block layer 19 is formed, an interlayer dielectric layer 20 is formed on the salicide block layer 19, the interlayer dielectric layer 20 covering the surface of the substrate 10. In this embodiment, the interlayer dielectric layer 20 may be formed on the substrate 10 by, for example, high-density plasma chemical vapor deposition, the thickness of the interlayer dielectric layer 20 may be 500nm to 800nm, and the material of the interlayer dielectric layer 20 may be, for example, an insulating material such as silicon dioxide. A plurality of openings are formed in the interlayer dielectric layer 20 in communication with the salicide block layer 19 and a conductive material is deposited in the openings, such as by a deposition process, for example, a metal material, such as a titanium/titanium nitride barrier layer and tungsten metal, is deposited in the openings to form the electrode. Wherein the conductive plug connected to the first doped region 171 is defined as the source 21 of the semiconductor device, the conductive plug connected to the gate structure is defined as the gate 22 of the semiconductor device, and the conductive plug connected to the second doped region 172 is defined as the drain 23 of the semiconductor device. By arranging the electrodes in the same plane, the connection of the semiconductor device with the subsequent circuit is facilitated.
In summary, the present invention provides a semiconductor device and a method for manufacturing the same, in which the layout of the semiconductor device is set during the process of forming the semiconductor device, the distance from the gate oxide layer at the interface of the isolation structure and the active region to the gate structure is increased, the occurrence of the defect phenomenon of the gate oxide layer is reduced, and the yield of the semiconductor device is improved. Meanwhile, in the manufacturing process, no extra process steps are needed, the size of the semiconductor device is not changed, and the performance of the semiconductor device is improved while the manufacturing cost is not increased.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (7)

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises an active region and an isolation region;
forming a gate oxide layer on the substrate;
forming a gate structure on the gate oxide layer, wherein a first preset distance is reserved between the gate structure and the gate oxide layer at the interface of the active region and the isolation region at one side of the gate structure away from the isolation region;
forming a source doping region in the active region at one side of the grid structure; and
forming a drain doping region in the active region at the other side of the grid structure;
and after the source doping region and the drain doping region are formed, etching the gate oxide layer and the shallow trench isolation structure of the isolation region to form an oxide layer region, wherein the oxide layer region wraps the gate structure and the region between the gate structure and the isolation region.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the first predetermined distance is 0.8 μm to 1.1 μm.
3. The method of manufacturing a semiconductor device according to claim 1, wherein a gate oxide layer between the active region and the isolation region has a second predetermined distance from the gate structure on a side of the gate structure away from the isolation region.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the second predetermined distance is 0.1 μm to 0.3 μm.
5. The method of manufacturing a semiconductor device according to claim 1, wherein the isolation region has a shape of a "U" or a "concave" arrangement.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the gate structure extends to both side edges of the isolation region in a channel width direction, and both ends of the gate structure cover a part of the isolation region.
7. The method of manufacturing a semiconductor device according to claim 1, further comprising a sidewall structure disposed on both sides of the gate structure, and disposed on the gate oxide layer.
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