CN114388363B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN114388363B CN114388363B CN202210292285.5A CN202210292285A CN114388363B CN 114388363 B CN114388363 B CN 114388363B CN 202210292285 A CN202210292285 A CN 202210292285A CN 114388363 B CN114388363 B CN 114388363B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
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- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 64
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- 238000000034 method Methods 0.000 claims abstract description 43
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- 238000005468 ion implantation Methods 0.000 claims abstract description 20
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 20
- 238000002955 isolation Methods 0.000 claims description 37
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- 238000000059 patterning Methods 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 2
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- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 25
- 229920005591 polysilicon Polymers 0.000 description 25
- 238000010586 diagram Methods 0.000 description 10
- 238000002513 implantation Methods 0.000 description 9
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- 238000002360 preparation method Methods 0.000 description 6
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
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- 238000009826 distribution Methods 0.000 description 2
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- 229910017052 cobalt Inorganic materials 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
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- 238000000206 photolithography Methods 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The manufacturing method of the semiconductor device comprises the following steps: providing a substrate; forming a drift region and a well region on the substrate; carrying out ion implantation in the drift region to form a top buried layer region; performing oxygen ion implantation on the surface of the substrate above the top buried layer region to form an oxygen-enriched region; and forming an oxide layer on the surface of the substrate through oxidation reaction, wherein the thickness of the oxide layer in the oxygen-rich region is larger than that of the oxide layer outside the oxygen-rich region. The semiconductor device and the manufacturing method thereof provided by the invention can simplify the process and improve the performance of the semiconductor device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor device and a manufacturing method thereof.
Background
Lateral Double-diffused Metal-Oxide Semiconductor (LDMOS) devices are often integrated with CMOS or Bipolar Junction Transistor (BJT) devices on a chip due to their advantages of low power consumption, high voltage resistance, and compatibility with CMOS processes, i.e., integrated Bipolar-CMOS-DMOS device processes (BCD processes), and are widely used in integrated power management circuits and other products.
Therefore, how to simplify the preparation process of the LDMOS and obtain a high-quality LDMOS device becomes an urgent problem to be solved.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, and the semiconductor device and the manufacturing method thereof can simplify the preparation process of the semiconductor device, reduce the production cost and obtain the high-quality semiconductor device.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a method for manufacturing a semiconductor device, which at least comprises the following steps:
providing a substrate;
forming a drift region and a well region on the substrate;
performing ion implantation in the drift region to form a top buried layer region;
performing oxygen ion implantation on the surface of the substrate above the top buried layer region to form an oxygen-enriched region;
and forming an oxide layer on the surface of the substrate through oxidation reaction, wherein the thickness of the oxide layer in the oxygen-enriched area is larger than that of the oxide layer outside the oxygen-enriched area.
In an embodiment of the present invention, the forming of the oxygen-rich region includes:
forming a light resistance layer on the drift region and the well region;
patterning the photoresist layer, and forming an opening on the drift region, wherein part of the drift region is exposed by the opening;
taking the patterned photoresist layer as a mask, and performing ion implantation on the opening to form the top buried layer region;
and implanting oxygen ions into the opening to form the oxygen-enriched area.
In an embodiment of the present invention, the energy of the ion implantation for forming the top buried layer region is 20-70 keV.
In an embodiment of the present invention, the oxygen ion implantation energy for forming the oxygen-rich region is 1 to 50 keV.
In an embodiment of the present invention, the forming of the oxide layer includes:
placing the substrate into a reaction chamber;
heating the reaction chamber to 900-1100 ℃;
and introducing nitrogen and oxygen, forming an oxide layer with the thickness of 5-60 nm on the surface of the substrate outside the oxygen-enriched area, and forming an oxide layer with the thickness of 100-500 nm in the oxygen-enriched area.
In an embodiment of the invention, the volume introduction ratio of the nitrogen to the oxygen is 1: 3-1: 10.
In an embodiment of the present invention, when the oxide layer is formed, impurity ions in the top buried layer region diffuse to three-dimensionally wrap the oxide layer in the oxygen-rich region.
In an embodiment of the present invention, the method for manufacturing the semiconductor device further includes:
etching the oxide layer outside the oxygen-enriched area to form a grid oxide layer and an isolation oxide layer, wherein the thickness of the grid oxide layer is smaller than that of the isolation oxide layer;
and forming a grid electrode on the grid electrode oxidation layer and part of the isolation oxidation layer.
In an embodiment of the present invention, the method for manufacturing the semiconductor device further includes:
forming a drain in the drift region;
a source is formed in the well region.
Another object of the present invention is to provide a semiconductor device, including:
a substrate;
the drift region is positioned in the substrate, and a top buried layer region is arranged in the drift region;
the well region is positioned in the substrate and is arranged adjacent to the drift region;
the grid oxide layer is positioned on the drift region and the well region;
and the isolation oxide layer is positioned in the drift region, the thickness of the isolation oxide layer is greater than that of the gate oxide layer, and the top buried layer region is wrapped by the isolation oxide layer in a three-dimensional mode.
According to the semiconductor device and the manufacturing method thereof, the oxygen-rich region and the top buried layer region can be self-aligned, and the performance of the semiconductor device is improved. In the production process, the manufacturing process can be simplified, the production efficiency can be improved, the production capacity can be increased, and the production cost can be reduced. In summary, the present invention provides a semiconductor device and a method for manufacturing the same, which can reduce the production cost and obtain a high quality semiconductor device.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram illustrating the distribution of drift and well regions in an embodiment.
FIG. 2 is a schematic diagram of an embodiment of forming a patterned photoresist layer on the drift region and the well region.
Fig. 3 is a schematic diagram of an ion implantation process performed in the top buried layer region and the oxygen-rich region in an embodiment.
FIG. 4 is a schematic structural diagram of a top buried layer region and an oxygen-rich region in an embodiment.
FIG. 5 is a diagram illustrating an oxide layer structure according to an embodiment.
FIG. 6 is a diagram illustrating an embodiment of a polysilicon layer.
FIG. 7 is a schematic diagram illustrating an exemplary distribution of doped regions.
FIG. 8 is a schematic diagram of a gate structure according to an embodiment.
Fig. 9 is a schematic view of a sidewall structure in an embodiment.
FIG. 10 is a diagram illustrating an embodiment of a salicide block.
Fig. 11 is a schematic diagram of a semiconductor device in an embodiment.
Description of reference numerals:
10 a substrate; 101 an epitaxial layer; 102 a deep well region; 110 a drift region; a 120 well region; 130 patterning the photoresist layer; 131 is opened; 140 a top buried layer region; 150 oxygen-enriched zone; 160 an oxide layer; 161 a gate oxide layer; 162 an isolation oxide layer; 170 a polysilicon layer; 180 a first doped region; 190 a second doped region; 200 a third doped region; 210 a gate structure; 220, a side wall structure; 230 self-aligned silicide blocking layers; 240 an insulating layer; 21 a first conductive plug; 22 a second electrically conductive plug; 23 a third conductive plug; 24 a fourth conductive plug.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The semiconductor device and the manufacturing method thereof provided by the invention optimize the semiconductor manufacturing process, can simplify the manufacturing process, have excellent performance, and can be widely applied to HF high-frequency power amplifiers, VHF power amplifiers, UHF power amplifiers, broadcast transmitters, microwave radars, navigation systems and the like.
Referring to fig. 1, in an embodiment of the invention, an LDMOS (laterally Double-diffused Metal-oxide Semiconductor) is prepared, but the method for manufacturing a Semiconductor device provided in the present application can be used to prepare structural layers of the same material with different thicknesses.
Referring to fig. 1, in an embodiment of the invention, a substrate 10 is provided, and the substrate 10 may be any material suitable for formation, such as a base plate of a silicon wafer, and the substrate may be a P-doped semiconductor substrate or an N-doped semiconductor substrate, in which embodiment, the substrate 10 is, for example, a P-doped semiconductor substrate.
Referring to fig. 1, in an embodiment of the present invention, near the bottom of the substrate 10, a P-type epitaxial layer 101 is disposed in the substrate 10, and the epitaxial layer 101 may be a homoepitaxial layer with the substrate 10, such as a silicon layer, or a heteroepitaxial layer, such as a silicon germanium layer or silicon carbide layer. The deep well region 102 is formed by ion implantation of impurity ions having a higher concentration than the epitaxial layer 101, and the ions implanted into the deep well region 102 may be, for example, P-type or N-type, and in the present embodiment, P-type impurities such as boron (B) or gallium (Ga) are implanted to form a P-type deep well region. The thickness of the deep well region 102 is greater than that of the epitaxial layer 101, the epitaxial layer 101 can improve the breakdown voltage and reduce the series resistance of the semiconductor device, and the deep well region 102 can reduce the Latch-up effect (Latch-up) of the semiconductor device and improve the yield of the semiconductor device.
Referring to fig. 1, in an embodiment of the invention, a drift region 110 is formed on an epitaxial layer 101 by ion implantation, a well region 120 is formed on a deep well region 102 by ion implantation, and the implanted ion types of the drift region 110 and the deep well region 102 are different. In the present embodiment, the drift region 110 is implanted with N-type impurities such As phosphorus (P) or arsenic (As) to form an N-type drift region, the well region 120 is implanted with P-type impurities such As boron (B) or gallium (Ga) to form a P-type well region, and the depth of the drift region 110 is greater than the depth of the well region 120. In other embodiments, the drift region 110 may be configured as a P-type drift region, and the well region 120 may be configured as an N-type well region, which may be selected according to the type of semiconductor device to be fabricated. By setting the depth of the drift region 110 to be greater than the depth of the well region 120, the withstand voltage value of the semiconductor device can be improved.
Referring to fig. 2, in an embodiment of the invention, after the drift region 110 and the well region 120 are formed, a patterned photoresist layer 130 is formed on the surface of the substrate 10. An opening 131 is disposed on the patterned photoresist layer 130, the opening 131 is located on the drift region 110, and the opening 131 exposes the surface of the drift region 110, that is, the photoresist covers the well region 120 and a portion of the drift region 110. The opening 131 is used to position the isolation oxide layer to be later prepared, and the size of the opening 131 is the same as that of the isolation oxide layer.
Referring to fig. 3 to 4, in an embodiment of the invention, after the formation of the patterned photoresist layer 130, ion implantation is performed step by using the patterned photoresist layer 130 as a mask, so as to form a top buried layer region 140 and an oxygen-rich region 150 in the drift region 110 corresponding to the opening 131, and the oxygen-rich region 150 is located on the top of the top buried layer region 140. Specifically, a P-type impurity such as boron (B) is implanted into the opening 131 at a high implantation energy to form a TOP buried layer region 140, i.e., a P-type TOP buried layer region (P-TOP), wherein the implantation energy of the P-type impurity is, for example, 20 to 70keV, and the implantation dose is, for example, 1x1012cm-2~1x1015cm-2. By providing the top buried layer region 140, the surface electric field of the LDMOS transistor can be reduced, and the voltage withstanding performance of the LDMOS transistor can be improved. Then, oxygen-containing impurities such as oxygen ions (O) are implanted at a low implantation energy to form the oxygen-rich region 150, and the oxygen-rich region 150 is formed on the top buried layer region 140 because the implantation energy is lower than that of the P-type impurities. Wherein the implantation dose of oxygen ions is, for example, 1 × 1012cm-2~1x1016cm-2The implantation energy is, for example, 1 to 50 keV. After the oxygen ion implantation is completed, the patterned photoresist layer 130 is removed. In the present embodiment, the depth of the oxygen-rich region 150 is, for example, 50 to 500nm, the thickness of the top buried layer region 140 is, for example, 800 to 4000nm, and the widths of the top buried layer region 140 and the oxygen-rich region 150 are, for example, 6 to 50 μm. In other embodiments, the depth and width of the top buried layer region 140 and the oxygen-rich region 150 can be flexibly selected according to the fabrication requirements. P-type ions and oxygen ions are injected in sequence through a photomask manufacturing process, the self-alignment function of the top buried layer region 140 and the oxygen-enriched region 150 is realized, and the phenomenon that the conduction resistance (Ron) is too large and the shadow occurs due to the misalignment of the top buried layer region 140 and the isolation oxide layer in the process of preparing the isolation oxide layer through the Local Oxidation of Silicon (LOCOS) after the top buried layer region 140 is formed is avoidedPerformance of semiconductor devices is affected. The invention realizes the self-alignment of the top buried layer region 140 and the oxygen-enriched region 150, can reduce the on-resistance of the semiconductor device and improve the performance of the semiconductor device. Compared with two photomask preparation processes of firstly forming the top buried layer region and then forming the isolation oxide layer, the preparation method provided by the invention simplifies the preparation process and reduces the preparation cost only by one photomask process.
Referring to fig. 5, in an embodiment of the invention, an oxide layer 160 and an isolation oxide layer 162 are formed on the surfaces of the drift region 110 and the well region 120, and the oxide layer 160 and the isolation oxide layer 162 are formed by, for example, a dry oxidation method, a water vapor oxidation method, or a wet oxidation method. In the present embodiment, the oxide layer 160 and the isolation oxide layer 162 are formed by, for example, a dry oxidation method, and specifically, the substrate 10 is placed in a reaction chamber, for example, a furnace tube, which is first evacuated, and then, for example, nitrogen (N) gas is introduced2) Maintaining the pressure in the furnace tube at normal pressure, heating the furnace tube to 900-1100 deg.C, and introducing nitrogen and oxygen (O)2) The reaction is carried out at this temperature for 20 to 300min, and after the reaction is completed, the substrate 10 is cooled in a stable gas atmosphere, for example, in an atmosphere of nitrogen gas or argon gas (Ar). Wherein, in the heating reaction process, the mixed gas of nitrogen and oxygen is continuously introduced to ensure the normal pressure state in the furnace tube, and the volume introduction ratio of the nitrogen to the oxygen is, for example, 1: 3-1: 10. The oxide layer is formed by a dry oxygen oxidation method, the formed gate oxide layer has good film forming quality, and the performance of the semiconductor device can be improved.
Referring to fig. 4 to 5, in an embodiment of the invention, the oxide layer 160 is formed by oxidizing silicon on the surface of the well region 120 and a portion of the drift region 110, and the isolation oxide layer 162 is formed by oxidizing the oxygen-rich region 150. In the present embodiment, since the oxygen-rich region 150 contains oxygen ions, the oxygen-rich region 150 has a higher oxidation growth rate than the rest of the single crystal silicon region, and the volume expansion rate is higher, so that the thickness of the isolation oxide layer 162 is greater than that of the oxide layer 160. In the present embodiment, the thickness of the oxide layer 160 is, for example, 5 to 60nm, the thickness of the isolation oxide layer 162 above the drift region 110 is, for example, 100 to 500nm, and the thickness of the isolation oxide layer 162 in the drift region 110 is, for example, 80 to 600 nm. The thicknesses of the oxide layer 160 and the isolation oxide layer 162 may be adjusted according to the implantation concentration of oxygen ions in the oxygen-rich region 150, the implantation energy, the oxidation temperature, the oxidation time, and the oxygen content of the gas. In the present invention, the thicknesses of the oxide layer 160 and the isolation oxide layer 162 are generally selected according to the requirements of the semiconductor device, wherein the oxide layer 160 is used for adjusting the turn-on voltage, and the isolation oxide layer 162 mainly plays a role of isolation. In the thermal oxidation process, the doped ions in the top buried layer region 140 are diffused, the edge of the top buried layer region is diffused into an arc-shaped structure, the isolation oxide layer 162 is wrapped in three dimensions, the isolation effect is improved, the contact area is increased when the semiconductor device works, and the voltage endurance value of the semiconductor device is improved. In the invention, by arranging the oxygen-enriched area, oxide layers with different thicknesses can be formed in different areas by one-time high-temperature oxidation in the oxidation process, and compared with the step-by-step formation of the oxide areas with different thicknesses, the high-temperature oxidation process is reduced, the manufacturing cost can be reduced, and the production capacity can be improved. By the method provided by the invention, the thickness of the oxide layer is easy to adjust and control, and the manufacturing process is simplified.
Referring to fig. 6, in an embodiment of the invention, a polysilicon layer 170 is formed on the oxide layer 160 and the isolation oxide layer 162, the polysilicon layer 170 may be P-type or N-type, and the doping type of the polysilicon layer 170 is different from that of the substrate 10. In the present embodiment, the polysilicon layer 170 is, for example, N-type, and the thickness of the polysilicon layer 170 is, for example, 200 to 400nm, in other embodiments, the thickness of the polysilicon layer 170 may be set according to actual requirements. Specifically, a polysilicon layer 170 is formed on the oxide layer 160 and the isolation oxide layer 162, a photoresist is formed on the polysilicon layer 170, and then the photoresist is exposed and developed to form a patterned photoresist layer (not shown). The polysilicon layer 170 is then etched by, for example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process. In this embodiment, for example, the polysilicon layer 170 is sequentially anisotropically etched by using a dry etching process, and the oxide layer 160 and the isolation oxide layer 162 may serve as an etch stop layer for the polysilicon layer 170. The etch is stopped when the polysilicon layer 170 is etched to the oxide layer 160 and the isolation oxide layer 162. I.e., the remaining polysilicon layer 170 is located on a portion of the oxide layer 160 and a portion of the isolation oxide layer 162, and the polysilicon layer 170 spans over the drift region 110 and the well region 120.
Referring to fig. 7, in an embodiment of the invention, ion implantation is performed using the oxide layer 160 as a mask to form a plurality of doped regions on the drift region 110 and the well region 120. Specifically, the first doped region 180 is disposed at the top region of the drift region 110, and the first doped region 180 serves as a drain region of the LDMOS transistor. A second doped region 190 and a third doped region 200 are formed in the top region of the well region 120, wherein the second doped region 190 serves as the source region of the LDMOS transistor, and the third doped region 200 serves as the base region of the LDMOS transistor. The first doped region 180 and the second doped region 190 are doped with a first type, the third doped region 200 is doped with a second type, and the first type doping and the second type doping may be P-type or N-type, but it is required to ensure that the doping types of the first type doping and the second type doping are different. In this embodiment, the first type doping is, for example, N-type doping, and the second type doping is, for example, P-type doping, in other embodiments, the first type doping may also be P-type doping, and the second type doping may also be N-type doping, which is specifically selected according to the type of the LDMOS transistor to be manufactured.
Referring to fig. 8, in an embodiment of the invention, after the doped region is formed, a patterned photoresist layer (not shown) is formed on the polysilicon layer 170 and the isolation oxide layer 162, and the oxide layer 160 outside the polysilicon layer 170 is removed by, for example, a dry etching process, a wet etching process, or a combination of the dry etching process and the wet etching process, using the patterned photoresist layer as a mask. In this embodiment, for example, a dry etching process is selected to remove the oxide layer 160, and after the etching is completed, the patterned photoresist layer is removed. The remaining oxide layer 160 is defined as the gate oxide layer 161 and the polysilicon layer 170 are defined as the gate structure 210 to serve as the gate of the LDMOS transistor. By forming the doped region first and then forming the gate structure, the loss of the substrate caused by ion implantation is prevented when the doped region is formed, and the performance of the semiconductor device is improved.
Referring to fig. 9, in an embodiment of the invention, after the gate structure 210 is formed, sidewall structures 220 are formed on two sides of the gate structure 210. Specifically, a sidewall dielectric layer (not shown) is formed on the polysilicon layer 170, the well region 120, the drift region 110 and the isolation oxide layer 162, and the material of the sidewall dielectric layer is, for example, silicon oxide, silicon nitride or a stacked layer of silicon oxide and silicon nitride. After the sidewall dielectric layer is formed, for example, the sidewall dielectric layer on the polysilicon layer 170, the well region 120, the drift region 110 and a portion of the isolation oxide layer 162 may be removed by using an etching process such as photolithography, and the sidewall dielectric layers on both sides of the gate structure 210 are retained, i.e., the sidewall structure 220 is formed. The height of the side wall structure 220 is the same as that of the gate structure 210, the width of the side wall structure 220 is gradually increased from the top to the bottom of the gate structure 210, and the insulating side wall structure 220 is arranged to prevent the prepared LDMOS from generating a leakage phenomenon. In this embodiment, the shape of the sidewall structure 220 is, for example, an arc shape, and in other embodiments, the shape of the sidewall structure 220 may also be other shapes, which may be selected according to the manufacturing requirements.
Referring to fig. 10, in an embodiment of the invention, after the formation of the sidewall spacer structure 220, a Self-Aligned silicide Block 230 (SAB) is formed on the doped region and the polysilicon layer 170. I.e., the salicide block layer 230 covers the first doped region 180, the second doped region 190, the third doped region 200, and the top of the polysilicon layer 170. Specifically, a metal layer (not shown) is formed on the top of the first doped region 180, the second doped region 190, the third doped region 200 and the polysilicon layer 170, and the metal layer is, for example, a titanium layer (Ti), a cobalt layer (Co) or a nickel layer (Ni), and then a first annealing is performed on the substrate 10 at, for example, 350 to 550 ℃, so that metal atoms react with silicon atoms in the first doped region 180, the second doped region 190, the third doped region 200 and the polysilicon layer 170 to form an intermediate silicide layer, and then a second annealing is performed on the intermediate silicide layer, wherein the temperature of the second annealing is higher than that of the first annealing, and the temperature of the second annealing is, for example, 600 to 800 ℃. The intermediate silicide layer is annealed and converted to a silicide layer, i.e., a salicide block layer 230. The salicide block layer 230 has good thermal stability, which can reduce the resistance of the device and ensure good contact with the metal electrode prepared later.
Referring to fig. 11, in an embodiment of the invention, after the salicide block layer 230 is formed, an insulating layer 240 is formed on the salicide block layer 230, the insulating layer 240 covers the entire surface of the substrate, and the insulating layer 240 is configured as, for example, a silicon oxide layer to protect the LDMOS transistor. A plurality of vias are formed in the insulating layer 240 until the salicide block layer 230 is exposed, and metal lines, such as tungsten, copper, or silver, are formed in the vias to form conductive plugs. The conductive plugs include a first conductive plug 21, a second conductive plug 22, a third conductive plug 23 and a fourth conductive plug 24, wherein the first conductive plug 21 is disposed on the first doped region 180 and connected to the salicide block layer 230 on the first doped region 180, that is, the first conductive plug 21 is connected to the drain region to serve as the drain of the LDMOS transistor. The second conductive plug 22 is disposed on the gate structure 210 and connected to the salicide block 230 on the gate structure 210 to serve as the gate of the LDMOS transistor. The third conductive plug 23 is located on the second doped region 190 and connected to the salicide block layer 230 on the second doped region 190 to serve as the source of the LDMOS transistor. The fourth conductive plug 24 is located in the third doped region 200 and connected to the salicide block layer 230 on the third doped region 200 to serve as the base of the LDMOS transistor for grounding.
In summary, the present invention provides a semiconductor device and a method for fabricating the same, in which an oxygen-rich region and a top buried layer region are formed in a self-aligned manner, so as to improve the performance of the semiconductor device and simplify the fabrication process, and a gate oxide layer and an isolation oxide layer are formed by a thermal oxidation process, i.e., oxide layers with different thicknesses are formed in different regions at one step, so as to improve the production efficiency and reduce the production cost.
The embodiments of the invention disclosed above are intended to be merely illustrative. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (8)
1. A method for manufacturing a semiconductor device, comprising:
providing a substrate;
forming a drift region and a well region on the substrate;
performing ion implantation in the drift region to form a top buried layer region;
performing oxygen ion implantation on the surface of the substrate above the top buried layer region to form an oxygen-enriched region;
forming an oxide layer on the surface of the substrate through oxidation reaction, wherein the thickness of the oxide layer in the oxygen-rich region is larger than that of the oxide layer outside the oxygen-rich region;
wherein the forming of the oxygen-rich region comprises:
forming a light resistance layer on the drift region and the well region;
patterning the photoresist layer, and forming an opening on the drift region, wherein part of the drift region is exposed by the opening;
taking the patterned photoresist layer as a mask, and performing ion implantation on the opening to form the top buried layer region;
and implanting oxygen ions into the opening to form the oxygen-enriched area.
2. The method according to claim 1, wherein an ion implantation energy for forming the top buried layer region is 20 to 70 keV.
3. The method of claim 1, wherein an energy of oxygen ion implantation for forming the oxygen-rich region is 1 to 50 keV.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the oxide layer comprises:
placing the substrate into a reaction chamber;
heating the reaction chamber to 900-1100 ℃;
and introducing nitrogen and oxygen, forming an oxide layer with the thickness of 5-60 nm on the surface of the substrate outside the oxygen-enriched area, and forming an oxide layer with the thickness of 100-500 nm in the oxygen-enriched area.
5. The method for manufacturing a semiconductor device according to claim 4, wherein a volume ratio of the nitrogen gas to the oxygen gas is 1:3 to 1: 10.
6. The method according to claim 4, wherein impurity ions in the top buried layer region are diffused to three-dimensionally wrap the oxide layer in the oxygen-rich region when the oxide layer is formed.
7. The method for manufacturing a semiconductor device according to claim 1, further comprising:
etching the oxide layer outside the oxygen-enriched area to form a grid oxide layer and an isolation oxide layer, wherein the thickness of the grid oxide layer is smaller than that of the isolation oxide layer;
and forming a grid electrode on the grid electrode oxidation layer and part of the isolation oxidation layer.
8. The method for manufacturing a semiconductor device according to claim 7, further comprising:
forming a drain in the drift region;
a source is formed in the well region.
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| US6177321B1 (en) * | 1999-05-10 | 2001-01-23 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device and fabrication method thereof |
| KR20040048002A (en) * | 2002-12-02 | 2004-06-07 | 삼성전자주식회사 | Method of manufacturing LDMOS transistor |
| CN101320752A (en) * | 2007-06-06 | 2008-12-10 | 旺宏电子股份有限公司 | Lateral diffusion metal-oxide-semiconductor element with low opening resistor and manufacturing method thereof |
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| US6177321B1 (en) * | 1999-05-10 | 2001-01-23 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device and fabrication method thereof |
| KR20040048002A (en) * | 2002-12-02 | 2004-06-07 | 삼성전자주식회사 | Method of manufacturing LDMOS transistor |
| CN101320752A (en) * | 2007-06-06 | 2008-12-10 | 旺宏电子股份有限公司 | Lateral diffusion metal-oxide-semiconductor element with low opening resistor and manufacturing method thereof |
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