CN117059672B - Semiconductor device integrated with SBD and manufacturing method thereof - Google Patents
Semiconductor device integrated with SBD and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
Abstract
The application provides a semiconductor device integrating an SBD and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor device of the integrated SBD includes: a first type epitaxial wafer; the second type well region is positioned on the surface layer of the plane region and is adjacent to the convex region; the first doped region and the second doped region are positioned on the surface layer of the second type well region; the inclined doped region is partially positioned on the surface layer of the second doped region, and the other part of the inclined doped region extends into the non-well region below the raised region; the width of the inclined doped region is smaller than that of the second doped region; the third doped region is positioned in the convex region and is close to one side of the second type well region; the grid structure is positioned on the surface of the second type well region; and the contact layer is positioned on the surfaces of the first doped region, the second doped region, the inclined doped region and the raised region, wherein the contact layer forms Schottky contact with the region of the raised region except the third doped region. The method has the advantages of improving the electrical performance and reliability of the device and reducing the cost.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device integrated with an SBD and a manufacturing method thereof.
Background
Under certain specific circuit topology applications, such as in a BUCK converter of DCDC, it is common for a SiC MOSFET to operate in the third quadrant, and the first proposal is to perform current flow in the third quadrant through a body diode in the SiC MOSFET, but the current body diode has the problem of poor electrical performance and reliability at normal temperature or high temperature.
Therefore, at present, a single anti-parallel SiC diode is required to bypass a bipolar body diode to achieve better dynamic performance and reliability, but the additional diode chip area is increased, the cost is increased, meanwhile, the number of passive elements and then cooling elements is increased, the module packaging cost is greatly increased, the circuit topology design becomes complex, and the power density of the system is reduced.
In summary, the body diode in the prior art has poor electrical performance and reliability, and the anti-parallel diode has the problems of high cost, large area and the like.
Disclosure of Invention
The invention aims to provide a semiconductor device integrating an SBD and a manufacturing method thereof, which solve the problems of poor electrical performance and reliability of a body diode and high cost and large area of an anti-parallel diode in the prior art.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
in one aspect, an embodiment of the present application provides an SBD-integrated semiconductor device, including:
a first type epitaxial wafer; the epitaxial wafer comprises a protruding area and a plane area, and the height of the protruding area is larger than that of the plane area;
the second type well region is positioned on the surface layer of the plane region and is adjacent to the raised region;
the first doped region and the second doped region are positioned on the surface layer of the second type well region, the first doped region is in contact with the second doped region, and the second doped region is adjacent to the raised region;
the inclined doped region is partially positioned on the surface layer of the second doped region, and the other part of the inclined doped region extends into the non-well region below the raised region; the width of the inclined doped region is smaller than that of the second doped region;
the third doped region is positioned in the convex region and is close to one side of the second type well region; the first doped region is a first type doped region, and the second doped region, the inclined doped region and the third doped region are all second type doped regions;
the grid structure is positioned on the surface of the second type well region;
the contact layer is positioned on the surfaces of the first doped region, the second doped region, the inclined doped region and the raised region, wherein the contact layer forms Schottky contact with the region of the raised region except the third doped region;
and the first metal layer is positioned on the surface of the contact layer, and the second metal layer is positioned on the back surface of the epitaxial wafer.
Optionally, the third doped region, the inclined doped region and the second doped region are all heavily doped, and doping concentrations of the third doped region, the inclined doped region, the second doped region and the second type well region are sequentially reduced.
Optionally, the size of the inclined doped region satisfies the formula:
L＞0，W＞0；
wherein L represents an edge width difference between the third doped region and the inclined doped region along a distance away from the first doped region; w represents the depth difference between the second doped region and the inclined doped region.
Optionally, the ion implantation angle of the inclined doped region is 30-45 degrees.
Optionally, the contact layer forms an ohmic contact with the third doped region, the second doped region, and the oblique doped region.
Optionally, the convex area is provided in a circular arc shape.
Optionally, the epitaxial wafer includes a first type substrate and a first type epitaxial layer located at one side of the first type substrate, the first type epitaxial layer is lightly doped, the epitaxial wafer further includes a fourth doped region located below the protruding region, the fourth doped region is the first type doped region and the fourth doped region is heavily doped.
Optionally, the gate structure includes:
the gate oxide layer is partially positioned on the surface of the second type well region;
the doped polysilicon layer is positioned on the surface of the gate oxide layer;
and the grid metal layer is connected with the doped polysilicon layer.
Optionally, the first type is N-type, and the second type is P-type.
On the other hand, the embodiment of the application also provides a manufacturing method of the semiconductor device of the integrated SBD, which is used for manufacturing the semiconductor device, and the manufacturing method of the semiconductor device of the integrated SBD comprises the following steps:
providing a first type epitaxial wafer;
performing ion implantation based on the set region of the first type epitaxial wafer to form a third doped region;
etching the epitaxial wafer, forming a protruding region and a plane region, wherein the height of the protruding region is larger than that of the plane region, and the third doped region is positioned in the protruding region;
manufacturing a second type well region based on the surface layer of the plane region, wherein the second type well region is adjacent to the protruding region;
manufacturing a first doped region and a second doped region based on the surface layer of the second type well region, wherein the first doped region is in contact with the second doped region, and the second doped region is adjacent to the raised region;
the manufacturing part is positioned in the inclined doped region on the surface layer of the second doped region, and the other part of the inclined doped region extends into the non-well region below the raised region; the width of the inclined doped region is smaller than that of the second doped region;
the first doped region is a first type doped region, and the second doped region, the inclined doped region and the third doped region are all second type doped regions;
manufacturing a grid structure based on the surface of the second type well region;
manufacturing a contact layer based on the first doped region, the second doped region, the inclined doped region and the surface of the raised region, wherein the contact layer forms Schottky contact with the region of the raised region except the third doped region;
and manufacturing a first metal layer based on the surface of the contact layer and manufacturing a second metal layer based on the back surface of the epitaxial wafer.
Compared with the prior art, the embodiment of the application has the following beneficial effects:
the application provides a semiconductor device of integrated SBD and a manufacturing method thereof, the semiconductor device of integrated SBD comprises: a first type epitaxial wafer; the epitaxial wafer comprises a convex area and a plane area, and the height of the convex area is larger than that of the plane area; the second type well region is positioned on the surface layer of the plane region and is adjacent to the convex region; the first doped region and the second doped region are positioned on the surface layer of the second type well region, the first doped region is contacted with the second doped region, and the second doped region is adjacent to the raised region; the inclined doped region is partially positioned on the surface layer of the second doped region, and the other part of the inclined doped region extends into the non-well region below the raised region; the width of the inclined doped region is smaller than that of the second doped region; the third doped region is positioned in the convex region and is close to one side of the second type well region; the first doped region is a first type doped region, and the second doped region, the inclined doped region and the third doped region are all second type doped regions; the grid structure is positioned on the surface of the second type well region; the contact layer is positioned on the surfaces of the first doped region, the second doped region, the inclined doped region and the raised region, wherein the contact layer forms Schottky contact with the region except the third doped region in the raised region; the first metal layer is positioned on the surface of the contact layer, and the second metal layer is positioned on the back surface of the epitaxial wafer. Because in the device provided by the application, the Schottky diode (SBD) is integrated in the convex area, when the semiconductor device works in the third quadrant, the current flow is realized through the integrated Schottky diode, the electrical performance and the reliability of the traditional PN junction body diode and the external anti-parallel diode are improved, and the device cost is reduced. Meanwhile, by introducing the inclined doped region and the third doped region, the electrical performance and reliability of the device are further improved.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting in scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is an electrical symbol diagram of an N-type normally-off MOS transistor in the prior art.
Fig. 2 is another electrical symbol diagram of an N-type normally-off MOS transistor in the prior art.
Fig. 3 is a schematic cross-sectional view of a semiconductor device integrated with an SBD according to an embodiment of the present application.
Fig. 4 is a schematic cross-sectional view of an epitaxial layer provided in an embodiment of the present application.
Fig. 5 is a simplified schematic diagram of a semiconductor device integrated with an SBD provided in an embodiment of the present application.
Fig. 6 is an equivalent circuit schematic diagram of a MOSFET provided in an embodiment of the present application.
Fig. 7 is a schematic cross-sectional view corresponding to S104 provided in an embodiment of the present application.
Fig. 8 is a schematic cross-sectional view corresponding to S106 provided in an embodiment of the present application.
Fig. 9 is a schematic cross-sectional view corresponding to S108 provided in an embodiment of the present application.
Fig. 10 is a schematic cross-sectional view illustrating a first doped region according to an embodiment of the present application.
Fig. 11 is a schematic cross-sectional view illustrating a second doped region according to an embodiment of the present application.
Fig. 12 is a schematic cross-sectional view corresponding to S112 provided in an embodiment of the present application.
Fig. 13 is a schematic cross-sectional view corresponding to a gate oxide layer formed on a surface according to an embodiment of the present application.
Fig. 14 is a schematic cross-sectional view of a polysilicon layer deposited according to an embodiment of the present application.
Fig. 15 is a schematic cross-sectional view of an interlayer dielectric layer deposited and etched according to an embodiment of the present application.
Fig. 16 is a schematic cross-sectional view of a portion corresponding to S116 according to an embodiment of the present application.
Fig. 17 is a schematic partial cross-sectional view corresponding to fig. 15 after the hole is opened according to an embodiment of the present application.
Icon:
101-a substrate; 102-an epitaxial layer; 103-a well region; 104-a first doped region; 105-a second doped region; 106-oblique doped regions; 107-a third doped region; 108-a gate structure; 1081-a gate oxide layer; 1082-a doped polysilicon layer; 1083-an interlayer dielectric layer; 109-a first contact layer; 110-a second contact layer; 111-a first metal layer; 112-a second metal layer.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
In the description of the present application, it should be noted that, the terms "upper," "lower," "inner," "outer," and the like indicate an orientation or a positional relationship based on the orientation or the positional relationship shown in the drawings, or an orientation or a positional relationship conventionally put in use of the product of the application, merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
As shown in fig. 1, an electrical symbol diagram of an N-type normally-off MOS transistor is shown, where G represents a gate, S represents a source, and D represents a drain, as described in the background art, under normal working conditions, when a voltage connected to the gate is greater than a threshold voltage, the MOS transistor is turned on, and at this time, current flows from the drain to the source; when the voltage of the grid connection is smaller than the threshold voltage, the MOS tube is turned off, and at the moment, current cannot flow from the drain electrode to the source electrode, and the working condition is that the MOS tube works in the first quadrant. However, under certain specific circuit topology applications, current is required to flow from the source to the drain, i.e., the MOS transistor is required to operate in the third quadrant, such as in a BUCK converter of DCDC. In this operating mode, the current flow in the third quadrant is typically achieved by the diode on the right in fig. 1.
In specific implementation, the diode is generally implemented by a body diode of a MOS transistor, but the body diode of the current SiC MOSFET has the following problems:
at normal temperature, the PN junction diode has higher starting voltage and larger on-state loss, and meanwhile, the defect of a substrate (basal plane dislocation) is easy to cause bipolar degradation to cause high switching loss, even cause leakage current to increase and breakdown to decrease; at high temperature, the bipolar PN junction reversely recovers the charge Q rr The high switching power loss and the like are caused.
Therefore, the body diode of SiC MOSFETs does not have the performance and reliability metrics required for the application end.
On the basis, in another implementation in the prior art, the bipolar body diode is bypassed by independently connecting the SiC diode in anti-parallel on the MOS tube, so that better dynamic performance and reliability can be realized, namely, a diode is independently connected outside the MOS tube, and the circuit structure shown in fig. 2 is formed. As in fig. 2, 1 denotes a body diode, and 2 denotes an externally separately connected schottky diode.
But this implementation has the following problems:
the area of the diode chip is additionally increased, the cost is increased, the number of passive elements and then cooling elements is increased, the module packaging cost is greatly increased, the circuit topology design becomes complex, and the power density of the system is reduced. Especially in the application fields of higher voltage and larger current, if the electric vehicle driving motor needs to accelerate faster by hundred kilometers, run excessively and the like, or the application fields of rail transit and power grid, the problems are more serious. Furthermore, even with external anti-parallel SiC diodes, the transient switch always has some energy to act on the BPD, with performance and reliability risks.
In summary, when the MOS transistor needs to work in the third quadrant in the prior art, the body diode has poor electrical performance and reliability, and the anti-parallel diode has the problems of high cost, large area and the like.
In view of this, an embodiment of the present application provides a semiconductor device integrated with an SBD, please refer to fig. 3, which includes:
a first type epitaxial wafer; the epitaxial wafer comprises a convex area and a plane area, and the height of the convex area is larger than that of the plane area; the second type well region 103 is positioned on the surface layer of the plane region, and the second type well region 103 is adjacent to the protruding region; the first doped region 104 and the second doped region 105 are positioned on the surface layer of the second type well region 103, the first doped region 104 is contacted with the second doped region 105, and the second doped region 105 is adjacent to the raised region; an inclined doped region 106 partially located on the surface layer of the second doped region 105, and another portion of the inclined doped region 106 extends into the non-well region 103 below the raised region; the width of the inclined doped region 106 is smaller than the width of the second doped region 105; a third doped region 107 located within the raised region and adjacent to one side of the second type well region 103; the first doped region 104 is a first type doped region, and the second doped region 105, the inclined doped region 106 and the third doped region 107 are all second type doped regions; a gate structure 108 located on the surface of the second type well region 103; the contact layer is positioned on the surfaces of the first doped region 104, the second doped region 105, the inclined doped region 106 and the raised region, wherein the contact layer forms Schottky contact with the region except the third doped region 107 in the raised region; a first metal layer 111 on the surface of the contact layer and a second metal layer 112 on the back of the epitaxial wafer.
The semiconductor device provided in the present application is a SiC MOSFET, and since the contact layer forms a schottky contact with a region of the raised region except for the third doped region 107 in the present application, a schottky diode (SBD) is integrated in the device, and when the device needs to operate at the third pixel, a path between the source and the drain is formed through the schottky diode.
By integrating the SBD in the device, the performance of the traditional PN junction body diode is improved, on one hand, the starting voltage of the diode device is reduced at normal temperature, on-state loss is reduced, the starting voltage of the third quadrant is earlier, the surge processing capability of the MOSFET is improved, meanwhile, the SBD is a multi-sub device, the problem of minority carrier lifetime is not required to be considered, and the reverse recovery charge Q is reduced at high temperature rr Shortens the reverse recovery time t rr Switching power loss is reduced; on the other hand, the bipolar degradation problem is avoided, the power loss is reduced, the leakage current of the device is reduced, and the breakdown voltage of the device is improved.
Of course, by integrating the SBD in the device, the performance of the external anti-parallel diode is improved, the additional chip cost and the cost brought by the passive element and the cooling element are reduced on the basis of realizing better dynamic performance and reliability, the circuit topology structure and the packaging structure are simplified, the switching loss is reduced, and the power density and the efficiency of the system are improved.
In addition, by introducing the third doped region 107 and the inclined doped region 106, on one hand, the SBD current channel structure can be flexibly adjusted to adjust the proper forward current specification, and on the other hand, the masking depth can be flexibly adjusted, the electric field on the Schottky surface of the SBD can be better shielded, the leakage current can be reduced, and the breakdown voltage can be improved; the structure of the epitaxial layer 102 can be changed due to the inclined doped region 106, a new double-triangle electric field distribution is formed in the integrated SBD according to the principle of charge coupling modulation, the peak electric field intensity is greatly reduced, and the breakdown voltage of the device can be further improved.
In one implementation, the first type is N-type, the second type is P-type, and different doping types can be realized by implanting different doping elements.
Wherein the gate structure 108 comprises: a gate oxide layer 1081 partially located on the surface of the second type well region 103; the doped polysilicon layer 1082 is positioned on the surface of the gate oxide layer 1081; and a gate metal layer connected to the doped polysilicon layer 1082. The gate structure 108 is a conventional structure and will not be described in detail herein.
The epitaxial wafer includes a first type substrate 101 and a first type epitaxial layer 102 located on one side of the first type substrate 101, the first type epitaxial layer 102 is lightly doped, and the epitaxial wafer further includes a fourth doped region located below the protruding region, where the doping concentration of the fourth doped region can be adjusted according to actual requirements, for example, the fourth doped region is the first type doped region and the fourth doped region is heavily doped.
That is, in the present application, the n+ type substrate 101 is used as the substrate 101, the N-type epitaxial layer 102 is used as the epitaxial layer 102, and specific materials of the substrate 101 and the epitaxial layer 102 are not limited in the present application, and SiC materials may be used for the substrate 101 and the epitaxial layer 102, for example.
Referring to fig. 4, a represents a raised region of the epitaxial layer 102, and other regions of the surface of the epitaxial layer 102 except the raised region are planar regions, wherein B represents the planar regions. It can be seen that the height of the raised area is greater than that of the planar area, and the surface of the planar area is a plane, and it is to be understood that, in the planar area, two second type well areas 103 are provided, and for convenience of understanding, two second type well areas 103 are shown in the drawings in this application, one MOS device is formed in the second type well area 103 on the left side, one MOS device is also formed in the second type well area 103 on the right side, and two MOS devices are integrated with one raised area, and diodes are formed in the raised area, that is, two MOS devices are integrated with one diode. Taking the left MOS device as an example, the right side edge of the second type well region 103 and the left side edge of the protruding region are located on the same plane, and a region below the protruding region (a region marked by an arrow C in the figure) is defined as a fourth doped region, the fourth doped region is located directly below the protruding region, and the thickness of the fourth doped region is smaller than or equal to the thickness of the second type well region 103.
For the fourth doped region, it may be left untreated so that its doping concentration is the same as that of the underlying epitaxial layer 102; of course, an appropriate doping concentration may be selected for this region, for example, a heavy doping may be used in the fourth doped region, which is greater than the doping concentration of the underlying epitaxial layer 102, and the structure may be formed by multiple epitaxial processes.
By setting the inclined doped region 106 and optimizing the doping concentration of the fourth doped region, the reverse characteristic of the device can be greatly improved while the smaller forward on-resistance is obtained, the contradiction between the two is relieved, the method is also beneficial to improving the breakdown voltage of the whole MOSFET, and better comprehensive performance and reliability of the MOSFET device are finally realized.
As an implementation manner, the third doped region 107, the inclined doped region 106, and the second doped region 105 are all highly doped, and the doping concentrations of the third doped region 107, the inclined doped region 106, the second doped region 105, and the second type well region 103 are sequentially reduced. Meanwhile, the size of the inclined doped region 106 satisfies the formula:
L＞0，W＞0；
wherein L represents the difference in edge widths of the third doped region 107 and the inclined doped region 106 along the distance from the first doped region 104; w represents the difference in depth between the second doped region 105 and the inclined doped region 106.
The contact layer forms ohmic contact with the third doped region 107, the second doped region 105 and the inclined doped region 106, and naturally, ohmic contact is also formed between the contact layer and the first doped region 104. In the present application, the specific contact layer material is not limited, and for example, ni or other metal material may be selected as the contact layer material. When Ni metal is selected as the contact layer material, good ohmic contact can be formed between the Ni metal and the N-type doped region and between the Ni metal and the P-type doped region.
Through the setting of the doping concentration, when the inclined doping region 106 is introduced, the equivalent area of the third doping region 107 is increased, and when carrier large injection occurs, such as when abnormal working conditions such as large surge current occur, the bipolar on-resistance of the device is reduced due to the conductivity modulation effect and is far smaller than the channel resistance, the large surge current is prevented from flowing to the channel region and being injected into the grid oxide, the stronger surge current processing capability of the device is realized, and the drift of the threshold voltage Vt of the MOSFET is also avoided.
And, by introducing the inclined doped region 106, the resistance of part of the second doped region 105 is reduced, which is beneficial to reducing the base resistance R of the parasitic NPN transistor of the MOSFET B Meanwhile, abnormal heavy current is far away from the base region, and the parasitic NPN transistor is bypassed as far as possible, so that the risk of starting the parasitic NPN transistor is avoided, dV/dt failure, avalanche failure and short circuit failure are effectively prevented, and the reliability of the MOSFET device is improved.
In addition, by introducing the inclined doped region 106, the third doped region 107, the second doped region 105 and the second type well region 103 to generate a comprehensive modulation effect, the introduction of the structure is equivalent to introducing PN junction depletion region equivalent resistance capacitance with an automatic buffer inhibition effect on a current path, when abnormal working conditions occur, the device can automatically and flexibly expand PN depletion regions at different positions, further automatically generate depletion layer equivalent resistance capacitance with different sizes, automatically inhibit the problems of EMI electromagnetic interference, oscillation, surge and the like, and finally, the device has better capability of resisting electromagnetic interference, oscillation and surge and higher device reliability.
The detailed analysis is performed as follows:
for convenience of explanation, referring to fig. 5, fig. 5 shows a simplified schematic diagram of a semiconductor device integrated with an SBD according to an embodiment of the present application. Corresponding to the cross-sectional structure shown in fig. 3, PW represents the second type well region 103, np represents the first doped region 104, pp represents the second doped region 105, p+ located in the inclined region represents the inclined doped region 106, p+ located in the raised region represents the third doped region 107, ni and Ti/TiN represent the contact layer, GAOX represents the gate oxide layer 1081, gaply represents the doped polysilicon layer 1082, ild represents the interlayer dielectric layer 1083, al represents the first metal layer 111, wherein Al connected to the doped polysilicon layer 1082 represents the gate metal. L represents the difference in edge widths of the third doped region 107 and the inclined doped region 106 along the distance from the first doped region 104; w represents the difference in depth between the second doped region 105 and the inclined doped region 106. And, schottky contact with the raised region of the epitaxial layer 102 is realized by the contact layer Ti/TiN, and ohmic contact is realized by Ni.
For the device, the first metal layer 111 serves as a source, the second metal layer 112 serves as a drain, and when the device is normally operated at the first condition, the voltage of the gate metal connection is greater than the threshold voltage, and under the action of the electric field, the well region 103 under the gate oxide layer 1081 forms an inversion layer near the gate oxide layer 1081, and a current flows from the drain to the source, as shown by an arrow X in the figure. When the device is required to work at the third quadrant, the current is shown by an arrow Y, and a current path is formed through the integrated Schottky diode; when abnormal working conditions such as large surge current occur, the current path is shown by an arrow Z, and due to the conductivity modulation effect, the bipolar on-resistance of the device is reduced and is far smaller than the channel resistance, so that the large surge current is prevented from flowing to the channel region and is injected into the gate oxide, stronger surge current processing capacity of the device is realized, the drift of threshold voltage Vt of the MOSFET device can also be avoided, namely, by setting the third doped region 107 of the inclined doped region 106 and the corresponding doping concentration setting, when the abnormal working conditions such as large surge current occur, the surge large current flows out preferentially along the direction of the arrow Z, thereby avoiding influencing the gate region and protecting the gate region of the device.
Fig. 6 shows an equivalent circuit schematic diagram of another MOSFET, in which 5 represents a body diode, 6 represents a parasitic NPN transistor, and 7 represents an external schottky diode, and it can be seen from fig. 5 that if the parasitic NPN transistor is turned on, current may flow through the NPN transistor, and at this time, dV/dt failure, avalanche failure, and short circuit failure of the MOSFET transistor will be caused, which will affect the reliability of the MOSFET device.
In combination with fig. 5, the first doped region 104, the second doped region 105 and the N-epitaxial layer 102 form a parasitic NPN transistor of the device, and the second doped region 105 serves as the base of the parasitic NPN transistor, on the basis of which the base resistance R of the parasitic NPN transistor of the MOSFET is advantageously reduced by tilting the doped region 106 accordingly B Meanwhile, abnormal heavy current is far away from the base region, and the parasitic NPN transistor is bypassed as far as possible, so that the risk of starting the parasitic NPN transistor is avoided, dV/dt failure, avalanche failure and short circuit failure of the device are effectively prevented, and the reliability of the MOSFET device is improved.
In addition, since the inclined doped region 106, the third doped region 107, the second doped region 105 and the second type well region 103 are P-type regions with different doping concentrations, the inclined doped region 106, the third doped region 107, the second doped region 105 and the second type well region 103 generate a comprehensive modulation effect, which is equivalent to introducing a PN junction depletion region equivalent resistance capacitor with an automatic buffer inhibition effect on a current path, when abnormal working conditions occur, the device can automatically and flexibly expand PN depletion regions at different positions, further automatically generate depletion layer equivalent resistance capacitors with different sizes, and automatically inhibit the problems of EMI electromagnetic interference, oscillation, surge and the like.
As one implementation, the ion implantation angle of the inclined doped region 106 is 30 ° to 45 °, preferably the implantation angle is selected to be 45 °. When the injection angle is 45 DEG, on one hand, the design of the device is easier to optimize, the reverse characteristic of the device is greatly improved while the smaller forward on-resistance is obtained, and the optimization space is larger; on the other hand, the second doped region 105 and the third doped region 107 have the smallest comprehensive influence, the device has better electromagnetic interference resistance, oscillation resistance and surge resistance, and the device has higher reliability.
In addition, the width of the third doped region 107 may be set smaller, so as to improve the integration level of the whole device, have higher power density and lower device cost, and in order to make the integrated SBD possess good surge-resistant high-current characteristics, in one implementation, the area of the inclined doped region 106 is the same as that of the third doped region 107, and the width of the inclined doped region 106 is smaller than that of the second doped region 105.
In addition, after the inclined doped region 106 is introduced, the equivalent depth of the third doped region 107 is increased, so that the protruding height of the third doped region 107 can be reduced, namely the protruding height of the protruding region is reduced, the etching depth is reduced, the difficulty of the etching process is reduced, and the process cost is lower.
In one implementation, the bump area may be configured to be circular arc, and when the top of the integrated diode is circular arc, the side wall of the diode located in the bump area has no redundant SiO 2 And polysilicon, ni metal covers the circular arc side wall, and the electric performance and reliability of the device are further improved.
Based on the above implementation manner, the embodiment of the application further provides a method for manufacturing a semiconductor device of an integrated SBD, which is used for manufacturing the semiconductor device of the SBD, and the method for manufacturing the semiconductor device of the integrated SBD includes:
s102, providing a first type epitaxial wafer;
s104, performing ion implantation based on the set region of the first type epitaxial wafer to form a third doped region 107;
s106, etching the epitaxial wafer, forming a convex area and a plane area, wherein the height of the convex area is larger than that of the plane area, and the third doped area 107 is positioned in the convex area;
s108, manufacturing a second type well region 103 based on the surface layer of the planar region, wherein the second type well region 103 is adjacent to the raised region;
s110, manufacturing a first doped region 104 and a second doped region 105 based on the surface layer of the second type well region 103, wherein the first doped region 104 is in contact with the second doped region 105, and the second doped region 105 is adjacent to the raised region;
s112, manufacturing an inclined doped region 106 with a part positioned on the surface layer of the second doped region 105, and extending the other part of the inclined doped region 106 into the non-well region 103 below the raised region; the width of the inclined doped region 106 is smaller than the width of the second doped region 105; the first doped region 104 is a first type doped region, and the second doped region 105, the inclined doped region 106 and the third doped region 107 are all second type doped regions;
s114, manufacturing a grid structure 108 based on the surface of the second type well region 103;
s116, manufacturing a contact layer based on the surfaces of the first doped region 104, the second doped region 105, the inclined doped region 106 and the raised region, wherein the contact layer forms Schottky contact with the region except the third doped region 107 in the raised region;
s118, a first metal layer 111 is formed on the contact layer surface and a second metal layer 112 is formed on the epitaxial wafer back surface.
The epitaxial wafer includes a substrate 101 and an epitaxial layer 102, the substrate 101 is doped with n+ and the epitaxial layer 102 is doped with N-, referring to fig. 7, ion implantation is first performed in a set region of the epitaxial layer 102 to form a third doped region 107, and in practical application, the ion implantation in the set region may be implemented through a mask process.
It should be noted that when the ion concentration of the fourth doped region needs to be adjusted, a layer of N-epi layer 102 is first epitaxially grown, then the fourth doped region is ion-implanted, and a layer of N-epi layer 102 is then epitaxially grown, which is not described herein.
Next, referring to fig. 8, the epitaxial layer 102 is etched to form a raised region and a planar region, wherein the raised region has a height greater than that of the planar region, and the third doped region 107 is located in the raised region. The etching depth is equal to the ion implantation depth, and the regions on the side of the third doped region 107 are all etched.
Referring to fig. 9, a second type well region 103 is formed based on the surface layer of the planar region, the second type well region 103 is adjacent to the raised region, and the second type well region 103 is a P-type region.
Referring to fig. 10, a first doped region 104 is formed on the surface layer of the second type well region 103 by ion implantation, then referring to fig. 11, a second doped region 105 is formed by ion implantation, the first doped region 104 contacts the second doped region 105, the second doped region 105 is adjacent to the raised region, wherein the first doped region 104 is an N-type region, and the second doped region 105 is a P-type region.
Referring to fig. 12, the tilt ion implantation is continued, typically at an implantation angle of 30 ° to 45 °, for example, 45 ° ion implantation is selected.
In practical implementation, in order to protect the third doped region 107, implantation protection may be formed on the sidewall of the third doped region 107 by a sidewall process, for example, a silicon dioxide layer may be deposited on the surface of the structure schematically shown in fig. 11, and then the silicon dioxide layer is etched to remove, so that a sidewall is formed on the sidewall of the third doped region 107. When the inclined ion implantation is performed, the inclined ion implantation does not affect the third doped region 107 due to the protection of the sidewall.
Next, referring to fig. 13, a gate oxide layer 1081 is formed on the surface, for example, the gate oxide layer 1081 is formed by a thermal oxidation process. Referring to fig. 14, the doped polysilicon layer 1082 is deposited and then etched. Referring to fig. 15, the deposition of the interlayer dielectric 1083 is continued, and the etching of the interlayer dielectric 1083 is performed.
Referring to fig. 16, the deposition of the contact layer is continued, wherein the contact layer provided in the present application includes a first contact layer 109 and a second contact layer 110, the first contact layer 109 is made of Ti/TiN material, the second contact layer 110 is made of Ni material, schottky contact is formed between the first contact layer 109 and the epitaxial layer 102, and ohmic contact is formed through the second contact layer 110.
Referring to fig. 17, an opening is performed on the interlayer dielectric layer 1083, and then, as shown in fig. 2, a first metal layer 111 and a second metal layer 112 are deposited to complete the fabrication of the semiconductor device.
In summary, the present application provides a semiconductor device of an integrated SBD and a method for manufacturing the same, where the semiconductor device of the integrated SBD includes: a first type epitaxial wafer; the epitaxial wafer comprises a convex area and a plane area, and the height of the convex area is larger than that of the plane area; the second type well region 103 is positioned on the surface layer of the plane region, and the second type well region 103 is adjacent to the protruding region; the first doped region 104 and the second doped region 105 are positioned on the surface layer of the second type well region 103, the first doped region 104 is contacted with the second doped region 105, and the second doped region 105 is adjacent to the raised region; an inclined doped region 106 partially located on the surface layer of the second doped region 105, and another portion of the inclined doped region 106 extends into the non-well region 103 below the raised region; the width of the inclined doped region 106 is smaller than the width of the second doped region 105; a third doped region 107 located within the raised region and adjacent to one side of the second type well region 103; the first doped region 104 is a first type doped region, and the second doped region 105, the inclined doped region 106 and the third doped region 107 are all second type doped regions; a gate structure 108 located on the surface of the second type well region 103; the contact layer is positioned on the surfaces of the first doped region 104, the second doped region 105, the inclined doped region 106 and the raised region, wherein the contact layer forms Schottky contact with the region except the third doped region 107 in the raised region; a first metal layer 111 on the surface of the contact layer and a second metal layer 112 on the back of the epitaxial wafer. Because in the device provided by the application, the Schottky diode (SBD) is integrated in the convex area, when the semiconductor device works in the third quadrant, the current flow is realized through the integrated Schottky diode, the electrical performance and the reliability of the traditional PN junction body diode and the external anti-parallel diode are improved, and the device cost is reduced. Meanwhile, by introducing the inclined doped region 106 and the third doped region 107, the electrical performance and reliability of the device are further improved.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. An SBD integrated semiconductor device, the SBD integrated semiconductor device comprising:
a first type epitaxial wafer; the epitaxial wafer comprises a protruding area and a plane area, and the height of the protruding area is larger than that of the plane area;
the second type well region (103) is positioned on the surface layer of the plane region, and the second type well region (103) is adjacent to the protruding region;
the first doped region (104) and the second doped region (105) are positioned on the surface layer of the second type well region (103), the first doped region (104) is in contact with the second doped region (105), and the second doped region (105) is adjacent to the protruding region;
an inclined doped region (106) partially located on the surface layer of the second doped region (105), and the other part of the inclined doped region (106) extends into the non-second type well region (103) below the raised region; the width of the inclined doped region (106) is smaller than the width of the second doped region (105);
a third doped region (107) located within the raised region and adjacent to one side of the second type well region (103); the first doped region (104) is a first type doped region, and the second doped region (105), the inclined doped region (106) and the third doped region (107) are all second type doped regions;
a gate structure (108) located on a surface of the second type well region (103);
the contact layer is positioned on the surfaces of the first doped region (104), the second doped region (105), the inclined doped region (106) and the raised region, wherein the contact layer forms Schottky contact with the region of the raised region except the third doped region (107);
and a first metal layer (111) positioned on the surface of the contact layer and a second metal layer (112) positioned on the back surface of the epitaxial wafer.
2. The SBD-integrated semiconductor device according to claim 1, characterized in that the third doped region (107), the inclined doped region (106), the second doped region (105) are all heavily doped, and the doping concentrations of the third doped region (107), the inclined doped region (106), the second doped region (105) and the second type well region (103) decrease in sequence.
3. The SBD integrated semiconductor device according to claim 1, wherein the dimensions of the inclined doped region (106) satisfy the formula:
L＞0，W＞0；
wherein L represents the edge width difference of the third doped region (107) and the inclined doped region (106) along the distance from the first doped region (104); w represents the difference in depth between the second doped region (105) and the inclined doped region (106).
4. The SBD integrated semiconductor device according to claim 1, wherein the inclined doped region (106) has an ion implantation angle of 30 ° -45 °.
5. The SBD integrated semiconductor device according to claim 1, wherein the contact layer forms an ohmic contact with the third doped region (107), the second doped region (105) and the oblique doped region (106).
6. The SBD integrated semiconductor device according to claim 1, wherein the bump area is provided in a circular arc shape.
7. The SBD integrated semiconductor device according to claim 1, wherein the epitaxial wafer comprises a first type substrate (101) and a first type epitaxial layer (102) on one side of the first type substrate (101), the first type epitaxial layer (102) being lightly doped, the epitaxial wafer further comprising a fourth doped region under the raised region, the fourth doped region being a first type doped region and the fourth doped region being heavily doped.
8. The SBD integrated semiconductor device of claim 1, wherein the gate structure (108) comprises:
a gate oxide layer (1081) partially located on the surface of the second type well region (103);
a doped polysilicon layer (1082) located on the surface of the gate oxide layer (1081);
and a gate metal layer connected to the doped polysilicon layer (1082).
9. The SBD integrated semiconductor device of claim 1, wherein the first type is N-type and the second type is P-type.
10. A method for manufacturing a semiconductor device of an integrated SBD, characterized in that the method for manufacturing a semiconductor device according to any one of claims 1 to 9 comprises:
providing a first type epitaxial wafer;
performing ion implantation based on a set region of the first type epitaxial wafer to form a third doped region (107);
etching the epitaxial wafer, forming a protruding region and a plane region, wherein the height of the protruding region is larger than that of the plane region, and the third doped region (107) is positioned in the protruding region;
manufacturing a second type well region (103) based on the surface layer of the plane region, wherein the second type well region (103) is adjacent to the protruding region;
manufacturing a first doped region (104) and a second doped region (105) on the basis of the surface layer of the second type well region (103), wherein the first doped region (104) is in contact with the second doped region (105), and the second doped region (105) is adjacent to the protruding region;
a manufacturing part is positioned in an inclined doped region (106) on the surface layer of the second doped region (105), and the other part of the inclined doped region (106) extends into a non-second type well region (103) below the raised region; the width of the inclined doped region (106) is smaller than the width of the second doped region (105);
the first doped region (104) is a first type doped region, and the second doped region (105), the inclined doped region (106) and the third doped region (107) are all second type doped regions;
-fabricating a gate structure (108) based on the surface of the second type well region (103);
manufacturing a contact layer based on the first doped region (104), the second doped region (105), the inclined doped region (106) and the surface of the raised region, wherein the contact layer forms Schottky contact with the region of the raised region except the third doped region (107);
a first metal layer (111) is formed on the surface of the contact layer, and a second metal layer (112) is formed on the back surface of the epitaxial wafer.
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