CN116722032A - Diode device and manufacturing method thereof - Google Patents
Diode device and manufacturing method thereof Download PDFInfo
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- CN116722032A CN116722032A CN202311007048.0A CN202311007048A CN116722032A CN 116722032 A CN116722032 A CN 116722032A CN 202311007048 A CN202311007048 A CN 202311007048A CN 116722032 A CN116722032 A CN 116722032A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000010410 layer Substances 0.000 claims abstract description 244
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 23
- 238000002161 passivation Methods 0.000 claims abstract description 11
- 239000002344 surface layer Substances 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims description 12
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- 230000005684 electric field Effects 0.000 description 7
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- 230000000873 masking effect Effects 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
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- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Abstract
The application provides a diode device and a manufacturing method thereof, and relates to the technical field of semiconductors. The diode device includes: a substrate; an epitaxial layer on one side of the substrate; the terminal area is positioned on the surface layer of the epitaxial layer and is adjacent to the main junction area; the main junction region comprises a first doped region and a second doped region which are arranged at intervals, and the depth of the first doped region is smaller than that of the second doped region; a passivation protection layer located at one side of the termination region; a front metal layer positioned at one side of the main junction region; and a back metal layer positioned on the side of the substrate away from the epitaxial layer. The diode device and the manufacturing method thereof provided by the application have the effects of better electromagnetic interference resistance, oscillation, surge, voltage and current overshoot resistance, stronger short circuit tolerance and higher reliability of the device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a diode device and a manufacturing method thereof.
Background
The SiC Schottky diode has the main advantages that the forward voltage is reduced, and the on-state loss is reduced; meanwhile, the single-pole type SiC device is used as a single-pole type device, has no minority carrier storage and reverse recovery phenomena, can realize higher switching frequency, and is beneficial to fully playing the advantages of the SiC device. Therefore, in the application occasions of medium-low voltage, medium-low current and medium-high frequency (600-3000V, 5-20A and 150-200 kHz), the SiC Schottky diode (SBD) rapidly replaces the Si Fast Recovery Diode (FRD).
However, the schottky structure has a major problem in that its reverse leakage current is large and its breakdown characteristics are soft as the reverse voltage increases, since its barrier height is low and there is a mirror barrier lowering effect.
To overcome the above problems, the most common solution is to use SiC-based JBS (junction barrier schottky) diodes. The JBS structure directly improves the schottky barrier lowering effect of the device without affecting the forward performance of the device. By adjusting the conditions of the JBS cell structure size, the P-type region doping and the like, charge coupling is realized by utilizing carrier two-dimensional depletion, so that the strongest electric field on the contact surface of the metal semiconductor is pushed into the device, the electric field on the surface of the device is reduced, the Schottky barrier reduction effect is greatly weakened, the leakage current of the device is reduced, and higher breakdown voltage is realized.
However, the current JBS diode still presents the problem of poor anti-electromagnetic interference, oscillation, surge and voltage overcurrent and overcurrent capability when being applied to abnormal working conditions.
Disclosure of Invention
The application aims to provide a diode device, which is used for solving the problems that a JBS diode in the prior art still shows poor electromagnetic interference resistance, oscillation, surge and voltage overcurrent and impact resistance when being applied to abnormal working conditions.
In order to achieve the above object, the technical scheme adopted by the embodiment of the application is as follows:
in one aspect, an embodiment of the present application provides a diode device, including:
a substrate;
an epitaxial layer located on one side of the substrate;
the terminal area is positioned on the surface layer of the epitaxial layer and is adjacent to the main junction area; wherein,,
the main junction region comprises a first doped region and a second doped region which are arranged at intervals, and the depth of the first doped region is smaller than that of the second doped region;
a passivation protection layer positioned at one side of the terminal region;
the front metal layer is positioned at one side of the main junction area;
and the back metal layer is positioned on one side of the substrate away from the epitaxial layer.
Optionally, the second doped region is provided in an L-shape or an inverted T-shape.
Optionally, the second doped region includes a first doped layer, a second doped layer and a third doped layer, where the first doped layer, the second doped layer and the third doped layer are disposed layer by layer and form a step structure, and a width of the third doped layer is equal to a width of the first doped region.
Optionally, the width and the height of each step in the step structure are equal.
Optionally, a difference in height between the third doped layer and the first doped region is equal to a sum of heights of the first doped layer and the second doped layer.
Optionally, the first doped region and the third doped layer are disposed at equal intervals, and a side surface of the first doped layer or the second doped layer and an adjacent side surface of the first doped region are located on the same plane.
Optionally, when the second doped regions are provided in an L-shape, two adjacent second doped regions face the same side or opposite sides.
On the other hand, the embodiment of the application also provides a manufacturing method of the diode device, which comprises the following steps:
providing a substrate;
manufacturing an epitaxial layer on one side of the substrate, and manufacturing a terminal area and a main junction area on the surface layer of the epitaxial layer, wherein the terminal area is adjacent to the main junction area; the main junction region comprises a first doped region and a second doped region which are arranged at intervals, and the depth of the first doped region is smaller than that of the second doped region;
manufacturing a passivation protection layer based on one side of the terminal area;
manufacturing a front metal layer on the basis of one side of the main junction region;
and manufacturing a back metal layer based on the side of the substrate away from the epitaxial layer.
Optionally, the second doped region includes a first doped layer, a second doped layer and a third doped layer, the first doped layer, the second doped layer and the third doped layer are disposed layer by layer and form a step structure, the width of the third doped layer is equal to the width of the first doped region, an epitaxial layer is manufactured based on one side of the substrate, and the step of manufacturing a termination region and a main junction region based on a surface layer of the epitaxial layer includes:
manufacturing a first epitaxial layer on one side of the substrate;
manufacturing a first doping layer based on the first epitaxial layer;
manufacturing a second epitaxial layer on the basis of one side, far away from the substrate, of the first epitaxial layer;
manufacturing a second doping layer based on one side of the second epitaxial layer; wherein the second doped layer is opposite to the first doped layer;
manufacturing a third epitaxial layer on the basis of one side, far away from the substrate, of the second epitaxial layer;
respectively manufacturing a third doped layer and a first doped region based on the third epitaxial layer; wherein the third doped layer is opposite to the second doped layer.
Optionally, the step of separately fabricating the third doped layer and the first doped region based on the third epitaxial layer includes:
etching grooves which are arranged at intervals on the basis of the third epitaxial layer;
and performing ion implantation on the basis of the bottom of the groove to form a third doped layer and a first doped region.
Compared with the prior art, the application has the following beneficial effects:
the application provides a diode device and a manufacturing method thereof, wherein the diode device comprises: a substrate; an epitaxial layer on one side of the substrate; the terminal area is positioned on the surface layer of the epitaxial layer and is adjacent to the main junction area; the main junction region comprises a first doped region and a second doped region which are arranged at intervals, and the depth of the first doped region is smaller than that of the second doped region; a passivation protection layer located at one side of the termination region; a front metal layer positioned at one side of the main junction region; and a back metal layer positioned on the side of the substrate away from the epitaxial layer. Because the first doped region and the second doped region with different depths are respectively arranged in the main junction region provided by the application, the masking depth can be flexibly adjusted in actual use, the Schottky surface electric field can be better shielded, and the leakage current can be reduced. And when abnormal working conditions occur, the problems of electromagnetic interference (EMI), oscillation, surge and the like can be automatically restrained, so that the device is better in electromagnetic interference, oscillation, surge and voltage and current overshoot resistance, stronger in short circuit tolerance and higher in reliability.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a diode device according to an embodiment of the present application.
Fig. 2 is a schematic cross-sectional view of a second type of diode device according to an embodiment of the present application.
Fig. 3 is a schematic cross-sectional view of a third diode device according to an embodiment of the present application.
Fig. 4 is a schematic cross-sectional view of a diode device according to an embodiment of the present application.
Fig. 5 is a schematic cross-sectional view of a diode device according to an embodiment of the present application.
Fig. 6 is a sixth cross-sectional schematic diagram of a diode device according to an embodiment of the present application.
Fig. 7 is a seventh schematic cross-sectional view of a diode device according to an embodiment of the present application.
Fig. 8 is an eighth schematic cross-sectional view of a diode device according to an embodiment of the present application.
Fig. 9 is a ninth schematic cross-sectional view of a diode device according to an embodiment of the present application.
Fig. 10 is a tenth schematic cross-sectional view of a diode device according to an embodiment of the present application.
Fig. 11 is an eleventh schematic cross-sectional view of a diode device according to an embodiment of the present application.
Fig. 12 is a twelfth cross-sectional view of a diode device according to an embodiment of the present application.
Fig. 13 is a thirteenth cross-sectional view of a diode device according to an embodiment of the present application.
Fig. 14 is a fourteenth cross-sectional view of a diode device according to an embodiment of the present application.
Fig. 15 is an exemplary flowchart of a method for manufacturing a diode device according to an embodiment of the present application.
In the figure:
101-a substrate; 102-an epitaxial layer; 103-main junction region; 1031-a first doped region; 1032-a second doped region; 10321-a first doped layer; 10322-a second doped layer; 10323-a third doped layer; a 104-termination region; 105-passivation protection layer; 106-a front side metal layer; 107-a backside metal layer; 108-ohmic contact layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
As described in the background art, the current JBS diode exhibits poor anti-electromagnetic interference, oscillation, surge, and voltage overcurrent and overvoltage capability when applied to abnormal conditions.
In view of this, the present application provides a diode device, referring to fig. 1, the diode device includes: a substrate 101; an epitaxial layer 102 on one side of the substrate 101; a termination region 104 and a main junction region 103 positioned on the surface layer of the epitaxial layer 102, the termination region 104 being adjacent to the main junction region 103; the main junction region 103 includes a first doped region 1031 and a second doped region 1032 disposed at intervals, and a depth of the first doped region 1031 is smaller than a depth of the second doped region 1032; a passivation protection layer 105 located at one side of the termination region 104; a front metal layer 106 located on one side of the main junction region 103; a backside metal layer 107 on a side of the substrate 101 remote from the epitaxial layer 102.
Through the arrangement of the first doped region 1031 and the second doped region 1032 with different depths, the effect of flexibly adjusting the masking depth can be achieved, and then the Schottky surface electric field can be better shielded, and the leakage current can be reduced. And when abnormal working conditions occur, the problems of electromagnetic interference (EMI), oscillation, surge and the like can be automatically restrained, so that the device is better in electromagnetic interference, oscillation, surge and voltage and current overshoot resistance, stronger in short circuit tolerance and higher in reliability.
As one implementation, the second doped region 1032 may be provided in an L-shape or an inverted T-shape, as in fig. 1, the second doped region 1032 is provided in an L-shape; in fig. 2, the second doped region 1032 is provided as an inverted T-shape. In the actual preparation process, the structure can be manufactured in a buried layer mode.
In one implementation, in order to more flexibly adjust the masking depth, the second doped layer 10322 may be divided into multiple layers, for example, the second doped region 1032 includes a first doped layer 10321, a second doped layer 10322, and a third doped layer 10323, the first doped layer 10321, the second doped layer 10322, and the third doped layer 10323 are disposed layer by layer and form a step structure, and the width of the third doped layer 10323 is equal to the width of the first doped region 1031.
For example, referring to fig. 3, fig. 3 shows a schematic cross-sectional view of the second doped region 1032 with a stepped structure, and since the structure of the application is also equivalent to introducing a PN junction depletion region equivalent resistance capacitor with an automatic buffer suppression function on a current path, when abnormal working conditions occur, the device can automatically and flexibly expand PN depletion regions at different positions, thereby automatically generating depletion layer equivalent resistance capacitors with different sizes, automatically suppressing problems such as EMI electromagnetic interference, oscillation, surge, and the like, and finally, the device has better capability of resisting electromagnetic interference, oscillation, surge, voltage and current overshoot, stronger short circuit tolerance SCWT, and high device reliability.
When the second doped region 1032 is in a stepped structure, a plurality of additional PN junction depletion layer equivalent resistance capacitance regions can be introduced, the adjusting range is widened, the synergistic effect of different positions of the device is optimized, and when abnormal working conditions occur, the electromagnetic interference resistance, oscillation, surge and voltage current overshoot resistance can be stronger.
For convenience of description, referring to fig. 4, fig. 4 is a partially enlarged schematic view of fig. 3, wherein two steps, namely, a first step 10 and a second step 20, are disposed in the second doped region 1032. In addition, the second doped region 1032 is provided with three layers of the first doped layer 10321, the second doped layer 10322 and the third doped layer 10323, and in the three-layer structure, the first doped layer 10321 and the second doped layer 10322 can be manufactured by a buried layer process and are both P-type doped, and they together form the second doped region 1032 with a step structure.
The height of the first doped layer 10321 is X, the height of the second doped layer 10322 is Y, the height of the third doped layer 10323 is Z, the width of the third doped layer 10323 is a, the width of the first doped region 1031 is B, the height of the first doped region 1031 is H, and the value of a is equal to the value of B.
The applicant has found that when the width and the height of each step in the step structure are equal, and the height difference between the third doped layer 10323 and the first doped region 1031 is equal to the sum of the heights of the first doped layer 10321 and the second doped layer 10322, the following effects can be simultaneously achieved:
the surface electric field is further shielded at a certain depth, and is far away from the surface as far as possible and translated inwards, so that leakage current is reduced, and breakdown voltage of the device is improved. Meanwhile, the on-resistance is smaller, and the balance between the on-resistance and the short circuit capacity can be realized.
That is, in the present application, the value of X is equal to the value of Y, and Z-h=x+y, and the height and width of each step are X. For example, for the first stage step 10 of fig. 4, the width and height are both X; the second step 20 is also X in width and height. Furthermore, in one implementation, the first doped region 1031 and the second doped region 1032 are disposed at equal intervals, and the side surface of the first doped layer 10321 or the side surface of the second doped layer 10322 and the adjacent side surface of the first doped region 1031 are located on the same plane, for example, in fig. 4, a dotted line exists on the right side of the mark B, an upper portion of the dotted line is connected to the right side of the first doped region 1031, and a lower portion of the dotted line is connected to the left side of the first doped layer 10321, so that the left side surface of the first doped layer 10321 and the right side surface of the first doped region 1031 are located on the same plane. By the arrangement of the structure, the effect of the structure on the current channel can be ensured. Meanwhile, in order to ensure that an effect is generated on the current channel, at least one side of the second doped region is in contact with the terminal, as shown in fig. 4, the second doped region comprises three first doped regions and three second doped regions from left to right, the first doped region on the left is in contact with the terminal, and the first doped region on the right is also in contact with the terminal. Naturally, when the device is arranged, the first left side is the second doped region, the first right side is the first doped region, and the L-shaped structure of the second doped region faces to the right side; alternatively, the first left side is the second doped region, and the first right side is also the second doped region, which is not limited herein.
Through the specific dimension ratio of the first doped region 1031 and the second doped region 1032, the masking depth can be flexibly adjusted, the schottky surface electric field can be better shielded, the leakage current can be reduced, and the breakdown voltage can be improved. Meanwhile, through the comprehensive modulation effect on the current path between doped regions with different depths, the on-resistance can be flexibly and effectively regulated, and the contradiction between Ronsp and SCWT is relieved.
Of course, the structure of the second doped region 1032 shown in fig. 3 is merely illustrative, and in practical applications, the structure of the second doped region 1032 may vary and form a stepped structure in different regions.
For example, referring to fig. 5, in the second doped region 1032, only the first step 10 may be disposed, and the first step 10 may be disposed on the right side region of the first doped layer 10321. And the width and height of the first step 10 are also X. In the figure, 108 denotes an ohmic contact layer. In addition, for convenience of description, only a partial cross-sectional view of the diode device is shown in the following drawings.
Alternatively, referring to fig. 6, only the first step 10 may be provided, but the first step 10 is provided in the left region of the first doping layer 10321. And the width and height of the first step 10 are also X.
Of course, referring to fig. 7, two steps, namely, a first step 10 and a second step 20 may be provided, the first step 10 is disposed in the right area of the first doped layer 10321, the second step 20 is disposed in the left area of the first doped layer 10321, and the widths and heights of the first step 10 and the second step 20 are also X.
For example, referring to fig. 8, three steps, that is, a first step 10, a second step 20, and a third step 30 may be provided, wherein the first step 10 and the second step 20 are provided in a left region, and the third step 30 is provided in a right region of the first doping layer 10321.
In the above example, the case where the second doping regions 1032 are provided in the L-shape has been described in which the adjacent two second doping regions 1032 face the same side, but in some embodiments, the adjacent two second doping regions 1032 may also be provided to face opposite sides. The orientation of the present application refers to the situation that the first doped layer and the second doped layer are located at the left side or the right side of the third doped layer, and when the first doped layer and the second doped layer are located at the left side of the third doped layer, the second doped region 1032 faces to the left side; when the first doped layer and the second doped layer are located to the right of the third doped layer, then the second doped region 1032 is oriented to the right. As in fig. 4-8, the second doped regions 1032 all face to the left; of course, in a specific implementation, the second doped regions 1032 may also all face to the right, which is not limited herein.
When adjacent two second doping regions 1032 face opposite sides, the structure of each second doping region 1032 may be the same as that in the above example. For example, referring to fig. 9-11, two adjacent second doped regions 1032 may be provided, wherein the left second doped region 1032 faces the right, and the right second doped region 1032 faces the left. Also, in order to ensure that the structure has an effect on the current path based on the structure arrangement, the leftmost second doped region 1032 needs to be oriented to the right and needs to be disposed closest to the termination region 104; the rightmost second doped region 1032 needs to be oriented to the left and needs to be disposed closest to the termination region 104. In the present application, the number of doped regions is not limited, and may be determined according to the device performance requirement, for example, referring to fig. 11, in this example, the doped regions are provided with 6 total doped regions, the second doped region 1032 located at the leftmost side is R1, which is directed to the right, and the second doped region 1032 located at the rightmost side is R2, which is directed to the left.
Of course, instead of providing the second doped region 1032 as an L-type, the second doped region 1032 may be provided as an inverted T-type, or a combination of both. For example, referring to fig. 12 and 13, the second doped region 1032 is provided with both an L-shape and an inverted T-shape, and the L-shape and the step-shape are further provided with a step structure, so as to more flexibly adjust the masking depth. It can be seen from the figure that, in order to ensure that the structure has an effect on the current channel, when the L-shaped and inverted T-shaped second doped regions 1032 are simultaneously disposed in the device, the inverted T-shaped structure may be disposed in the middle of the main junction region 103, the L-shaped structure may be disposed on the left and right sides, and the leftmost second doped region 1032 needs to be oriented to the right and disposed at the position closest to the terminal region 104; the rightmost second doped region 1032 is desirably oriented to the left and is disposed closest to the termination region 104. Of course, an inverted T-shaped structure may be separately provided, for example, on the basis of fig. 2, a step structure may be provided on the inverted T-shaped second doped region 1032, which is not limited herein.
Based on the above implementation, applicants have found that the number of doped regions can be determined by:
when the number of doped regions is even:
the number of doped regions in the diode device satisfies the formula:
y=n/2, y represents the number of the second doped regions of the L-type, and n represents the total number of the doped regions; and when the number of the doped regions is even, the second doped regions of the L-shape are all oriented to the same side, and the width of each second doped region of the L-shape extends to the side edge of the adjacent first doped region, as shown in fig. 4-8.
When the number of doped regions is odd:
the number of second doped regions in the diode device is determined by the value of (n-3)/2;
wherein when the value of (n-3)/2 is even, then in the diode device, the number of the inverted T-shaped second doped regions is one, and the inverted T-shaped second doped regions are located at the middle position, and the width of the inverted T-shaped second doped regions extends to the side edge of the second first doped region; the number of the L-shaped second doped regions is (n-3)/2, the width of each L-shaped second doped region extends to the side edge of the adjacent first doped region, and each L-shaped second doped region faces to the middle position.
For example, referring to fig. 14, the total number of doped regions is 11, (n-3)/2=4, so the number of L-shaped second doped regions is 4, each L-shaped second doped region faces the middle position, and in each L-shaped second doped region, the side of the first doped layer or the second doped layer and the side of the adjacent first doped region are located on the same plane. And, the width of the second doped region of the inverted T-shape extends to the side of the second first doped region, in the figure, 40 represents the first doped region, 50 represents the second first doped region, and the second doped region of the inverted T-shape and the side of the second first doped region 50 are located on the same plane.
When the value of (n-3)/2 is odd, the number of the inverted T-shaped second doped regions is one, and the inverted T-shaped second doped regions are positioned at the middle position, and the width of the inverted T-shaped second doped regions extends to the side edge of the third first doped region; the number of the L-shaped second doped regions is (n-5)/2, the width of each L-shaped second doped region extends to the side edge of the adjacent first doped region, and each L-shaped second doped region faces to the middle position.
As shown in fig. 12 and 13, at this time, the total number of doped regions is 9, (n-3)/2=3, and thus, the value of (n-3)/2 is odd, the number of L-shaped second doped regions is (n-5)/2=2, and each L-shaped second doped region faces toward the middle position, and in each L-shaped second doped region, the side edge of the first doped layer or the second doped layer and the side edge of the adjacent first doped region are located on the same plane. For example, as shown in fig. 12, in each of the L-shaped second doped regions, the side edge of the first doped layer is located on the same plane as the side edge of the adjacent first doped region; as shown in fig. 13, in each of the L-shaped second doped regions, the side of the second doped layer is in the same plane as the side of the adjacent first doped region. And, the width of the second doped region of the inverted T-shape extends to the side of the third first doped region, in the figure, 40 represents the first doped region, 50 represents the second first doped region, 60 represents the third first doped region, and the second doped region of the inverted T-shape and the side of the third first doped region 60 are located on the same plane.
Alternatively, after determining the total number of doped regions, the structure of the diode device may also be determined using the value of (n/3), wherein when the value of n/3 is an integer and there is no remainder, the structure of the diode device may be selectively determined using the structures of fig. 9 to 11, on the basis that the number of L-shaped second doped regions is (n/3) x 2; of course, the structure of the diode device may also be determined based on the parity of the total number of doped regions, as shown in fig. 4-8 and fig. 12-14. When n/3 has a remainder, the structure of fig. 9-11 cannot be adopted, and the structure of the diode device can be determined only according to the parity of the total number of doped regions, such as the structures shown in fig. 4-8 and fig. 12-14.
For example, when the total number of doped regions is 9, then the value of n/3 is an integer and there is no remainder, at this time, the structure of fig. 9-11 may be used to fabricate a diode device, specifically, the number of L-shaped second doped regions is (n/3) x2, i.e., when n is equal to 9, the number of L-shaped second doped regions is 4. And, as shown in fig. 9-11, every two L-shaped second doped regions are taken as a group and all face the middle first doped region, and at the same time, the width of each L-shaped second doped region extends to the side edge of the middle first doped region. Of course, when the total number of doped regions is 9, the total number of doped regions is an odd number, and thus, the diode device may also be fabricated using the structure of fig. 12 or 13.
When the total number of doped regions is 12, the n/3 value is an integer and no remainder is found, and the diode device can be fabricated by using the structures of fig. 9-11, and the total number of doped regions is an even number, so that the diode device can be fabricated by using the structures of fig. 4-8.
When the total number of doped regions is 11, n/3 has a remainder at this time, and thus the diode device cannot be fabricated using the structure of fig. 9 to 11 at this time, but only using the structure of fig. 14.
Based on the above implementation manner, the embodiment of the present application further provides a method for manufacturing a diode device, referring to fig. 15, the method includes:
s102, providing a substrate 101;
s104, manufacturing an epitaxial layer 102 on the basis of one side of the substrate 101, and manufacturing a terminal area 104 and a main junction area 103 on the basis of the surface layer of the epitaxial layer 102, wherein the terminal area 104 is adjacent to the main junction area 103; the main junction region 103 includes a first doped region 1031 and a second doped region 1032 disposed at intervals, and a depth of the first doped region 1031 is smaller than a depth of the second doped region 1032;
s106, manufacturing a passivation protection layer 105 based on one side of the terminal region 104;
s108, manufacturing a front metal layer 106 based on one side of the main junction region 103;
s110, a back metal layer 107 is fabricated based on a side of the substrate 101 away from the epitaxial layer 102.
Wherein, the step of S104 includes:
s1041, manufacturing a first epitaxial layer 102 on the basis of one side of a substrate 101;
s1042, manufacturing a first doped layer 10321 based on the first epitaxial layer 102;
s1043, manufacturing a second epitaxial layer 102 based on the side of the first epitaxial layer 102 away from the substrate 101;
s1044, manufacturing a second doping layer 10322 based on the second epitaxial layer 102; the second doped layer 10322 is opposite to the first doped layer 10321;
s1045, manufacturing a third epitaxial layer 102 based on the side of the second epitaxial layer 102 away from the substrate 101;
in S1046, the third doped layer 10323 is formed on the basis of the third epitaxial layer 102 and is opposite to the first doped region 1031, and the third doped layer 10323 is opposite to the second doped layer 10322.
The opposite positions of the first doped layer 10321, the second doped layer 10322, and the third doped layer 10323 in the present application are all disposed at designated positions, so as to integrally form the L-shaped or inverted T-shaped second doped region 1032.
And, the step of S106 includes:
etching the grooves which are arranged at intervals on the basis of the third epitaxial layer 102;
ion implantation is performed based on the trench bottom to form a third doped layer 10323 and a first doped region 1031.
In the present application, the first doped region 1031 and the second doped region 1032 are fabricated by using a buried layer, and it can be understood that, in the overall process, an epitaxial layer is fabricated first, and then a buried layer is fabricated.
Specifically, in the preparation process of the present application, a first epitaxial layer is first fabricated, and then ion implantation is performed on the first epitaxial layer 102 to form a first doped layer 10321, where the first doped layer 10321 is a buried layer; then, a second epitaxial layer is fabricated, and then ion implantation is performed on the corresponding position of the second epitaxial layer to form a second doped layer 10322, where the second doped layer 10322 is also a buried layer. Then, the third epitaxial layer 102 is grown, and trenches are etched on the third epitaxial layer 102, wherein the trenches are spaced apart and have the same depth, and then ion implantation is performed along the bottom of the trenches to form the third doped layer 10323 and the first doped region 1031. Since the depth of the third doped layer 10323 is greater than the depth of the first doped region 1031, ion implantation is required to be performed separately during ion implantation, and generally, ion implantation of the third doped layer 10323 is performed first and then ion implantation of the first doped region 1031 is performed. After the ion implantation of the main junction region 103 is finished, ion implantation is continued along the terminal region 104, and then an ion high temperature annealing process is performed. Thereafter, a conventional passivation layer 105 process, an ohmic contact process, a front side metal process, and a back side metal process are performed, which will not be described herein.
In summary, the present application provides a diode device and a method for manufacturing the same, the diode device includes: a substrate 101; an epitaxial layer 102 on one side of the substrate 101; a termination region 104 and a main junction region 103 positioned on the surface layer of the epitaxial layer 102, the termination region 104 being adjacent to the main junction region 103; the main junction region 103 includes a first doped region 1031 and a second doped region 1032 disposed at intervals, and a depth of the first doped region 1031 is smaller than a depth of the second doped region 1032; a passivation protection layer 105 located at one side of the termination region 104; a front metal layer 106 located on one side of the main junction region 103; a backside metal layer 107 on a side of the substrate 101 remote from the epitaxial layer 102. In the main junction region 103 provided by the application, the first doped region 1031 and the second doped region 1032 with different depths are respectively arranged, so that the masking depth can be flexibly adjusted in actual use, the electric field on the Schottky surface can be better shielded, and the leakage current can be reduced. And when abnormal working conditions occur, the problems of electromagnetic interference (EMI), oscillation, surge and the like can be automatically restrained, so that the device is better in electromagnetic interference, oscillation, surge and voltage and current overshoot resistance, stronger in short circuit tolerance and higher in reliability.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A diode device, the diode device comprising:
a substrate (101);
an epitaxial layer (102) located on one side of the substrate (101);
a terminal region (104) and a main junction region (103) which are positioned on the surface layer of the epitaxial layer (102), wherein the terminal region (104) is adjacent to the main junction region (103); wherein,,
the main junction region (103) comprises a first doped region (1031) and a second doped region (1032) which are arranged at intervals, and the depth of the first doped region (1031) is smaller than that of the second doped region (1032);
a passivation layer (105) located on one side of the termination region (104);
a front metal layer (106) located on one side of the main junction region (103);
and a back metal layer (107) located on a side of the substrate (101) remote from the epitaxial layer (102).
2. The diode device of claim 1, wherein the second doped region (1032) is provided in an L-shape or an inverted T-shape.
3. The diode device of claim 1, wherein the second doped region (1032) comprises a first doped layer (10321), a second doped layer (10322) and a third doped layer (10323), the first doped layer (10321), the second doped layer (10322) and the third doped layer (10323) being arranged layer by layer and forming a stepped structure, and a width of the third doped layer (10323) being equal to a width of the first doped region (1031).
4. The diode device of claim 3, wherein each step in the stair step structure has a width equal to a height.
5. The diode device of claim 4, wherein a height difference between the third doped layer (10323) and the first doped region (1031) is equal to a sum of heights of the first doped layer (10321) and the second doped layer (10322).
6. A diode device as claimed in claim 3, characterized in that the first doped region (1031) is arranged equidistant from the third doped layer (10323) and that the side of the first doped layer (10321) or the second doped layer (10322) is in the same plane as the adjacent side of the first doped region (1031).
7. The diode device of claim 1, wherein when said second doped regions (1032) are arranged in an L-shape, adjacent two of said second doped regions (1032) are oriented to the same side or opposite sides.
8. The manufacturing method of the diode device is characterized by comprising the following steps of:
providing a substrate (101);
manufacturing an epitaxial layer (102) on the basis of one side of the substrate (101), and manufacturing a terminal area (104) and a main junction area (103) on the basis of a surface layer of the epitaxial layer (102), wherein the terminal area (104) is adjacent to the main junction area (103); wherein the main junction region (103) comprises a first doped region (1031) and a second doped region (1032) which are arranged at intervals, and the depth of the first doped region (1031) is smaller than that of the second doped region (1032);
-making a passivation layer (105) on the basis of one side of the termination region (104);
manufacturing a front metal layer (106) on the basis of one side of the main junction region (103);
a back metal layer (107) is produced on the basis of the side of the substrate (101) remote from the epitaxial layer (102).
9. The method for manufacturing a diode device according to claim 8, wherein the second doped region (1032) includes a first doped layer (10321), a second doped layer (10322), and a third doped layer (10323), the first doped layer (10321), the second doped layer (10322), and the third doped layer (10323) are arranged layer by layer and form a step structure, and a width of the third doped layer (10323) is equal to a width of the first doped region (1031), an epitaxial layer (102) is manufactured based on one side of the substrate (101), and a termination region (104) and a main junction region (103) are manufactured based on a surface layer of the epitaxial layer (102), comprising:
-fabricating a first epitaxial layer (102) on the basis of one side of the substrate (101);
-fabricating a first doped layer (10321) based on the first epitaxial layer (102);
-fabricating a second epitaxial layer (102) based on a side of the first epitaxial layer (102) remote from the substrate (101);
-creating a second doped layer (10322) based on one side of the second epitaxial layer (102); wherein the second doped layer (10322) is located opposite to the first doped layer (10321);
-fabricating a third epitaxial layer (102) based on a side of the second epitaxial layer (102) remote from the substrate (101);
respectively manufacturing a third doping layer (10323) and a first doping region (1031) based on the third epitaxial layer (102); wherein the third doped layer (10323) is located opposite to the second doped layer (10322).
10. The method of manufacturing a diode device according to claim 9, wherein the step of manufacturing a third doped layer (10323) and the first doped region (1031) based on the third epitaxial layer (102) respectively comprises:
etching grooves which are arranged at intervals on the basis of the third epitaxial layer (102);
ion implantation is performed on the basis of the bottom of the groove so as to form a third doped layer (10323) and a first doped region (1031).
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