CN110534575B - VDMOS device - Google Patents
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- CN110534575B CN110534575B CN201910831289.4A CN201910831289A CN110534575B CN 110534575 B CN110534575 B CN 110534575B CN 201910831289 A CN201910831289 A CN 201910831289A CN 110534575 B CN110534575 B CN 110534575B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 104
- 210000000746 body region Anatomy 0.000 claims description 24
- 238000002955 isolation Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 11
- 230000008569 process Effects 0.000 abstract description 8
- 238000011084 recovery Methods 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- 239000000969 carrier Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention provides a VDMOS device, and belongs to the technical field of semiconductor devices. In application scenes such as a bridge circuit and the like needing diode freewheeling, the VDMOS device provided by the invention can use a channel region as a freewheeling channel, and an external anti-parallel diode does not need to be added to the VDMOS, so that the system volume can be reduced. Meanwhile, the channel of the VDMOS is used for follow current, no excess carrier is injected into the drift region, the problem of reverse recovery of body diode follow current of the conventional VDMOS is solved, the problems of increase of device electric leakage, deterioration of high-temperature characteristics and the like are solved, the area of the device is not increased additionally, and the process is simple.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a VDMOS device.
Background
The power device is an indispensable electronic component in a power control circuit and a power switch circuit, and the power MOSFET always dominates the market of power semiconductor devices by virtue of the excellent performance of the power MOSFET. Power MOSFETs are required to freewheel with a diode in many applications. For example, power MOSFET devices are commonly used as switching devices in half-bridge circuits for power conversion applications. Due to the existence of the switching delay, when the grid signal of one power MOSFET is changed to be low, the power MOSFET is not immediately turned off, and if the other power transistor is turned on at the moment, a large current is generated to damage the device because both transistors are turned on. Therefore, enough time must be allowed for one power MOSFET to safely turn off before the other power MOSFET can turn on, which is called dead time. In the dead time, the current on the inductive load needs to follow current by using a diode, so that the current can change more smoothly, and the device is prevented from being damaged.
In the prior art, this problem is usually solved by using an anti-parallel diode outside the power MOSFET or a body diode employing the power MOSFET. For the reverse parallel diode outside the power MOSFET, the number of devices is increased, and the system volume is increased. The body diode of the power MOSFET is adopted to carry out follow current, excessive non-equilibrium carriers can be introduced in the forward conduction process of the body diode, so that the reverse recovery time of the body diode is increased, the switching speed of a device is influenced, and the loss in the reverse recovery process is increased. The body diode of the power MOSFET is optimized, and the scheme typically has a lifetime control technique and an integrated schottky diode. Although the stored charge of the diode can be reduced by the lifetime control technique, it generally causes problems such as increased device leakage and poor high-temperature characteristics. The method of integrating the schottky diode may result in an increased device area and a complicated process.
Disclosure of Invention
The invention aims to solve the technical problem in the prior art and provides a VDMOS device.
In order to solve the technical problem, an embodiment of the present invention provides a VDMOS device, which includes a metalized drain electrode, a first conductive type semiconductor highly-doped substrate, a first conductive type semiconductor doped drift region, an isolation dielectric layer, and a metalized source electrode, which are sequentially stacked from bottom to top;
the first conductive type semiconductor doping drift region is provided with a trench gate structure, a second conductive type semiconductor body region, a second conductive type semiconductor high-doping contact region and a first conductive type high-doping source region;
the second conductive type semiconductor body region is positioned on two sides of the trench gate structure, and the second conductive type semiconductor highly-doped contact region and the side surface of the first conductive type highly-doped source region are mutually contacted, positioned on the second conductive type semiconductor body region and positioned on two sides of the trench gate structure;
the isolation medium layer is positioned on the first part of the first conductive type high-doping source region and the trench gate structure; the metalized source electrode is positioned on the second part of the first conductive type high-doping source region and the second conductive type semiconductor high-doping contact region, and the side surface of the metalized source electrode is contacted with the side surface of the isolation medium layer;
a first conductive type semiconductor lightly doped region is arranged between the second conductive type semiconductor body region and the trench gate structure on at least one side, the side surface of the trench gate structure is contacted with one side surface of the first conductive type semiconductor doping drift region, the first conductive type semiconductor lightly doped region and the first conductive type highly doped source region, the other side surface of the first conductive type semiconductor lightly doped region is contacted with one side surface of the second conductive type semiconductor body region, the bottom surface of the first conductive type semiconductor lightly doped region is flush with the bottom surface of the second conductive type semiconductor body region, and the depth of the first conductive type semiconductor lightly doped region is smaller than the depth of the bottom surface of a gate electrode in the trench gate structure;
the work function of the gate electrode is smaller than that of the first conductive type semiconductor lightly doped region, and the width W of the first conductive type semiconductor lightly doped region satisfies: w is less than
Wherein N is1、N2The doping concentrations of the first conductivity type semiconductor lightly doped region and the second conductivity type semiconductor body region respectively,
and
respectively the work functions of the first conductivity type semiconductor lightly doped region and the gate electrode,sis the dielectric constant of the semiconductor, niIs the semiconductor intrinsic carrier concentration, q is the electron charge amount, k is the boltzmann constant, and T is the temperature.
On the basis of the technical scheme, the invention can be further improved as follows.
Furthermore, the trench gate structure comprises a gate dielectric layer and a gate electrode arranged in the gate oxide layer.
Further, the gate dielectric layer is a gate oxide layer.
Further, the first conductive type is an N type, and the second conductive type is a P type.
Further, the first conductive type is a P type, and the second conductive type is an N type.
The invention has the beneficial effects that: in application scenes such as a bridge circuit and the like needing diode freewheeling, the VDMOS device provided by the invention can use a channel region as a freewheeling channel, and an external anti-parallel diode does not need to be added to the VDMOS, so that the system volume can be reduced. Meanwhile, the channel of the VDMOS is used for follow current, no excess carrier is injected into the drift region, the problem of reverse recovery of body diode follow current of the conventional VDMOS is solved, the problems of increase of device electric leakage, deterioration of high-temperature characteristics and the like are solved, the area of the device is not increased additionally, and the process is simple.
Drawings
Fig. 1 is a schematic structural diagram of a VDMOS device according to a first embodiment of the present invention;
FIG. 2 is an initial band diagram and a curved band diagram of an embodiment of the invention;
fig. 3 is a schematic structural diagram of a VDMOS device according to a second embodiment of the invention.
In the drawings, the components represented by the respective reference numerals are listed below:
1. the structure comprises a metalized drain electrode, 2, a first conduction type semiconductor highly-doped substrate, 3, a first conduction type semiconductor doped drift region, 4, a second conduction type semiconductor body region, 5, a second conduction type semiconductor highly-doped contact region, 6, a first conduction type highly-doped source region, 8, a trench gate structure, 9, a gate dielectric layer, 10, a gate electrode, 11, an isolation dielectric layer, 12, a metalized source electrode, 31 and a first conduction type semiconductor lightly-doped region.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, a VDMOS device according to a first embodiment of the present invention includes a metalized drain electrode 1, a first conductive type semiconductor highly doped substrate 2, a first conductive type semiconductor doped drift region 3, an isolation dielectric layer 11, and a metalized source electrode 12, which are sequentially stacked from bottom to top;
the first conductive type semiconductor doping drift region 3 is provided with a trench gate structure 8, a second conductive type semiconductor body region 4, a second conductive type semiconductor high doping contact region 5 and a first conductive type high doping source region 6;
the second conductive type semiconductor body region 4 is positioned at two sides of the trench gate structure 8, and the second conductive type semiconductor highly-doped contact region 5 and the first conductive type highly-doped source region 6 are positioned on the second conductive type semiconductor body region 4 and positioned at two sides of the trench gate structure 8, wherein the side surfaces of the second conductive type semiconductor highly-doped contact region and the first conductive type highly-doped source region are mutually contacted;
the isolation medium layer 11 is positioned on the first part of the first conductive type high-doping source region 6 and the trench gate structure 8; the metalized source electrode 12 is positioned on the second part of the first conductive type high-doping source region 6 and the second conductive type semiconductor high-doping contact region 5, and the side surface of the metalized source electrode is contacted with the side surface of the isolation medium layer 11;
a first conductive type semiconductor lightly doped region 31 is arranged between the second conductive type semiconductor body region 4 and the trench gate structure 8 at two sides, the side surface of the trench gate structure 8 is contacted with one side surface of the first conductive type semiconductor doping drift region 3, the first conductive type semiconductor lightly doped region 31 and the first conductive type highly doped source region 6, the other side surface of the first conductive type semiconductor lightly doped region 31 is contacted with one side surface of the second conductive type semiconductor body region 4, the bottom surface of the first conductive type semiconductor lightly doped region 31 is flush with the bottom surface of the second conductive type semiconductor body region 4, and the depth of the bottom surface is smaller than the depth of the bottom surface of the gate electrode 10 in the trench gate structure 8;
the work function of the gate electrode 10 is smaller than that of the first conductivity-type semiconductor lightly doped region 31, and the width W of the first conductivity-type semiconductor lightly doped region 31 satisfies: w is less than
Wherein N is1、N2Respectively the doping concentrations of the first conductivity type semiconductor lightly doped region 31 and the second conductivity type semiconductor body region 4,
and
respectively the work functions of the first conductivity type semiconductor lightly doped region 31 and the gate electrode 10,sis the dielectric constant of the semiconductor, niIs the semiconductor intrinsic carrier concentration, q is the electron charge amount, k is the boltzmann constant, and T is the temperature.
In the embodiment, the VDMOS device provided by the invention can use the channel region as the freewheeling channel, and an external anti-parallel diode is not required to be added to the VDMOS, so that the system volume can be reduced. Meanwhile, the channel of the VDMOS is used for follow current, no excess carrier is injected into the drift region, the problem of reverse recovery of body diode follow current of the conventional VDMOS is solved, the problems of increase of device electric leakage, deterioration of high-temperature characteristics and the like are solved, the area of the device is not increased additionally, and the process is simple.
The working principle of the present invention will be described in detail by taking an N-channel VDMOS as an example, in which the first conductive type semiconductor lightly doped region 31 is an N-type semiconductor lightly doped region, the second conductive type semiconductor body region 4 is a P-type semiconductor region, and the first conductive type semiconductor doped drift region 3 is an N-type drift region. The specific principle is as follows:
an initial energy band diagram of the first conductivity type semiconductor lightly doped region 31 is shown in fig. 2 (a). When the device is not biased, the work function of the gate electrode 10 is reduced
Work function smaller than N-type semiconductor lightly doped region
The work function difference causes the energy band of the first conductive type semiconductor lightly doped region 31 near the interface of the gate dielectric layer 9 to bend upwards to form a depletion region with a width of
A PN junction depletion region having a width of
Since the width W of the first conductive type semiconductor lightly doped region 31 is smaller than
The first conductivity type semiconductor lightly doped region 31 is entirely a depletion region as shown in (b) of fig. 2.
When the N-channel VDMOS is in the MOS working mode, the working principle of the N-channel VDMOS is completely the same as that of a conventional MOS device. When the gate electrode 10 is biased to zero, the first conductive type semiconductor lightly doped region 31 is completely depleted, and the device has no current, when the gate electrode 10 is biased in the forward direction, the metalized drain electrode 1 is biased in the forward direction, and the metalized source electrode 12 is grounded, the surface energy band of the first conductive type semiconductor lightly doped region 31 bends downwards to form an electron accumulation layer, so that the device is conducted.
When the N-channel VDMOS is in a freewheeling state, the metalized source electrode 12 is positively biased, the metalized drain electrode 1 is grounded, and the gate electrode 10 is zero biased. At this time, the potential of the second conductivity type semiconductor body region 4, which is equipotential to the metalized source electrode 12, is raised, so that the depletion region in the first conductivity type semiconductor lightly doped region 31 is reduced, an electron channel occurs, and electrons can enter the high potential metalized source electrode 12 from the metalized drain electrode 1 through the first conductivity type semiconductor lightly doped region 31, thereby forming a forward current. Since the current is a majority current, minority carriers are not accumulated in the first conductive type semiconductor doped drift region 3, and thus a minority carrier storage effect is not generated. Because the channel region follow current of the VDMOS is utilized, the area of a device is not increased, the process is completely compatible with the conventional VDMOS, and the process difficulty is not increased.
As shown in fig. 3, a VDMOS device according to a second embodiment of the present invention is provided, in this embodiment, on the basis of the first embodiment, a lightly doped region 31 of a first conductivity type semiconductor is provided between a second conductivity type semiconductor body 4 and a trench gate structure 8 on one side.
In the above embodiment, the number of the first conductive type semiconductor lightly doped regions 31 is adjusted to adjust the freewheel channel resistance, so as to adjust the freewheel current.
Optionally, the trench gate structure 8 includes a gate dielectric layer 9 and a gate electrode 10 disposed in the gate oxide layer 9. Optionally, the gate dielectric layer 9 is a gate oxide layer.
Optionally, the first conductivity type is an N-type, and the second conductivity type is a P-type.
Optionally, the first conductivity type is a P type, and the second conductivity type is an N type.
The VDMOS device can use the channel region as a follow current channel, and an external anti-parallel diode is not required to be added to the VDMOS, so that the system volume can be reduced. Meanwhile, the channel of the VDMOS is used for follow current, no excess carrier is injected into the drift region, the problem of reverse recovery of body diode follow current of the conventional VDMOS is solved, the problems of increase of device electric leakage, deterioration of high-temperature characteristics and the like are solved, the area of the device is not increased additionally, and the process is simple.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (5)
1. A VDMOS device comprises a metalized drain electrode (1), a first conductive type semiconductor highly-doped substrate (2), a first conductive type semiconductor doped drift region (3), an isolation dielectric layer (11) and a metalized source electrode (12) which are sequentially stacked from bottom to top;
the first conductive type semiconductor doping drift region (3) is provided with a trench gate structure (8), a second conductive type semiconductor body region (4), a second conductive type semiconductor high doping contact region (5) and a first conductive type high doping source region (6);
the second conductive type semiconductor body region (4) is positioned on two sides of the trench gate structure (8), the second conductive type semiconductor highly-doped contact region (5) and the first conductive type highly-doped source region (6) are positioned above the second conductive type semiconductor body region (4) in a manner that the side surfaces of the second conductive type semiconductor highly-doped contact region and the first conductive type highly-doped source region are mutually contacted, and the second conductive type semiconductor highly-doped contact region (5) and the first conductive type highly-doped source region (6) as well as the other second conductive type semiconductor highly-doped contact region (5) and the first conductive type highly-doped source region (6) are respectively positioned on two sides of the trench gate structure (8);
the isolation dielectric layer (11) is positioned on the first part of the first conductive type high-doping source region (6) and the trench gate structure (8); the metalized source electrode (12) is positioned on the second part of the first conductive type high-doping source region (6) and the second conductive type semiconductor high-doping contact region (5), and the side surface of the metalized source electrode is contacted with the side surface of the isolation dielectric layer (11);
the trench gate structure is characterized in that a first conductive type semiconductor lightly doped region (31) is arranged between the second conductive type semiconductor body region (4) and the trench gate structure (8) on at least one side, the side face of the trench gate structure (8) is in contact with one side face of the first conductive type semiconductor doped drift region (3), the first conductive type semiconductor lightly doped region (31) and a first conductive type high doping source region (6), the other side face of the first conductive type semiconductor lightly doped region (31) is in contact with one side face of the second conductive type semiconductor body region (4), the bottom face of the first conductive type semiconductor lightly doped region (31) is flush with the bottom face of the second conductive type semiconductor body region (4), and the depth of the bottom face is smaller than the depth of the bottom face of a gate electrode (10) in the trench gate structure (8);
the work function of the gate electrode (10) is smaller than that of the first conductivity type semiconductor lightly doped region (31), and the width W of the first conductivity type semiconductor lightly doped region (31) satisfies: w is less than
Wherein N is1、N2Respectively the doping concentrations of the first conductivity type semiconductor lightly doped region (31) and the second conductivity type semiconductor body region (4),
and
respectively, a first conductivity type semiconductor lightly doped region (31) and a gate electrode (10),sis the dielectric constant of the semiconductor, niIs the semiconductor intrinsic carrier concentration, q is the electron charge amount, k is the boltzmann constant, and T is the temperature.
2. A VDMOS device according to claim 1, characterized in that the trench-gate structure (8) comprises a gate dielectric layer (9) and a gate electrode (10) arranged in the gate dielectric layer (9).
3. A VDMOS device according to claim 2, wherein the gate dielectric layer (9) is a gate oxide layer.
4. The VDMOS device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
5. The VDMOS device of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.
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| CN201910831289.4A CN110534575B (en) | 2019-09-04 | 2019-09-04 | VDMOS device |
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| US20100301410A1 (en) * | 2008-09-30 | 2010-12-02 | Infineon Technologies Austria Ag | Semiconductor device and manufacturing method therefor |
| CN109065628A (en) * | 2018-08-21 | 2018-12-21 | 电子科技大学 | A kind of slot grid DMOS device of body area varying doping |
| CN109904155A (en) * | 2019-01-31 | 2019-06-18 | 电子科技大学 | A kind of silicon carbide MOSFET device of the reversed freewheeling diode of integrated high-speed |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100301410A1 (en) * | 2008-09-30 | 2010-12-02 | Infineon Technologies Austria Ag | Semiconductor device and manufacturing method therefor |
| CN109065628A (en) * | 2018-08-21 | 2018-12-21 | 电子科技大学 | A kind of slot grid DMOS device of body area varying doping |
| CN109904155A (en) * | 2019-01-31 | 2019-06-18 | 电子科技大学 | A kind of silicon carbide MOSFET device of the reversed freewheeling diode of integrated high-speed |
Non-Patent Citations (1)
| Title |
|---|
| An Ultra-Low Qrr Cell-Distributed Schottky Contacts SJ-MOSFET with Integrated Isolated NMOS;Shaohong Li, et al.;《 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)》;20190711;全文 * |
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