CN114784108B - Planar gate SiC MOSFET integrated with junction barrier Schottky diode and manufacturing method thereof - Google Patents
Planar gate SiC MOSFET integrated with junction barrier Schottky diode and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention belongs to the technical field of power semiconductor devices, and relates to a planar gate SiC MOSFET integrated with a junction barrier Schottky diode and a manufacturing method thereof. According to the invention, by integrating the JBS diode in the three-dimensional y direction of the SiC MOSFET, the problems of overlarge forward turn-on voltage drop, overlong reverse recovery time and the like of the parasitic body diode can be effectively solved while the cell width of the SiC MOSFET is not increased, and compared with an internal integrated SBD, the integrated JBS diode has smaller reverse leakage current. The method for integrating the JBS diode does not need to additionally increase the area of the active region, has higher integration level and does not increase the width of the JFET region. Meanwhile, the P-type doped regions at intervals are introduced in the y direction of the JFET region, so that the electric field distribution of the JFET region of the device and the peak electric field in the oxide layer can be improved when the device is in blocking operation, a CSL layer with higher concentration can be adopted when the device is designed, the forward conduction characteristic of the device is improved while the reverse blocking characteristic of the device is not reduced, and the resistance of the device in forward conduction is reduced.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a planar gate SiC MOSFET integrated with a junction barrier Schottky diode and a manufacturing method thereof.
Background
Power semiconductor devices have been used as a core element in power electronics systems, and have been an essential electronic element for production and life since the invention in the last 70 th century. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structures were developed in the mid-70 s of the 20 th century, which have greatly improved performance compared to bipolar transistor BJTs, and the main problems of bipolar transistor structures are low current gain in high voltage applications and the inability of power bipolar transistors to operate at high frequencies due to the long charge storage times of minority carrier injection in the drift region. In inductive load applications, the hard switching process can lead to destructive failure. In the aspect of device application, the voltage control device is used for replacing current control, so that the problem can be avoided, the MOSFET gate structure is high in input impedance, simple to drive, excellent in switching performance in the high-frequency field and capable of bearing high voltage and large current, and therefore the MOSFET gate structure is developed into one of core electronic components in a modern power electronic circuit, is widely applied to various fields of traffic, communication, household appliances and aerospace, and the performance of a power electronic system is greatly improved by the application of the MOSFET.
Silicon power devices have been significantly improved over the past few decades, however, these devices are approaching the performance limits defined by the basic material properties of silicon, with further improvement being achieved only by migration to more powerful semiconductor materials, silicon carbide (SiC) being a wide bandgap semiconductor material with excellent physical and electrical properties suitable as a substrate material for high voltage, low loss power devices. The application of the SiC material in the power MOSFET device can necessarily further improve various performances, and the device plays a larger role in practical application.
In recent years, siC MOSFETs have been successfully commercialized and exhibit excellent performance, which in some applications has been comparable to Si-based IGBTs, but there is still room for optimization in some critical parameters, in particular how to further reduce the on-resistance Rds, on, the gate-to-drain charge Qgd and gate-to-drain capacitance Cgd, thereby improving the high frequency quality factor (HF-FOM) of the device. Better device performance is achieved in performance by optimizing the threshold voltage and increasing the forward blocking voltage. Fig. 1 is a schematic diagram of a conventional planar gate SiC MOSFET half cell structure. When the SiC MOSFET is applied to an inductive load circuit, a freewheeling diode is usually connected in parallel in the circuit, when the current of the inductive load suddenly increases or decreases, abrupt voltage is generated at two ends of the load, which may possibly destroy devices or other elements, when the SiC MOSFET is used together with the freewheeling diode, the load current may change gently, so as to avoid abrupt voltage change, a certain protection effect is achieved on the devices, but due to the serious bipolar degradation phenomenon of the parasitic body diode of the SiC MOSFET, the larger voltage drop during the turn-on and the serious reverse recovery phenomenon during the turn-off, the switching loss of the devices is inevitably increased, so that the parasitic body diode of the SiC MOSFET is not suitable for being used as the freewheeling diode, therefore, a freewheeling diode is usually connected in parallel in the circuit, although the freewheeling diode avoids the parasitic body diode problem of the SiC MOSFET, the design cost is additionally increased, and the metal interconnection problem exists between the freewheeling diode and the SiC MOSFET which is connected in parallel externally, which may result in the reliability of the devices being reduced, and the capacitance and the switching loss may also be increased. Because of the above problems, attempts have been made to integrate a diode inside the SiC MOSFET to achieve this function, not only avoiding the parasitic body diode problem, but also without separately connecting a freewheeling diode outside the device, since the on-voltage drop of the Schottky Barrier Diode (SBD) is low and the reverse recovery process is very short, it is common to choose to integrate the SBD to achieve the freewheeling diode effect, but SBD has a serious problem that a relatively large reverse leakage current due to the schottky barrier drop at high reverse bias will result in a difficult-to-ignore off-state loss, so that a novel diode needs to be integrated to improve this problem.
Disclosure of Invention
The invention aims to solve the technical problems existing in the prior art and provides a planar gate SiC MOSFET integrated with a junction barrier Schottky diode and a manufacturing method thereof. According to the invention, by integrating the JBS diode in the three-dimensional y direction of the SiC MOSFET, the problems of overlarge forward turn-on voltage drop, overlong reverse recovery time and the like of the parasitic body diode can be effectively solved while the cell width of the SiC MOSFET is not increased. And the integrated JBS diode has a smaller reverse leakage current than the integrated SBD. Meanwhile, the spaced P-type doped regions are introduced in the y direction of the JFET region, so that the electric field distribution of the JFET region of the device and the peak electric field in the oxide layer can be improved when the device is in blocking operation, a carrier storage layer CSL layer with higher concentration can be adopted when the device is designed, the forward conduction characteristic of the device is improved while the reverse blocking characteristic of the device is not reduced, and the resistance of the device when the device is in forward conduction is reduced. In addition, the capacitance between the gate and the drain can be reduced by adopting a split gate structure, which improves the switching speed of the device, thereby reducing the switching loss of the device.
In order to solve the technical problems, the embodiment of the invention provides a planar gate SiC MOSFET integrated with a junction barrier schottky diode, which defines the three-dimensional direction of a device in a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, wherein the half cell structure comprises: a back drain metal 11, an N-type substrate layer 1 and an N-drift region 2 which are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, two sides of the top layer of the N-drift region 2 are respectively provided with a P-type base region 3 and a P-type region 6, the P-type base region 3 and the P-type region 6 are arranged at intervals, one side of the top layer of the P-type base region 3 is provided with an N+ source region 4 and a P+ source region 5, the sides of the N+ source region 4 and the P+ source region 5 are contacted with each other, and the P+ source region 5 is arranged close to the side of the P-type base region 3; along the Y-axis direction, the top layer of the N-drift region 2 is provided with P-type regions 6 which are distributed at intervals;
along the Z-axis direction, the first portion of the n+ source region 4, the first portion of the N-drift region 2 between the P-type base region 3 and the P-type region 6 distributed along the X-axis direction, and the P-type base region 3 have a gate structure thereon, the second portion of the n+ source region 4, the portion of the P-type region 6, the second portion of the N-drift region 2 between the P-type region 6 distributed along the Y-axis direction, and the p+ source region 5 have a source metal 10 thereon, a dielectric layer 9 is disposed between the source metal 10 and the gate structure, and the source metal 10 and the n+ source region 4 and the p+ source region 5 may form ohmic contact;
along the Y-axis direction, the source metal 10 forms an ohmic contact with the P-type region 6, the N-drift region 2 between the source metal 10 and the P-type region 6 forms a schottky contact, and a junction barrier schottky diode is integrated therein. On the basis of the technical scheme, the invention can be improved as follows.
Further, the gate structure is further located on a third portion of the N-drift region 2 between the P-type base region 3 and the P-type region 6 distributed in the X-axis direction.
Further, the junction depth of the P-type region 6 is the same as the junction depth of the P-type base region 3.
Further, the junction depth of the p+ source region 5 and the P-type region 6 is the same as the junction depth of the P-type base region 3.
Further, the top layer of the N-drift region 2 further has a carrier storage layer 12, and the junction depth of the carrier storage layer 12 is greater than or less than the junction depth of the P-type base region 3.
Further, the gate structure is a split gate structure.
Further, the gate structure comprises a gate oxide layer 7 and a gate electrode 8 which are sequentially stacked from bottom to top.
Further, the gate electrode 8 is a metal gate electrode or a polysilicon gate electrode.
Further, the semiconductor material used in the device is any one or more of SiC, si, ge, gaN, diamond and gallium oxide.
Further, the source metal 10 is titanium, nickel, copper or aluminum.
In order to solve the technical problems, the embodiment of the invention provides a method for manufacturing a planar gate SiC MOSFET of an integrated junction barrier Schottky diode, which comprises the following steps:
step 1: an N-type heavily doped monocrystalline silicon carbide wafer is selected as an N-type substrate layer 1 of the device;
step 2: forming an N-drift region 2 on an N-type heavily doped monocrystalline silicon carbide wafer by adopting an epitaxial process;
step 3: forming a P-type base region 3 by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 4: forming an N+ source region 4 by adopting an oxidation self-alignment process and implanting N-type impurities for a plurality of times;
step 5: forming a P+ source region 5 and a P type region 6 by adopting a photoetching process and implanting P type impurities for a plurality of times;
step 6: forming a gate oxide layer 7 through an oxidation process, and depositing a layer of polycrystal on the gate oxide layer 7 to serve as a gate electrode 8;
step 7: etching part of the polycrystal and the gate oxide layer through an etching process to form a gate structure, and depositing a dielectric layer 9 to cover the polycrystal;
step 8: forming a source metal hole on the front side of the device through a photoetching process, and sputtering a layer of metal to serve as source metal 10;
step 9: the device is flipped over and a layer of metal is sputtered on the back as drain metal 11.
Further, the P-type base region 3 and the P-type region 6 are simultaneously formed by an ion implantation process.
The working principle of the invention is as follows: the method has the advantages that the cell width of the SiC MOSFET is not increased, meanwhile, the JBS diode is integrated in the three-dimensional y direction, the problems of overlarge forward starting voltage drop, overlong reverse recovery time and the like of the parasitic body diode of the SiC MOSFET are effectively solved, the circuit design requirement in actual use is met, the circuit design cost is reduced, and the problems of reliability reduction, capacitance and switching loss increase and the like of devices caused by metal interconnection problems are avoided.
In the inductive load circuit, when the gate voltage is greater than the threshold voltage of the device, the SiC MOSFET is in a conducting state, when the drain electrode is connected to a high potential and the source electrode is connected to a low potential, the electron current of the n+ source region 4 flows to the JFET region through the channel and spreads in the N-drift region 2, and when the SiC MOSFET is in a conducting state, the device charges the inductor in the inductive load circuit, and a certain amount of charge is stored on the inductor. When the grid voltage is smaller than the threshold voltage of the device and becomes 0, the SiC MOSFET is in an off state, the load current is required to flow through the freewheeling diode, and the freewheeling diode is forward biased at the moment. When the device is turned on again, the load current flows to the SiC MOSFET, and at the moment, the load current flowing to the JBS diode is reduced, and the reverse recovery time of the JBS diode is short, so that the influence on the switching speed of the device is small, and the switching characteristic of the SiC MOSFET is improved.
The invention has the beneficial effects that the problems of overlarge forward opening voltage drop, overlong reverse recovery time and the like of the parasitic body diode are effectively solved by integrating the JBS diode in the three-dimensional y direction of the SiC MOSFET while almost not influencing the performance of the SiC MOSFET. And the integrated JBS diode has less reverse leakage current than the internal integrated SBD.
In addition, the mode of integrating the JBS diode in the three-dimensional y direction does not need to additionally increase the area of the active region, but only forms a JBS diode in the JFET region through special layout design processing, thereby reducing the cost of the chip. Meanwhile, the design method does not need to add an extra photoetching plate and does not complicate the manufacturing process. And the integration level of the mode of integrating the JBS diode in the three-dimensional y direction is higher, the width of the JFET region is not increased, and meanwhile, good ohmic contact and Schottky contact can be formed. Meanwhile, the P-type doped regions at intervals are introduced in the y direction of the JFET region, so that the electric field distribution of the JFET region of the device and the peak electric field in the oxide layer can be improved when the device is in blocking operation, a CSL layer with higher concentration can be adopted when the device is designed, the forward conduction characteristic of the device is improved while the reverse blocking characteristic of the device is not reduced, and the resistance of the device in forward conduction is reduced. In addition, the capacitance between the gate and the drain can be reduced by adopting a split gate structure, which improves the switching speed of the device, thereby reducing the switching loss of the device.
Drawings
Fig. 1 is a schematic diagram of a half cell structure of a conventional planar gate SiC MOSFET;
fig. 2 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET integrated with a junction barrier schottky diode according to a first embodiment of the present invention;
fig. 3 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET integrated with a junction barrier schottky diode according to a second embodiment of the present invention;
fig. 4 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET integrated with a junction barrier schottky diode according to a third embodiment of the present invention;
fig. 5 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET integrated with a junction barrier schottky diode according to a fourth embodiment of the present invention;
fig. 6 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET integrated with a junction barrier schottky diode according to a fifth embodiment of the present invention;
fig. 7 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET integrated with a junction barrier schottky diode according to a sixth embodiment of the present invention;
fig. 8 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET integrated with a junction barrier schottky diode according to a seventh embodiment of the present invention;
fig. 9 is a schematic diagram of a half cell structure of a planar gate SiC MOSFET integrated with a junction barrier schottky diode according to an eighth embodiment of the present invention;
fig. 10-17 are schematic process flow diagrams of a method for fabricating a planar gate SiC MOSFET integrated with a junction barrier schottky diode according to a ninth embodiment of the present invention.
In the drawings, the list of components represented by the various numbers is as follows:
1. the semiconductor device comprises an N-type substrate layer, 2, an N-drift region, 3, a P-type base region, 4, an N+ source region, 5, a P+ source region, 6, a P-type region, 7, a gate oxide layer, 8, a gate electrode, 9, a dielectric layer, 10, source metal, 11, back drain metal, 12 and a carrier storage layer.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
As shown in fig. 2, in the planar gate SiC MOSFET of the integrated junction barrier schottky diode provided in the first embodiment of the present invention, three dimensions of the device are defined by a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, wherein the half cell structure comprises: a back drain metal 11, an N-type substrate layer 1 and an N-drift region 2 which are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, two sides of the top layer of the N-drift region 2 are respectively provided with a P-type base region 3 and a P-type region 6, the P-type base region 3 and the P-type region 6 are arranged at intervals, one side of the top layer of the P-type base region 3 is provided with an N+ source region 4 and a P+ source region 5, the sides of the N+ source region 4 and the P+ source region 5 are contacted with each other, and the P+ source region 5 is arranged close to the side of the P-type base region 3; along the Y-axis direction, the top layer of the N-drift region 2 is provided with P-type regions 6 which are distributed at intervals;
along the Z-axis direction, the first portion of the n+ source region 4, the first portion of the N-drift region 2 between the P-type base region 3 and the P-type region 6 distributed along the X-axis direction, and the P-type base region 3 have a gate structure thereon, the second portion of the n+ source region 4, the portion of the P-type region 6, the second portion of the N-drift region 2 between the P-type region 6 distributed along the Y-axis direction, and the p+ source region 5 have a source metal 10 thereon, a dielectric layer 9 is disposed between the source metal 10 and the gate structure, and the source metal 10 and the n+ source region 4 and the p+ source region 5 may form ohmic contact;
along the Y-axis direction, the source metal 10 forms an ohmic contact with the P-type region 6, the N-drift region 2 between the source metal 10 and the P-type region 6 forms a schottky contact, and a junction barrier schottky diode is integrated therein.
In the above embodiment, siC is selected as the semiconductor material used for the device. In addition, the semiconductor material used in the device may be any one or more of SiC, si, ge, gaN, diamond and gallium oxide.
As shown in fig. 3, a planar gate SiC MOSFET of an integrated junction barrier schottky diode according to a second embodiment of the present invention is based on the first embodiment, so that the junction depth of the P-type region 6 is the same as the junction depth of the P-type base region 3.
In the above embodiment, since the junction depths of the P-type base region 3 and the P-type region 6 are the same, the junction depth of the P-type region 6 will become deeper, thereby improving the forward blocking capability of the device.
As shown in fig. 4, a planar gate SiC MOSFET of an integrated junction barrier schottky diode according to a third embodiment of the present invention is provided, on the basis of the first embodiment, such that the gate structure is further located on a third portion of the N-drift region 2 between the P-type base region 3 and the P-type region 6 distributed along the X-axis direction.
In the above embodiment, the area of the schottky contact formed by the source metal 10 and the N-drift region 2 is larger, which further optimizes part of the characteristics of the JBS diode and improves the performance of the SiC MOSFET.
As shown in fig. 5, a planar gate SiC MOSFET of an integrated junction barrier schottky diode according to a fourth embodiment of the present invention is based on the second embodiment, such that the gate structure is further located on a third portion of the N-drift region 2 between the P-type base region 3 and the P-type region 6 distributed along the X-axis direction.
As shown in fig. 6, a planar gate SiC MOSFET of an integrated junction barrier schottky diode according to a fifth embodiment of the present invention is based on the first embodiment, so that the junction depth of the p+ source region 5 and the P-type region 6 is the same as the junction depth of the P-type base region 3.
As shown in fig. 7, a planar gate SiC MOSFET of an integrated junction barrier schottky diode according to a sixth embodiment of the present invention is based on the fifth embodiment, such that the gate structure is further located on a third portion of the N-drift region 2 between the P-type base region 3 and the P-type region 6 distributed along the X-axis direction.
As shown in fig. 8, in the planar gate SiC MOSFET of the integrated junction barrier schottky diode according to the seventh embodiment of the present invention, on the basis of the first embodiment, the top layer of the N-drift region 2 further has a carrier storage layer 12, and the junction depth of the carrier storage layer 12 is greater than or less than the junction depth of the P-type base region 3.
In the above embodiment, since a CSL layer 12 having a higher doping concentration than the N-drift region 2 is formed, this will reduce the on-resistance of the SiC MOSFET, further optimizing the forward on-characteristics of the SiC MOSFET.
As shown in fig. 9, a planar gate SiC MOSFET of an integrated junction barrier schottky diode according to an eighth embodiment of the present invention is based on the seventh embodiment, such that the gate structure is further located on a third portion of the N-drift region 2 between the P-type base region 3 and the P-type region 6 distributed along the X-axis direction.
Optionally, the gate structure is a split gate structure.
Alternatively, the gate structure includes a gate oxide layer 7 and a gate electrode 8 which are sequentially stacked from bottom to top.
As shown in fig. 10-17, a method for manufacturing a planar gate SiC MOSFET of an integrated junction barrier schottky diode according to a ninth embodiment of the present invention includes the following steps:
step 1: an N-type heavily doped monocrystalline silicon carbide wafer with a certain thickness is selected as an N-type substrate layer 1 of the device;
step 2: forming an N-drift region 2 on an N-type heavily doped monocrystalline silicon carbide wafer with a certain thickness through an epitaxial process;
step 3: depositing a SiO2 film by PECVD at low temperature; depositing a layer of polycrystal by LPCVD at high temperature, wherein the thickness of the polycrystal is larger than that of the SiO2 film as a mask during ion implantation;
step 4: an ion implantation window of the P-type base region 3 is formed through a photoetching process, and the P-type base region 3 is formed through multiple times of ion implantation of P-type impurities under certain target temperature and different energy and dosage, as shown in fig. 10;
step 5: determining an ion implantation window of the N+ source region 4 through an oxidation self-alignment process at a certain temperature;
step 6: n+ source region 4 is formed by ion implantation of N-type impurities multiple times at a certain target temperature and at different energies and dosages, as shown in fig. 11;
step 7: depositing a SiO2 film by PECVD at low temperature; depositing a layer of polycrystal by LPCVD at high temperature, wherein the thickness of the polycrystal is larger than that of the SiO2 film as a mask during ion implantation;
step 8: ion implantation windows of the P+ source region 5 and the P type region 6 are formed through photoetching technology, and P type impurities are implanted for a plurality of times to form the P+ source region 5 and the P type region 6 under certain target temperature and different energy and dosage, as shown in figure 12;
step 9: sputtering a carbon film on the surface of the wafer, and carrying out high-temperature annealing on the wafer under certain conditions;
step 10: forming a gate oxide layer 7 by an oxidation process at a high temperature as shown in fig. 13, and depositing a layer of polycrystal as a gate electrode 8 on the gate oxide layer as shown in fig. 14;
step 11: etching part of the polycrystal and the gate oxide layer by an etching process to form a gate structure, and depositing a dielectric layer 9 to cover the polycrystal as shown in fig. 15;
step 12: etching a source metal hole on the front surface of the wafer through a photoetching process, and sputtering a layer of metal as source metal 10, as shown in fig. 16;
step 13: the wafer is turned over and a layer of metal is sputtered on the back as drain metal 11, as shown in fig. 17.
The tenth embodiment of the invention provides a method for manufacturing a planar gate SiC MOSFET of an integrated junction barrier schottky diode, which comprises steps 1-3 and 5-7, wherein steps 9-13 are the same as those of embodiment 1, and the steps are as follows:
step 4: ion implantation windows of the P-type base region 3 and the P-type region 6 are formed through photoetching technology, and P-type impurities are implanted for a plurality of times to form the P-type base region 3 and the P-type region 6 under certain target temperature and different energy and dosage;
step 8: an ion implantation window of the P+ source region 5 is formed through a photoetching process, and the P+ source region 5 is formed through multiple times of ion implantation of P-type impurities under certain target temperature and different energy and dosage.
In the above embodiment, the P-type base region 3 and the P-type region 6 are formed simultaneously by an ion implantation process.
Optionally, the method further comprises the following steps: at a certain target temperature, different energies and doses, a Carrier Storage Layer (CSL) layer 11 is formed on the top layer of the N-drift region 2 by ion implantation of N-type impurities for a plurality of times.
The method for manufacturing the planar gate SiC MOSFET of the integrated junction barrier schottky diode according to the eleventh embodiment of the present invention includes the steps 1 to 10, the step 13 being the same as the step 1, and the different steps being:
step 11: etching part of the polycrystal and the gate oxide layer by an etching process, wherein the etching region comprises part of the polycrystal and the gate oxide layer on the N-drift region 2 at the JFET, and a dielectric layer 9 is deposited to cover the polycrystal;
step 12: source metal holes are etched in the front side of the wafer by a photolithographic process, the locations of which include a partial region on the N-drift region 2 at the JFET, and a layer of metal is sputtered as source metal 10, as shown in fig. 4.
The invention can integrate the JBS diode in the device while hardly affecting the performance of the SiC MOSFET, meets the circuit design requirement in actual use, reduces the circuit design cost, and avoids the problems of reduced reliability, increased capacitance and switching loss of the device caused by the problem of metal interconnection.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (9)
1. A planar gate SiC MOSFET integrated with a junction barrier Schottky diode defines the three-dimensional direction of a device in a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, wherein the half cell structure comprises: a back drain metal (11), an N-type substrate layer (1) and an N-drift region (2) are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, two sides of the top layer of the N-drift region (2) are respectively provided with a P-type base region (3) and a P-type region (6), the P-type base region (3) and the P-type region (6) are arranged at intervals, one side of the top layer of the P-type base region (3) is provided with an N+ source region (4) and a P+ source region (5) with side surfaces in contact with each other, and the P+ source region (5) is arranged close to the side surfaces of the P-type base region (3); the top layer of the N-drift region (2) is provided with P-type regions (6) distributed at intervals along the Y-axis direction;
a first part of the N+ source region (4), a first part of the N-drift region (2) between the P-type base region (3) and the P-type region (6) distributed along the X-axis direction and the P-type base region (3) are provided with a grid structure, a second part of the N+ source region (4), a part of the P-type region (6), a second part of the N-drift region (2) between the P-type region (6) distributed along the Y-axis direction and the P+ source region (5) are provided with source metal (10), a dielectric layer (9) is arranged between the source metal (10) and the grid structure, and the source metal (10) forms ohmic contact with the N+ source region (4) and the P+ source region (5);
along the Y-axis direction, the source metal (10) forms ohmic contact with the P-type region (6), the N-drift region (2) between the source metal (10) and the P-type region (6) forms Schottky contact, and a junction barrier Schottky diode is integrated in the source metal.
2. A planar gate SiC MOSFET integrated with a junction barrier schottky diode according to claim 1, characterized in that said gate structure is also located on a third portion of the N-drift region (2) between said P-type base region (3) and P-type region (6) distributed along the X-axis direction.
3. A planar gate SiC MOSFET integrated with a junction barrier schottky diode according to claim 1 or claim 2, characterized in that the junction depth of said P-type region (6) is the same as the junction depth of said P-type base region (3).
4. A planar gate SiC MOSFET integrated with a junction barrier schottky diode according to claim 1 or claim 2, characterized in that the junction depth of said p+ source region (5) and said P-type region (6) is the same as the junction depth of said P-type base region (3).
5. A planar gate SiC MOSFET integrated with a junction barrier schottky diode according to claim 1 or claim 2, characterized in that the top layer of said N-drift region (2) further has a carrier storage layer (12), said carrier storage layer (12) having a junction depth greater or less than the junction depth of said P-type base region (3).
6. A planar gate SiC MOSFET integrated with a junction barrier schottky diode according to claim 1 or claim 2, characterized in that said gate structure is a split gate structure.
7. A planar gate SiC MOSFET integrated with a junction barrier schottky diode according to claim 1 or claim 2, characterized in that the gate structure comprises a gate oxide layer (7) and a gate electrode (8) arranged in sequence from bottom to top.
8. A method of fabricating a planar gate SiC MOSFET of an integrated junction barrier schottky diode according to any of claims 1-7, comprising the steps of:
step 1: an N-type heavily doped monocrystalline silicon carbide wafer is selected as an N-type substrate layer (1) of the device;
step 2: an epitaxial process is adopted to form an N-drift region (2) on the N-type heavily doped monocrystalline silicon carbide piece;
step 3: forming a P-type base region (3) by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 4: forming an N+ source region (4) by adopting an oxidation self-alignment process and implanting N-type impurities for a plurality of times;
step 5: forming a P+ source region (5) and a P-type region (6) by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 6: forming a gate oxide layer (7) through an oxidation process, and depositing a layer of polycrystal on the gate oxide layer (7) to serve as a gate electrode (8);
step 7: etching part of the polycrystal and the gate oxide layer through an etching process to form a gate structure, and depositing a dielectric layer (9) to cover the polycrystal;
step 8: forming a source metal hole on the front side of the device through a photoetching process, and sputtering a layer of metal as source metal (10);
step 9: the device is turned over and a layer of metal is sputtered on the back as drain metal (11).
9. The method for manufacturing the planar gate SiC MOSFET of the integrated junction barrier schottky diode according to claim 8, wherein the P-type base region (3) and the P-type region (6) are formed simultaneously by an ion implantation process.
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