CN116130480A - Metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents
Metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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Abstract
The invention provides a metal oxide semiconductor field effect transistor and a manufacturing method thereof, wherein the transistor improves the bipolar degradation phenomenon of silicon carbide, improves the reliability of a chip and reduces the packaging cost of a module by integrating a Schottky barrier diode in a JFET region; the Schottky barrier diode with the groove structure effectively protects the JFET region electric field of the metal oxide semiconductor field effect transistor and the Schottky contact electric field of the Schottky barrier diode, and improves the blocking capacity of the metal oxide semiconductor field effect transistor; the groove type source electrode structure increases the contact area of the source hole in three-dimensional space, reduces the influence of the source contact resistance on the whole resistance of the device, and is beneficial to the output of larger current capacity.
Description
Technical Field
The present invention relates to the field of semiconductor device manufacturing technology, and in particular, to a metal oxide semiconductor field effect transistor and a method for manufacturing the same.
Background
The SiC MOSFET (SiC Metal-Oxide-Semiconductor Field-Effect Transistor) has the characteristics of low on-resistance, high switching speed, high temperature resistance and the like, and has great application advantages in the fields of high-voltage frequency conversion, new energy automobiles, rail transit and the like. To improve the current capability of SiC MOSFETs, the current flow area is often increased by compressing the cell size, improving the current capability. When the cell size is continuously compressed, the contact area of the source electrode hole is reduced, and the source electrode contact resistance is greatly increased, so that the reduction of the whole resistance of the device is not facilitated.
Meanwhile, in the application scenes of motor driving, traction inversion and the like, the traditional method is to connect a Schottky diode in parallel outside a SiC MOSFET, and the reverse freewheeling capacity is realized by utilizing the low conduction voltage drop of the external anti-parallel diode. But for the module, the packaging area is increased, and the current passing capability of the whole device module is reduced. The other way is to use the body diode integrated inside the SiC MOSFET to perform the freewheel function during reverse conduction. But since the body diode is a PIN structure device, a high turn-on voltage drop and reverse recovery loss are generated. Meanwhile, the conduction of the SiC bipolar device can induce electron-hole recombination, so that the stacking layer in the body is expanded, the voltage drop of the device is increased, the reverse bias leakage current is increased, and the reliability of the silicon carbide device is not facilitated.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a mosfet and a method for manufacturing the same.
A metal oxide semiconductor field effect transistor comprising: the semiconductor device comprises an N+ substrate layer, an N-drift layer, a P well layer, a first P+ deep well region, a second P+ deep well region, an N+ source region, a source metal layer, an ohmic contact layer and a Schottky contact layer;
the transistor is provided with a JFET region, and the N-drift layer is provided with a JFET groove in the JFET region;
the N-drift layer is arranged on the N+ substrate layer, the P well layer is arranged on the N-drift layer, the N+ source region is arranged on the P well layer, and the P well layer and the N+ source region are respectively arranged on two sides of the JFET groove;
source grooves are formed in two sides of the P well layer and the N+ source region respectively, the first P+ deep well region is arranged at the bottom of the source groove, and the second P+ deep well region is arranged at the bottom of the JFET groove;
the first P+ deep well region is connected with the source metal layer through an ohmic contact layer, the second P+ deep well region is connected with the source metal layer through an ohmic contact layer, at least part of the source metal layer is arranged in the JFET groove, and the source metal layer is connected with the bottom and the side wall of the JFET groove through the Schottky contact layer.
In one embodiment, the schottky contact layer is disposed on a sidewall of the JFET channel, and at least a portion of the schottky contact layer is disposed on a bottom of the JFET channel.
In one embodiment, at least a portion of the schottky contact layer extends from the side walls of the JFET channel to the outside of the JFET channel and is disposed on the N-drift layer.
In one embodiment, the number of the second p+ deep well regions in the JFET region is two, and the schottky contact layer disposed at the bottom of the JFET channel is located between the two second p+ deep well regions.
In one embodiment, the number of the second p+ deep well regions within the JFET region is one, and the width of the JFET channel is equal to the width of the second p+ deep well region.
In one embodiment, the semiconductor device further comprises an interlayer dielectric layer and gate polysilicon, wherein the interlayer dielectric layer is arranged on the N+ source electrode region, and the interlayer dielectric layer is coated on the outer side of the gate polysilicon.
In one embodiment, the semiconductor device further comprises a drain metal layer, and the N+ substrate layer is arranged on the drain metal layer.
A metal oxide semiconductor field effect transistor comprising:
manufacturing an N+ substrate layer;
manufacturing an N-drift layer on the N+ substrate layer;
manufacturing a P well layer on the N-drift layer;
manufacturing an N+ source electrode region on the P well layer;
etching a source electrode groove and a JFET groove on the N-drift layer, wherein the source electrode groove is positioned on two sides of the P well layer and the N+ source electrode area, the JFET groove is arranged in the JFET area, and the P well layer and the N+ source electrode area are respectively arranged on two sides of the JFET groove;
forming a first P+ deep well region at the bottom of the source electrode groove, and forming a second P+ deep well region at the bottom of the JFET groove;
manufacturing a Schottky contact layer in the JFET groove;
an ohmic contact layer is manufactured in the JFET groove and the source electrode groove;
and manufacturing a source metal layer in the JFET groove and the source groove.
In one embodiment, the step of fabricating a schottky contact layer in the JFET channel includes:
and manufacturing a Schottky contact layer in the JFET groove and at the outer side of the JFET groove, so that at least part of the Schottky contact layer extends to the outer side of the JFET groove from the side wall of the JFET groove and is arranged on the N-drift layer.
In one embodiment, the number of the second p+ deep well regions within the JFET region is one, and the width of the JFET channel is equal to the width of the second p+ deep well region.
According to the metal oxide semiconductor field effect transistor and the manufacturing method thereof, the Schottky barrier diode is integrated in the structure, so that the bipolar degradation phenomenon of silicon carbide is improved, the reliability of a chip is improved, and the packaging cost of a module is reduced; the Schottky barrier diode with the groove structure effectively protects the JFET region electric field of the metal oxide semiconductor field effect transistor and the Schottky contact electric field of the Schottky barrier diode, and improves the blocking capacity of the metal oxide semiconductor field effect transistor; the groove type source electrode structure increases the contact area of the source hole in three-dimensional space, reduces the influence of the source contact resistance on the whole resistance of the device, and is beneficial to the output of larger current capacity.
Drawings
FIG. 1 is a schematic diagram of a metal oxide semiconductor field effect transistor according to an embodiment;
FIG. 2 is a schematic diagram of a MOSFET in another embodiment;
FIG. 3 is a schematic diagram of a structure of a MOSFET in yet another embodiment;
FIG. 4 is a flow chart of a method of manufacturing a MOSFET in one embodiment;
FIGS. 5A-5G are schematic diagrams illustrating the structure of a MOSFET at various steps in the fabrication process according to one embodiment;
fig. 6 is a schematic diagram of a plan top view structure of a mosfet in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
Example 1
In this embodiment, as shown in fig. 1 and 6, there is provided a metal oxide semiconductor field effect transistor including: a drain metal layer 110, an n+ substrate layer 120, an N-drift layer 130, a P-well layer 140, a first p+ deep well region 210, a second p+ deep well region 220, an n+ source region 230, a source metal layer 240, an ohmic contact layer 250, and a schottky contact layer 260; the transistor has a JFET region 310, and the N-drift layer 130 is provided with a JFET groove 301 in the JFET region 310; the n+ substrate layer 120 is disposed on the drain metal layer 110, the N-drift layer 130 is disposed on the n+ substrate layer 120, the P-well layer 140 is disposed on the N-drift layer 130, the n+ source region 230 is disposed on the P-well layer 140, and the P-well layer 140 and the n+ source region 230 are disposed on two sides of the JFET channel 301, respectively; source trenches 201 are further disposed on two sides of the P-well layer 140 and the n+ source region 230, the first p+ deep well region 210 is disposed at the bottom of the source trench 201, and the second p+ deep well region 220 is disposed at the bottom of the JFET trench 301; the first p+ deep well region 210 is connected to the source metal layer 240 through an ohmic contact layer 250, the second p+ deep well region 220 is connected to the source metal layer 240 through an ohmic contact layer 250, at least a portion of the source metal layer 240 is disposed in the JFET channel 301, and the source metal layer 240 is connected to the bottom and the sidewall of the JFET channel 301 through the schottky contact layer 260.
In this embodiment, the metal oxide semiconductor field effect transistor is a SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor).
By opening the JFET (Junction Field-Effect Transistor) region with the JFET channel 301, the source metal layer 240 can be located in the JFET channel 301 and connected to the second p+ deep well region 220 through the ohmic contact layer 250, and the source metal layer 240 is connected to the bottom and the sidewall of the JFET channel 301 through the schottky contact layer 260, so as to form a silicon carbide schottky barrier diode (SiC SBD), which effectively utilizes the area of the JFET region 310 and has a higher cell integration level. The integrated Schottky barrier diode is of a groove structure, so that the JFET region 310 electric field of the SiC MOSFET and the SiC SBD Schottky contact electric field are effectively protected, and the blocking capacity of the SiC MOSFET device is improved; the integrated SiC SBD is a trench structure, and is integrated in three dimensions on the sidewall of the portion of the trench JFET region 310, which enlarges the flow area of the schottky contact and reduces the conduction voltage drop of the body two tubes.
In addition, the source part of the SiC MOSFET is of a groove-shaped structure design, the groove-shaped side wall of the source hole is used for increasing the source contact surface, so that the through-flow path of electrons entering and exiting the source is increased, the source contact resistance is reduced, and the through-flow capacity of the device is improved; the source part of the SiC MOSFET is designed into a groove structure, and P+ deep well injection is formed by utilizing the groove structure, so that the short circuit with the source region N+ is better realized, and the inhibition effect on the parasitic NPN transistor is enhanced; the groove structure of the JFET region 310, the groove structure of the source region and the P+ deep well are formed by adopting a synchronous procedure, and the P+ junction depth has consistent adjustability, so that synchronous compromise optimization of an internal body diode electric field and an SBD electric field is facilitated; the manufacturing method of the SiC MOSFET cell channel adopts a channel self-alignment forming mode, so that the channel length is greatly reduced, and the current output capacity of the device is improved.
In one embodiment, referring to fig. 1 again, the mosfet further includes an interlayer dielectric layer 150 and a gate polysilicon 160, the interlayer dielectric layer 150 is disposed on the n+ source region 230, the interlayer dielectric layer 150 wraps the outer sides of the gate polysilicon 160, and the number of the gate polysilicon 160 is two, and the two gate polysilicon 160 are disposed at intervals.
In the embodiment, the SiC MOSFET gate polysilicon adopts a split gate structure mode, so that the gate capacitance and the input capacitance are effectively reduced, and the switching characteristic of the device is improved.
In one embodiment, referring again to fig. 1, the number of the second p+ deep well regions 220 in the JFET region 310 is two, and the schottky contact layer 260 disposed at the bottom of the JFET channel 301 is located between the two second p+ deep well regions 220.
In one embodiment, the schottky contact layer 260 is disposed on a sidewall of the JFET channel 301, and at least a portion of the schottky contact layer 260 is disposed on a bottom of the JFET channel 301.
Example two
In this embodiment, as shown in fig. 2, at least a portion of the schottky contact layer 260 extends from the sidewall of the JFET channel 301 to the outside of the JFET channel 301 and is disposed on the N-drift layer 130.
In this embodiment, the schottky contact layer 260 of the JFET region 310 is formed on the top region of the JFET trench 301 except for the trench sidewall, so that the area of the integrated SiC SBD can be increased and the turn-on capability can be improved.
Example III
In one embodiment, as shown in fig. 3, the number of the second p+ deep well regions 220 in the JFET region 310 is one, and the width of the JFET channel 301 is equal to the width of the second p+ deep well region 220.
In this embodiment, the trench SBD diode integrated in the middle portion of the JFET region 310 may remain as 1 p+ deep well region. The flow area of the Schottky barrier diode can be adjusted by adjusting the area and the quantity of P+ injection.
Example IV
In this embodiment, as shown in fig. 4, there is provided a mosfet including:
In this embodiment, by opening the JFET (Junction Field-Effect Transistor) region with the JFET channel 301, the source metal layer 240 can be located in the JFET channel 301 and connected to the second p+ deep well region 220 through the ohmic contact layer 250, and the source metal layer 240 is connected to the bottom and the sidewall of the JFET channel 301 through the schottky contact layer 260, so as to form a silicon carbide schottky barrier diode (SiC SBD), which effectively uses the area of the JFET region 310 and has a higher cell integration level. The integrated Schottky barrier diode is of a groove structure, so that the JFET region 310 electric field of the SiC MOSFET and the SiC SBD Schottky contact electric field are effectively protected, and the blocking capacity of the SiC MOSFET device is improved; the integrated SiC SBD is a trench structure, and is integrated in three dimensions on the sidewall of the portion of the trench JFET region 310, which enlarges the flow area of the schottky contact and reduces the conduction voltage drop of the body two tubes.
In addition, the source part of the SiC MOSFET is of a groove-shaped structure design, the groove-shaped side wall of the source hole is used for increasing the source contact surface, so that the through-flow path of electrons entering and exiting the source is increased, the source contact resistance is reduced, and the through-flow capacity of the device is improved; the source part of the SiC MOSFET is designed into a groove structure, and P+ deep well injection is formed by utilizing the groove structure, so that the short circuit with the source region N+ is better realized, and the inhibition effect on the parasitic NPN transistor is enhanced; the groove structure of the JFET region 310, the groove structure of the source region and the P+ deep well are formed by adopting a synchronous procedure, and the P+ junction depth has consistent adjustability, so that synchronous compromise optimization of an internal body diode electric field and an SBD electric field is facilitated; the manufacturing method of the SiC MOSFET cell channel adopts a channel self-alignment forming mode, so that the channel length is greatly reduced, and the current output capacity of the device is improved.
In addition, the trench structure of the JFET region 310 and the trench structure of the source region, and the first p+ deep well region 210 and the second p+ deep well region 220 are formed by using a synchronous process, and the p+ junction depth has consistent adjustability, which is beneficial to synchronously compromising and optimizing the internal body diode electric field and the SBD electric field.
In one embodiment, the step of fabricating the schottky contact layer 260 in the JFET channel 301 includes: as shown in fig. 2, a schottky contact layer 260 is formed in the JFET trench 301 and outside the JFET trench 301 such that at least a portion of the schottky contact layer 260 extends from the sidewalls of the JFET trench 301 to the outside of the JFET trench 301 and is disposed on the N-drift layer 130.
In this embodiment, the schottky contact layer 260 of the JFET region 310 is formed on the top region of the JFET trench 301 except for the trench sidewall, so that the area of the integrated SiC SBD can be increased and the turn-on capability can be improved.
In one embodiment, as shown in fig. 3, the number of the second p+ deep well regions 220 in the JFET region 310 is one, and the width of the JFET channel 301 is equal to the width of the second p+ deep well region 220.
In this embodiment, the trench SBD diode integrated in the middle portion of the JFET region 310 may remain as 1 p+ deep well region. The flow area of the Schottky barrier diode can be adjusted by adjusting the area and the quantity of P+ injection.
Example five
In this embodiment, a silicon carbide MOSFET is provided, taking an N-channel MOSFET as an example, on the basis of a conventional structure, by integrating SBD in a cell area of the MOSFET, the utilization area of an active area of a chip is increased, thereby increasing the power density of the chip; the electric field in the cell body is balanced better by utilizing the design of the groove type JBS structure and the source electrode structure, and the area integration utilization in the three-dimensional space is realized.
The specific process flow is as follows:
step one, as shown in FIG. 5A, preparing a SiC epitaxial wafer comprising an N+ substrate layer 120 having a doping concentration of 1E18cm < -3 > to 1E19cm < -3 >, and forming an N-drift layer 130 over the N+ substrate layer 120, wherein the N-drift layer 130 has a concentration of about 1E14 cm -3 ～5E16cm -3 In particular, it is necessary to optimize the chip withstand voltage.
Step two, as shown in fig. 5A, an oxide layer of 1.5 μm to 3.0 μm is deposited on top of the SiC epitaxial wafer, a P-well implantation window is formed by photolithography-etching, and a cellular P-well layer 140 is formed by Al ion implantation using the oxide layer as an ion implantation mask, and the junction depth of the P-well is 1.0 μm to 1.5 μm.
And step three, as shown in fig. 5B, depositing silicon oxide again, and reversely etching to form the silicon oxide side wall. N ion implantation is performed to form an N+ source region 230 by using the side wall of the secondary silicon oxide as an ion implantation mask, wherein the N+ junction depth is 0.3-0.4 mu m. And the silicon oxide side wall is utilized to realize an accurate and controllable self-aligned channel with the thickness of 0.25-0.8 mu m according to actual needs.
Step four, as shown in fig. 5C, depositing an oxide layer of 1.0 μm to 2.0 μm, forming a source trench 201 and a JFET trench 301 etching window by photolithography-etching, etching SiC medium by using the oxide layer as a barrier layer, and forming a structure region with a groove on the surface of the N-drift region, wherein the junction depth of the groove is 0.25 μm to 0.35 μm.
Step five, as shown in fig. 5D, performing a second oxide deposition-photolithography-etching on the JFET channel 301, wherein the intermediate region of the JFET region 310 is covered by the second oxide layer, so as to form an implantation barrier. Al ion implantation is carried out on the wafer to form a cellular region, and the P+ junction depth is 1.0-1.6 mu m.
And step six, removing all dielectric layers on the SiC epitaxial layer, and performing an activation annealing process on the SiC wafer for 10-40 min at 1700-1800 ℃ to activate implanted ions.
Step seven, as shown in fig. 5E, gate oxide oxidation, polysilicon deposition and patterning form gate polysilicon 160, i.e., the gate electrode. An interlayer dielectric layer 150 is deposited and the openings are etched.
And step eight, as shown in fig. 5E and 5F, depositing a thin layer of silicon nitride with a thickness of 0.5-1.0 μm on the wafer, and performing coverage protection on the non-ohmic alloy region in the trench JFET structure by photoetching.
Step nine, as shown in fig. 5G, ni/Ti/Al metal is deposited on the front surface, and annealed at 900-1000 ℃ for 2-5 min, forming an ohmic alloy layer to SiC in the source region and JFET region 310, forming an ohmic contact layer 250. By performing corrosion removal on the nitride, depositing Ti or Mo metal again, and annealing for 5-10 min at 400-600 ℃ to form a Schottky contact layer 260 on SiC in the JFET region 310.
Step ten, referring to fig. 1, depositing Ni metal on the back of the wafer, and annealing at 900-1000 ℃ for 2-5 min to form a back drain electrode, thereby forming a drain metal layer 110. And thickening Al metal on the front surface to lead out a source electrode and a gate electrode. To this end, siC MOSFETs integrating the trench SiC SBD structure and the source structure are formed.
In the embodiment, the SiC SBD is integrated in the SiC MOSFET cell, and is used as a freewheeling diode in reverse bias to inhibit the opening of the body diode, so that the reliability of long-term operation of the chip is improved; when the SBD structure is integrated in the MOSFET cell structure, the SBD part and the MOSFET part can share part of the areas of the active area and the terminal area, so that the overall power density of the chip is greatly improved, and meanwhile, the packaging cost of the module is reduced; the contact area of the source hole is increased in a three-dimensional space by utilizing the groove type source electrode structure, the influence of the source contact resistance on the whole resistance of the device is reduced, and the output of larger current capacity is facilitated.
The SiC SBD is integrated in the SiC MOSFET in the embodiment, so that the bipolar degradation phenomenon of silicon carbide is improved, the reliability of a chip is improved, and the packaging cost of a module is reduced; the groove type SiC SBD structure effectively protects the JFET region electric field and the SiC SBD Schottky contact electric field of the SiC MOSFET, and improves the blocking capacity of the SiC MOSFET device; the groove type source electrode structure increases the contact area of the source hole in three-dimensional space, reduces the influence of the source contact resistance on the whole resistance of the device, and is beneficial to the output of larger current capacity.
The integrated SiC SBD is arranged at the JFET region, so that the JFET region area is effectively utilized, and the cell integration level is higher; the integrated SiC SBD is of a groove structure, so that the JFET region electric field of the SiC MOSFET and the SiC SBD Schottky contact electric field are effectively protected, and the blocking capacity of the SiC MOSFET device is improved; the integrated SiC SBD is of a groove type structure, and is integrated in the three-dimensional direction on the side wall of the groove type JFET region, so that the flow area of Schottky contact is enlarged, and the conduction voltage drop of the body two tubes is reduced; the SiC MOSFET gate polysilicon adopts a split gate structure mode, so that the gate capacitance and the input capacitance are effectively reduced, and the switching characteristic of the device is improved; the source part of the SiC MOSFET is of a groove-shaped structure design, the groove-shaped side wall of the source hole is used for increasing the source contact surface, so that the through-flow path of electrons entering and exiting the source is increased, the source contact resistance is reduced, and the through-flow capacity of the device is improved; the source part of the SiC MOSFET is designed into a groove structure, and P+ deep well injection is formed by utilizing the groove structure, so that the short circuit with the source region N+ is better realized, and the inhibition effect on the parasitic NPN transistor is enhanced; the groove structure of the JFET region, the groove structure of the source region and the P+ deep well are formed by adopting a synchronous procedure, and the P+ junction depth has consistent adjustability, so that synchronous compromise optimization of an internal body diode electric field and an SBD electric field is facilitated; the manufacturing method of the SiC MOSFET cell channel adopts a channel self-alignment forming mode, so that the channel length is greatly reduced, and the current output capacity of the device is improved.
The metal oxide semiconductor field effect transistor has the following advantages:
1. the source electrode is designed in a groove shape, so that the contact area of the source electrode is increased in the three-dimensional direction, the electronic current path is increased, and the contact resistance is reduced;
2. SBD integration is carried out on MOSFET cells, so that bipolar degradation effect of the silicon carbide MOSFET is improved, and reliability of the chip is improved;
3. the integrated SBD structure is of a groove type design, so that the shielding effect on the Schottky surface electric field and the JFET region surface electric field is enhanced, and the breakdown capacity of the device is enhanced;
5. the design of the groove-shaped source electrode can promote the injection junction depth of P+ and better realize the short circuit with the N+ of the source region, thereby enhancing the inhibition effect on the parasitic NPN transistor;
6. the structural mode of the split gate effectively reduces the gate capacitance and the input capacitance and improves the switching characteristic of the device.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A metal oxide semiconductor field effect transistor, comprising: the semiconductor device comprises an N+ substrate layer, an N-drift layer, a P well layer, a first P+ deep well region, a second P+ deep well region, an N+ source region, a source metal layer, an ohmic contact layer and a Schottky contact layer;
the transistor is provided with a JFET region, and the N-drift layer is provided with a JFET groove in the JFET region;
the N-drift layer is arranged on the N+ substrate layer, the P well layer is arranged on the N-drift layer, the N+ source region is arranged on the P well layer, and the P well layer and the N+ source region are respectively arranged on two sides of the JFET groove;
source grooves are formed in two sides of the P well layer and the N+ source region respectively, the first P+ deep well region is arranged at the bottom of the source groove, and the second P+ deep well region is arranged at the bottom of the JFET groove;
the first P+ deep well region is connected with the source metal layer through an ohmic contact layer, the second P+ deep well region is connected with the source metal layer through an ohmic contact layer, at least part of the source metal layer is arranged in the JFET groove, and the source metal layer is connected with the bottom and the side wall of the JFET groove through the Schottky contact layer.
2. The metal oxide semiconductor field effect transistor of claim 1, wherein the schottky contact layer is disposed on a sidewall of the JFET channel and at least a portion of the schottky contact layer is disposed on a bottom of the JFET channel.
3. The metal oxide semiconductor field effect transistor of claim 1, wherein at least a portion of the schottky contact layer extends from a sidewall of the JFET channel to an outside of the JFET channel and is disposed on the N-drift layer.
4. The metal oxide semiconductor field effect transistor of claim 1, wherein the number of the second p+ deep well regions in the JFET region is two, and the schottky contact layer disposed at the bottom of the JFET channel is located between the two second p+ deep well regions.
5. The metal oxide semiconductor field effect transistor of claim 1, wherein the number of the second p+ deep well regions within the JFET region is one and the width of the JFET channel is equal to the width of the second p+ deep well region.
6. The metal oxide semiconductor field effect transistor of claim 1, further comprising an interlayer dielectric layer and a gate polysilicon, wherein the interlayer dielectric layer is disposed on the n+ source region, and wherein the interlayer dielectric layer is wrapped around the gate polysilicon.
7. The metal oxide semiconductor field effect transistor of claim 1, further comprising a drain metal layer, the n+ substrate layer disposed on the drain metal layer.
8. A metal oxide semiconductor field effect transistor, comprising:
manufacturing an N+ substrate layer;
manufacturing an N-drift layer on the N+ substrate layer;
manufacturing a P well layer on the N-drift layer;
manufacturing an N+ source electrode region on the P well layer;
etching a source electrode groove and a JFET groove on the N-drift layer, wherein the source electrode groove is positioned on two sides of the P well layer and the N+ source electrode area, the JFET groove is arranged in the JFET area, and the P well layer and the N+ source electrode area are respectively arranged on two sides of the JFET groove;
forming a first P+ deep well region at the bottom of the source electrode groove, and forming a second P+ deep well region at the bottom of the JFET groove;
manufacturing a Schottky contact layer in the JFET groove;
an ohmic contact layer is manufactured in the JFET groove and the source electrode groove;
and manufacturing a source metal layer in the JFET groove and the source groove.
9. The method of claim 8, wherein the step of forming a schottky contact layer in the JFET channel comprises:
and manufacturing a Schottky contact layer in the JFET groove and at the outer side of the JFET groove, so that at least part of the Schottky contact layer extends to the outer side of the JFET groove from the side wall of the JFET groove and is arranged on the N-drift layer.
10. The method of claim 8, wherein the number of second p+ deep well regions in the JFET region is one and the JFET channel has a width equal to the width of the second p+ deep well regions.
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| CN116759460A (en) * | 2023-08-18 | 2023-09-15 | 深圳平创半导体有限公司 | Shielded gate trench transistor and manufacturing method thereof |
| CN116759460B (en) * | 2023-08-18 | 2024-04-05 | 深圳平创半导体有限公司 | Shielded gate trench transistor and manufacturing method thereof |
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