CN110739219B - Preparation method of SiC MOSFET (Metal-oxide-semiconductor field Effect transistor) with embedded channel diode - Google Patents
Preparation method of SiC MOSFET (Metal-oxide-semiconductor field Effect transistor) with embedded channel diode Download PDFInfo
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
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Abstract
The invention provides a preparation method of a SiC MOSFET (metal oxide semiconductor field effect transistor) embedded with a trench diode, which specifically comprises the steps of growing an N-drift layer and a JFET (junction field effect transistor) region on the upper surface of a substrate layer in sequence; forming P-base regions on two sides of the JFET region; forming an N + source region and a P-plus region in the P-base region; forming MOSFET gate oxide and thin trench diode gate oxide on the upper surfaces of the JFET region, the N + source region and the P-plus; forming a MOSFET polysilicon gate and a trench diode polysilicon gate on the upper surfaces of the MOSFET gate oxide and the trench diode gate oxide; depositing SiO on the upper surfaces of the MOSFET polysilicon gate and the trench diode polysilicon gate 2 To form isolated oxygen; and sputtering source metal on the front surface of the device and sputtering drain metal on the back surface of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a SiC MOSFET with an embedded channel diode.
Background
Breakthrough of wide bandgap semiconductor materials, represented by SiC, is expected to lead to the development of new generation power electronics. The SiC material has higher breakdown field strength, higher carrier saturation velocity and higher thermal conductivity than the Si material, so that the SiC power electronic device has the characteristics of high related power-off voltage, small on-resistance, high switching frequency, high efficiency and good high-temperature performance compared with the similar device of Si. SiC power electronic devices will become one of the important bases for the development of megawatt electronics and green energy.
As a unipolar power device, since it has advantages such as low on-resistance, high input impedance, and high switching speed, the SiC MOSFET will be an ideal high-voltage power switching device in the range of blocking voltage 3000 to 4500V, and it is completely possible to further improve the overall efficiency and switching frequency of the system instead of the Si IGBT device. The SiC MOSFET, as a third-generation semiconductor device, is a strong competitor of Si-based devices in the field of power electronics, and has the potential for application at higher temperature, higher voltage, and higher frequency due to the more excellent performance advantages of SiC materials.
In a rectifier or inverter system, a switching device in a power network often needs to be connected with a free-wheeling diode in an anti-parallel mode to alleviate the impact of voltage spike on the switching device. Currently, the following schemes are mainly selected for the freewheeling diode: 1. an external diode is adopted, but extra parasitic capacitance and inductance are brought to the system, and the loss of the system is increased; 2. the diode and the switching device are packaged integrally, but the method can increase the area of a chip additionally, thereby increasing the leakage of the device and degrading the temperature characteristic of the device. 3. The parasitic body diode of the MOSFET device itself is used as a follow current tube in reverse operation, but for the conventional SiC MOSFET, the conduction of the body diode also causes two problems: firstly, the SiC MOSFET body diode is close to 3V of starting voltage to cause extra power loss of the system; and secondly, the conduction of the body diode can induce a bipolar degradation phenomenon, which is because the recombination of electron hole pairs can cause the proliferation of SiC material defects, thereby increasing the electric leakage of the whole device and causing failure.
Disclosure of Invention
The invention provides a preparation method of a SiC MOSFET structure with an embedded channel diode, which aims to solve the problem that the traditional SiC MOSFET structure cannot use body diode freewheeling. The technical problem to be solved by the invention is realized by the following technical scheme:
a preparation method of a SiC MOSFET with an embedded channel diode comprises the following steps:
growing an N-drift layer 3 on the upper surface of the substrate layer 2;
a JFET area 4 is grown on the upper surface of the N-drift layer 3;
adopting a Ni/Au metal layer as a barrier layer on the JFET area 4, and carrying out Al ion injection with the energy of 100 keV-600 keV for 2-5 times to form a left P-base area 5 and a right P-base area 5;
SiO is adopted on the upper surfaces of the left and right P-base regions 5 and the JFET region 4 2 As a barrier layer, N ions with the energy of 10keV to 200keV are implanted for 2 to 5 times to form a left N + source area 6 and a right N + source area 6;
SiO is adopted on the upper surfaces of the left and right P-base regions 5, the left and right N + source regions 6 and the JFET region 4 2 As a barrier layer, carrying out 2-5 times of Al ion implantation with the energy of 10 keV-200 keV to form a left P-plus area 7 and a right P-plus area 7;
performing high-temperature annealing after ion implantation in an argon environment at 1200-1800 ℃, wherein the annealing time is 20-60 minutes, and activating impurity ions of a left P-base area 5, a right P-base area 5, a left N + source area 6 and a right P-plus area 7;
thermally growing SiO on the upper surfaces of the JFET area 4, the left and right P-base areas 5, the left and right N + source areas 6 and the left and right P-plus areas 7 2 And using photoresist as mask to etch SiO 2 Etching and thinning the right surface;
in SiO 2 Depositing polysilicon on the upper surface, and etching the deposited polysilicon to form a MOSFET polysilicon gate 8 and a trench diode polysilicon gate 13;
depositing SiO on the MOSFET polysilicon gate 8, the trench diode polysilicon gate 13, and all exposed upper surfaces 2 In the SiO 2 The upper surface adopts photoresist as a mask to etch SiO 2 Exposing the upper surfaces of the P-plus region 7, the N + source region 6 and part of the polysilicon gate 13 of the trench diode, and forming MOSFET gate oxide 9 positioned on the upper surfaces of the left N + source region 6, the left P-base region 5 and part of the JFET region 4, and trench diode gate oxide 12 positioned on the upper surfaces of the right N + source region 6, the right P-base region 5 and part of the JFET region 4 and having a smaller thickness;
the source metal 11 is sputtered on the front side of the device and the drain metal 1 is sputtered on the back side of the device.
Advantageous effects
The preparation method of the SiC MOSFET with the embedded channel diode provided by the invention solves the problem that the traditional SiC MOSFET structure cannot use body diode follow current, only adds a one-step gate oxide etching process compared with the preparation method of the traditional structure, has high process compatibility and controls the manufacturing cost.
Drawings
FIG. 1 is a diagram of a conventional SiC MOSFET structure;
FIG. 2 is a block diagram of a SiC MOSFET with embedded channel diodes in accordance with the present invention;
FIG. 3 is a comparison graph of simulation results of conduction curves of a conventional structure and a structure of the present invention when the device is operated in a reverse freewheeling state;
FIG. 4 shows the current I in the reverse direction SD ＝100A/cm 2 Comparing the hole concentration distribution situation in the device of the traditional structure and the structure of the invention;
FIG. 5 shows the current I in the reverse direction SD ＝100A/cm 2 Meanwhile, the longitudinal distribution diagram of the hole concentration in the traditional structure and the structure device of the invention is shown;
FIG. 6 is a graph comparing the forward conduction characteristic and the reverse breakdown characteristic of the device of the conventional structure and the structure of the present invention;
FIG. 7 shows the current I in the forward direction DS ＝100A/cm 2 Comparing the current density distribution inside the device with the traditional structure and the structure of the invention;
FIG. 8 shows the input capacitance characteristics (C) of the device of the conventional structure and the structure of the present invention ISS ) Output capacitance characteristic (C) OSS ) And transfer capacitance characteristics (C) RSS ) Comparing the simulation results with a graph;
FIG. 9 (a) is a circuit diagram showing simulation of gate charge characteristics, and FIG. 9 (b) is a comparison graph of simulation results of gate charge characteristics of a conventional structure and a structure of the present invention;
table 1 is a summary comparison of the performance parameters of the conventional structure and the structure of the present invention;
fig. 10-21 are flow charts of methods for fabricating device structures of the present invention.
Detailed Description
The principles and features of this invention are described in connection with the drawings, which are set forth as examples only and not intended to limit the scope of the invention.
In this embodiment, the terms "upper", "lower", "left" and "right" refer to the positional relationship when the MOSFET device structure is in the illustrated state, "long" refers to the lateral dimension when the MOSFET device structure is in the illustrated state, and "thick" refers to the longitudinal dimension when the MOSFET device structure is in the illustrated state.
The SiC MOSFET structure with embedded trench diodes manufactured by the present invention, as shown in fig. 2, includes:
an N-drift layer 3;
the substrate layer 2 is positioned on the lower surface of the N-drift layer 3;
the drain electrode metal 1 is positioned on the lower surface of the substrate layer 2;
a JFET region 4 located on the upper surface of the N-drift layer 3;
p-base regions 5 located on both sides of the JFET region 4;
the N + source region 6 is positioned on the upper surfaces of the preset regions of the left and right P-base regions 5;
a P-plus region 7 located on the upper surface of the preset region of the left and right P-base regions 5 and located outside the N + source region 6;
the MOSFET gate oxide 9 is positioned on the upper surfaces of the left N + source region 6, the left P-base region 5 and part of the JFET region 4;
the trench diode gate oxide 12 is positioned on the upper surfaces of the right N + source region 6, the right P-base region 5 and part of the JFET region 4, has the thickness smaller than that of the MOSFET gate oxide 9, and is adjacent to the MOSFET gate oxide 9;
the MOSFET polysilicon gate 8 is positioned on the upper surface of the MOSFET gate oxide 9;
the trench diode polysilicon gate 13 is positioned on the upper surface of the trench diode gate oxide 12 and forms a split gate structure with the MOSFET polysilicon gate 8;
the isolation oxygen 10 is positioned on the upper surfaces of the MOSFET polysilicon gate 8, the trench diode polysilicon gate 13, the exposed MOSFET gate oxide 9 and the exposed trench diode gate oxide 12;
and the source metal 11 is positioned on the upper surfaces of the N + source region 6, the P-plus region 7 and the isolation oxide 10 and is connected with the polysilicon gate 13 of the trench diode through a contact hole.
Furthermore, the MOSFET gate oxide 9, the trench diode gate oxide 12 and the isolation oxide 10 are all made of SiO 2 。
Further, the MOSFET polysilicon gate 8 and the trench diode polysilicon gate 13 are made of polysilicon, which is doped N-type, doped P-type, and doped with a concentration of 1 × 10 19 ～1×10 20 cm -3 。
Further, the material of the source metal 11 and the drain metal 1 are both Ni/Ti/Ni/Ag stacked metal materials for forming ohmic contact.
Furthermore, the N-drift layer 3 is N-type SiC, the doping element is N element, and the doping concentration is 1 multiplied by 10 15 ～5×10 16 cm -3 The thickness is 5-15 μm, and the doping concentration and thickness of the N-drift layer 3 determine the breakdown voltage and the on-state characteristic of the device.
Further, the thickness of the MOSFET gate oxide 9 is 50 nm-150 nm, the thickness of the trench diode gate oxide 12 is 10 nm-50 nm, and the thickness of the trench diode gate oxide 12 is thinner than that of the MOSFET gate oxide 9, so that when the device is used as a reverse freewheeling diode, the trench diode is conducted, the substrate layer 2 emits electrons, the electrons enter the right N + source region 6 through an inversion layer trench on the upper surface of the right P-base region 5, and then enter the source metal 11, and reverse current pointing to the drain metal 1 from the source metal 11 is formed. FIG. 3 is a comparison of the simulation results of the conduction curves of the conventional structure and the structure of the present invention when operating in the reverse freewheeling state, and it is apparent that the conventional structure conducts reverse conduction (bipolar conduction) through the body diode, and the turn-on voltage V is significantly lower than the turn-on voltage V TH The voltage is 2.7V, and the conduction curve of the structure of the invention presents a linear region, which indicates that the embedded channel diode is in unipolar conduction, and the turn-on voltage is only 1.5V. FIG. 4 shows the current I in the reverse direction SD ＝100A/cm 2 In the comparison of the hole concentration distribution in the device of the conventional structure and the structure of the invention, it can be seen that the hole concentration in the N-drift region 3 is lower in the structure of the invention. FIG. 5 shows the current I in the reverse direction SD ＝100A/cm 2 The lower hole concentration demonstrates that the inventive structure greatly suppresses the turn-on of the parasitic body diode, which means that it completely eliminates the bipolar degradation effect.
Further, the JFET region 4 is N-type SiC, the doping element is N element, and the doping concentration is 1 multiplied by 10 17 ～5×10 17 cm -3 The thickness is 1-2 mu m, the JFET area 4 is mainly used for improving the conduction characteristic of the device, and the high-concentration JFET area 4 is beneficial to improving the current distribution and reducing the conduction resistance of the device. FIG. 6 shows a conventional structure and the present inventionThe forward conduction characteristic and the reverse breakdown characteristic of the structural device are compared, and it can be seen that the breakdown voltage BV of the structure provided by the invention is not degraded compared with that of the traditional structure. In the aspect of forward conduction characteristics, although the right channel of the device in the structure of the invention serves as a conductive path when the device is in reverse conduction, so that the density of the forward conduction channel of the device is reduced by half, as can be seen from the partially enlarged view in fig. 6, the current carrying capacity of the device is not obviously degraded in a linear region, and when I is in a linear region DS ＝100A/cm 2 In time, the on-resistance R of the conventional structure ON Is 0.89m omega cm 2 R of the structure of the invention ON Is 0.96m omega cm 2 In contrast, this is only an 8% increase, primarily because the high concentration of the JFET region 4 allows for more uniform current flow, as shown in fig. 7.
Further, the horizontal distance between the MOSFET polysilicon gate 8 and the trench diode polysilicon gate 13 is 0.2 μm to 1 μm, the length of the contact hole between the source metal 11 and the trench diode polysilicon gate 13 is 0.2 μm to 1 μm, and the source metal 11 is connected to the trench diode polysilicon gate 13 through the contact hole. Compared with the conventional structure shown in fig. 1, part of the polysilicon of the structure of the invention is etched to form the polysilicon gate 13 of the trench diode, thereby weakening the coupling effect between device electrodes and greatly improving the capacitance characteristic and the gate charge characteristic of the SiC MOSFET. FIG. 8 shows the input capacitance characteristics (C) of the device with the conventional structure and the structure of the present invention ISS ) Output capacitance characteristic (C) OSS ) And transfer capacitance characteristics (C) RSS ) Comparison of simulation results of (A) when V DS C of conventional structure at =200V ISS Is 20nF/cm 2 ，C RSS Is 52pF/cm 2 And C of the structure of the present invention ISS Is only 9nF/cm 2 Reduced by 55%, C RSS Is 7pF/cm 2 And the reduction is 87%. FIG. 9 (a) is a simulation circuit diagram of gate charge characteristics, and FIG. 9 (b) is a comparison graph of simulation results of gate charge characteristics of the conventional structure and the structure of the present invention, from which it can be seen that the gate charge Q of the conventional structure is G Is 1037nC/cm 2 Grid leakage charge Q GD Is 121nC/cm 2 The gate charge Q of the inventive structure G Is 531 tonC/cm 2 Grid leakage charge Q GD Is 12nC/cm 2 In contrast, the degradation is reduced by 49% and 90%, respectively, and therefore, the quality factor R for evaluating the high-frequency characteristics of the device ON ×Q G And R ON ×Q GD The improvements are 45% and 89%, respectively, which means that the inventive structure is more advantageous in high frequency applications. For a more intuitive comparison, table one summarizes the performance parameters of the two structures.
Furthermore, the P-base region 5 is doped P-type, the doping element is Al element, and the doping concentration is 1 × 10 17 ～5×10 17 cm -3 The thickness of the P-base region 5 is 1-2 μm.
Furthermore, the N + source region 6 is doped N-type, the doping element is N element, and the doping concentration is 1 × 10 19 ～1×10 20 cm -3 The thickness of the N + source region 6 is 0.1-1 μm.
Further, P-plus7 is P-type doping, the doping element is Al element, and the doping concentration is 1 × 10 19 ～1×10 20 cm -3 The thickness of the P-plus7 is 0.1 to 1 mu m.
Referring to fig. 10 to 21, fig. 10 to 21 are flow charts of a method for fabricating a device structure according to the present invention, and the specific fabrication method includes the following steps:
step 1: selecting a SiC substrate layer 2, and growing an N-drift layer 3 on the upper surface of the substrate layer 2 by using an epitaxial growth process, wherein the doping element of the N-drift layer 3 is an N element, and the doping concentration is 1 multiplied by 10 15 ～5×10 16 cm -3 The thickness is 5 to 15 μm, see FIG. 10.
And 2, step: a JFET region 4 is grown on the upper surface of the N-drift layer 3 by utilizing an epitaxial growth process, the JFET region 4 is doped with N elements with the doping concentration of 1 multiplied by 10 17 ～5×10 17 cm -3 The thickness is 1 to 2 μm, see FIG. 11.
And step 3: at 400 deg.C, using Ni/Au metal layer as barrier layer, performing Al ion implantation on the upper surface of JFET region 4 for 4 times with implantation energies of 200keV, 300keV, 400keV and 500keV, respectively, and with implantation energy of 200keV, the implantation dosage is 1.0 × 10 12 cm -2 (ii) a At an implantation energy of 300keVThe implantation dose is 5.0 × 10 12 cm -2 (ii) a At an implantation energy of 400keV, the implantation dose is 4.0 × 10 13 cm -2 (ii) a At an implantation energy of 500keV, the implantation dose is 7.0 × 10 12 cm -2 To form P-base region 5, see fig. 12.
And 4, step 4: at the ambient temperature of 400 ℃, siO is adopted 2 The oxide layer is used as a barrier layer, N ions are implanted for 4 times on the upper surfaces of the left and right P-base regions 5, the implantation energies are respectively 60keV, 80keV, 100keV and 120keV, and the implantation dosage is 1.6 multiplied by 10 when the implantation energy is 60keV 15 cm -2 (ii) a At an implant energy of 80keV, the implant dose is 1.8X 10 15 cm -2 (ii) a At an implantation energy of 100keV, the implantation dose is 2.0 × 10 15 cm -2 (ii) a At an implantation energy of 120keV, the implantation dose is 1.8 × 10 15 cm -2 To form N + source regions 6, see fig. 13.
And 5: at the ambient temperature of 400 ℃, siO is adopted 2 Using the oxide layer as a barrier layer, performing Al ion implantation on the upper surfaces of the left and right P-base regions 5 for 4 times, wherein the implantation energies are 60keV, 80keV, 100keV and 120keV, respectively, and the implantation dose is 1.6 × 10 at an implantation energy of 60keV 15 cm -2 (ii) a At an implant energy of 80keV, the implant dose is 1.8X 10 15 cm -2 (ii) a At an implantation energy of 100keV, the implantation dose is 2.0 × 10 15 cm -2 (ii) a At an implantation energy of 120keV, the implantation dose is 1.8 × 10 15 cm -2 To form a P-plus region 7, see fig. 14.
And 6: and (3) carrying out high-temperature annealing after ion implantation in an argon environment at 1200-1800 ℃, wherein the annealing time is 20-60 minutes, and activating impurity ions of the P-base region, the N + source region and the P-plus region.
And 7: in a dry oxygen environment, the ambient temperature is 1100 ℃, the oxidation time is 8 hours, and SiO grows on the upper surfaces of a JFET (junction field effect transistor) area 4, a left P-base area 5, a right P-base area 5, a left N + source area 6, a right P-plus area 7 2 With a thickness of 30nm, depositing a layer of SiO with a thickness of 20-120 nm by PECVD 2 See fig. 15.
And 8: in SiO 2 The upper surface adopts photoresist as a mask plate, and SiO on the right part is etched 2 See fig. 16.
And step 9: in SiO 2 Depositing polysilicon on the upper surface, wherein the polysilicon is doped N-type, the doping element is P element, and the doping concentration is 1 × 10 19 ～1×10 20 cm -3 See fig. 17.
Step 10: the polysilicon deposited in step 9 is etched using photoresist as a mask on the polysilicon top surface to form MOSFET polysilicon gate 8, and trench diode polysilicon gate 13, see fig. 18.
Step 11: depositing SiO on the MOSFET polysilicon gate 8, the trench diode polysilicon gate 13, and all exposed upper surfaces 2 See fig. 19.
Step 12: in the SiO 2 The upper surface adopts photoresist as a mask to etch SiO 2 Exposing the upper surfaces of the P-plus region 7, the N + source region 6 and the trench diode polysilicon gate 13, forming the MOSFET gate oxide 9 on the upper surfaces of the left N + source region 6, the left P-base region 5 and a portion of the JFET region 4, and forming the trench diode gate oxide 12 on the upper surfaces of the right N + source region 6, the right P-base region 5 and a portion of the JFET region 4, which is thinner, as shown in fig. 20.
Step 13: the Ni/Ti/Ni/Ag stack metal is deposited on the front side of the device as the source metal 11 and the Ni/Ti/Ni/Ag stack metal is deposited on the back side of the device as the drain metal 1, see fig. 21.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (1)
1. A preparation method of a SiC MOSFET with an embedded channel diode is characterized by comprising the following steps:
growing an N-drift layer (3) on the upper surface of the substrate layer (2);
growing a JFET region (4) on the upper surface of the N-drift layer (3);
adopting a Ni/Au metal layer as a barrier layer on the JFET area (4), and performing Al ion implantation with the energy of 100 keV-600 keV for 2-5 times to form a left P-base area (5) and a right P-base area (5);
SiO is adopted on the upper surfaces of the left and right P-base regions (5) and the JFET region (4) 2 The oxide layer is used as a barrier layer, N ions with the energy of 10 keV-200 keV are implanted for 2-5 times to form a left N + source region and a right N + source region (6);
SiO is adopted on the upper surfaces of the left and right P-base regions (5), the left and right N + source regions (6) and the JFET region (4) 2 As a barrier layer, carrying out 2-5 times of Al ion implantation with the energy of 10 keV-200 keV to form a left P-plus area (7) and a right P-plus area (7);
performing high-temperature annealing after ion implantation in an argon environment at 1200-1800 ℃, wherein the annealing time is 20-60 minutes, and activating impurity ions of a left P-base area (5), a right P-base area (5), a left N + source area (6) and a right P-plus area (7);
thermally growing SiO on the upper surfaces of the JFET area (4), the left and right P-base areas (5), the left and right N + source areas (6), the left and right P-plus areas (7) 2 And using photoresist as mask to etch SiO 2 Etching and thinning the right surface;
in SiO 2 Depositing polysilicon on the upper surface, and etching the deposited polysilicon to form a MOSFET polysilicon gate (8) and a trench diode polysilicon gate (13);
depositing SiO on the MOSFET polysilicon gate (8), the trench diode polysilicon gate (13), and all exposed upper surfaces 2 In the SiO 2 The upper surface adopts photoresist as a mask to etch SiO 2 Exposing the upper surfaces of the P-plus region (7), the N + source region (6) and part of the polysilicon gate (13) of the trench diode, and forming MOSFET gate oxide (9) positioned on the upper surfaces of the left N + source region (6), the left P-base region (5) and part of the JFET region (4), and the trench diode gate oxide (12) which is positioned on the upper surfaces of the right N + source region (6), the right P-base region (5) and part of the JFET region (4) and has thinner thickness;
the source metal (11) is sputtered on the front side of the device and the drain metal (1) is sputtered on the back side of the device.
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| WO2017114113A1 (en) * | 2015-12-31 | 2017-07-06 | 全球能源互联网研究院 | Sic trench mosfet device for integrating schottky diode, and manufacturing method thereof |
| CN109037333A (en) * | 2017-06-12 | 2018-12-18 | 中兴通讯股份有限公司 | Silicone carbide metal oxide semiconductor field effect transistor and its manufacturing method |
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| WO2017114113A1 (en) * | 2015-12-31 | 2017-07-06 | 全球能源互联网研究院 | Sic trench mosfet device for integrating schottky diode, and manufacturing method thereof |
| CN109037333A (en) * | 2017-06-12 | 2018-12-18 | 中兴通讯股份有限公司 | Silicone carbide metal oxide semiconductor field effect transistor and its manufacturing method |
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