CN116072546A - Silicon carbide split gate trench MOSFET integrated with SBD and preparation method - Google Patents
Silicon carbide split gate trench MOSFET integrated with SBD and preparation method Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 61
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 61
- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000151 deposition Methods 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000011084 recovery Methods 0.000 description 32
- 238000005516 engineering process Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract
The invention relates to the technical field of power semiconductors, and provides a silicon carbide split gate trench MOSFET integrated with an SBD and a preparation method thereof, wherein the method comprises the following steps: an N+ type substrate, on which an N+ type buffer layer is grown; growing an N-type drift region on the N+ type buffer layer; forming a P-type doped region on the N-type drift region; forming an N+ type doped region on the P type doped region; etching a grid groove and a source groove on the N+ type doped region, the P type doped region and the N-type drift region; al ion implantation is carried out on the bottom surface and the side surface of the source electrode groove, and a P+ type doped region is formed on the N-type drift region; depositing an oxide layer in the gate trench; a split gate is formed between the bottom and the oxide layers on the two sides; depositing a gate oxide layer on the split gate; then forming a grid electrode; depositing an oxide layer on the grid electrode; forming an SBD in the source electrode groove; and forming a source electrode in the source electrode groove, and forming a drain electrode on the other surface of the N+ type substrate.
Description
Technical Field
The invention relates to the technical field of power semiconductors, in particular to a silicon carbide split gate trench MOSFET integrated with an SBD and a preparation method.
Background
The excellent physical characteristics of the silicon carbide material enable the silicon carbide trench MOSFET to have good static and dynamic characteristics, but the turn-on voltage of the silicon carbide trench MOSFET body diode is higher due to the larger forbidden bandwidth; in addition, the bipolar degradation phenomenon of the silicon carbide trench MOSFET, namely that the conduction of the body diode can increase defects in the drift region, so that the forward resistance is increased, the problem brings serious test for the long-term stable operation of the silicon carbide trench MOSFET, and the challenge for the safety design of the whole power electronic system. In practice, a silicon carbide schottky diode is typically connected in anti-parallel with a silicon carbide trench MOSFET to act as a freewheeling diode. However, the external silicon carbide schottky diode (Schottky Barrier Diode, SBD) inevitably introduces additional parasitic inductance and capacitance, which greatly affects the switching performance of the silicon carbide trench MOSFET, making it always limited in the high frequency and miniaturization directions. In addition, the external silicon carbide schottky diode also increases packaging cost and increases module volume.
The existing silicon carbide trench MOSFET has poor reverse recovery characteristic and reverse recovery peak current I rm Reverse recovery time T rr Reverse recovery charge Q rr The switching speed and switching loss of the silicon carbide trench MOSFET are severely affected. Furthermore, the Miller capacitance C of the conventional silicon carbide trench MOSFET gd And gate charge Q gd The larger switching loss is high, so that the device has larger power consumption in high-frequency and high-power application, and the use cost of the device can be greatly increased.
Disclosure of Invention
The invention aims to solve at least one technical problem in the background art and provides a silicon carbide split gate trench MOSFET integrated with an SBD and a preparation method.
In order to achieve the above object, the present invention provides a method for manufacturing a silicon carbide split gate trench MOSFET of an integrated SBD, comprising:
providing an N+ type substrate, and growing an N+ type buffer layer on one surface of the N+ type substrate;
growing an N-type drift region on the N+ type buffer layer;
forming a P-type doped region on the N-type drift region through Al ion implantation;
forming an N+ type doped region on the P type doped region through N ion implantation;
etching a grid groove and a source groove on the N+ type doped region, the P type doped region and the N-type drift region, wherein the grid groove and the source groove are arranged at intervals, and the source groove is positioned at two sides of the grid groove;
al ion implantation is carried out on the bottom surface and the side surface of the source electrode groove, and a P+ type doped region is formed on the N-type drift region;
depositing oxide layers at the bottom and at both sides of the gate trench;
polysilicon is deposited between the bottom and the oxide layers on the two sides to form split gates;
depositing a gate oxide layer on the split gate;
polysilicon is deposited between the gate oxide layer and the oxide layers on two sides to form a gate;
depositing an oxide layer on the gate;
depositing schottky metal in the source electrode groove to form an SBD;
and depositing Al metal in the source electrode groove to form a source electrode, and depositing Al metal on the other surface of the N+ type substrate to form a drain electrode.
According to one aspect of the invention, the SBD is deposited laterally of the N-type drift region between the P+ type doped region and the P type doped region.
According to one aspect of the invention, the thickness of the N+ type substrate is 100-500 μm, and the doping concentration is 1×10 19 -1×10 21 cm -3 。
According to one aspect of the invention, the thickness of the N+ type buffer layer is 1-20 μm, and the doping concentration is 1×10 18 -1×10 20 cm -3 。
According to one aspect of the invention, the N-type drift region has a thickness of 5-200 μm and a doping concentration of 1×10 13 -1×10 17 cm -3 。
According to one aspect of the invention, the P+ type doped region has a thickness of 0.1-10 μm and a length of0.1-10 μm, with a doping concentration of 1×10 18 -1×10 20 cm -3 。
According to one aspect of the invention, the P-type doped region has a thickness of 0.1-10 μm, a length of 0.1-20 μm, and a doping concentration of 1×10 16 -1×10 18 cm -3 。
According to one aspect of the invention, the N+ type doped region has a thickness of 0.1-10 μm, a length of 0.2-30 μm, and a doping concentration of 1×10 18 -1×10 20 cm -3 。
According to one aspect of the invention, the source trench has a depth of 0.5-50 μm and a length of 0.1-50 μm.
According to one aspect of the present invention, the thickness of the SBD is 0.1-20 μm.
According to one aspect of the invention, the gate trench has a depth of 0.5-50 μm and a length of 0.2-50 μm.
According to one aspect of the invention, the gate has a thickness of 0.2-30 μm and a length of 0.1-45 μm.
According to one aspect of the invention, the split gate has a thickness of 0.2-20 μm and a length of 0.1-45 μm.
According to one aspect of the invention, the distance between the grid electrode and the P type doped region or the N+ type doped region is 0.05-0.5 μm, the distance between the grid electrode and the split grid is 0.05-10 μm, the distance between the side surface of the split grid and the N-type drift region is 0.05-10 μm, and the distance between the bottom surface of the split grid and the N-type drift region is 0.05-10 μm.
In order to achieve the above object, the present invention further provides a silicon carbide split gate trench MOSFET integrated with an SBD, including:
an n+ type substrate;
an n+ type buffer layer disposed on one surface of the n+ type substrate;
an N-type drift region arranged on the N+ type buffer layer;
the P-type doped region is arranged on the N-type drift region;
the N+ type doped region is arranged on the P type doped region;
a grid groove and a source groove are arranged on the N+ type doped region, the P type doped region and the N-type drift region, wherein the grid groove and the source groove are arranged at intervals, and the source groove is positioned at two sides of the grid groove;
p+ type doped regions are arranged on the bottom surface and the side surface of the source electrode groove, and the P+ type doped regions are positioned on the N-type drift region;
an oxide layer is arranged at the bottom and two sides in the grid electrode groove;
split gates are arranged between the bottom and the oxide layers on the two sides;
a grid oxide layer is arranged on the split grid;
a grid electrode is arranged between the grid electrode oxide layer and the oxide layers at two sides of the grid electrode groove;
an oxide layer is arranged on the grid electrode;
an SBD is arranged in the source electrode groove;
a source electrode is arranged in the source electrode groove;
and the other surface of the N+ type substrate is provided with a drain electrode.
According to one aspect of the invention, a method for fabricating a silicon carbide split gate trench MOSFET integrated with an SBD includes the steps of: an N+ type substrate, wherein an N+ type buffer layer is grown on one surface of the N+ type substrate; growing an N-type drift region on the N+ type buffer layer; forming a P-type doped region on the N-type drift region through Al ion implantation; forming an N+ type doped region on the P type doped region through N ion implantation; etching a grid groove and a source groove on the N+ type doped region, the P type doped region and the N-type drift region, wherein the grid groove and the source groove are arranged at intervals, and the source groove is positioned at two sides of the grid groove; performing Al ion vertical injection and lateral injection on the bottom surface and the side surface of the source electrode groove, so that an L-shaped P+ type doped region is formed on the N-type drift region; depositing oxide layers at the bottom and at both sides of the gate trench; polysilicon is deposited between the bottom and the oxide layers on the two sides to form split gates; depositing a gate oxide layer on the split gate; polysilicon is deposited between the gate oxide layer and the oxide layers at two sides of the gate trench to form a gate; depositing an oxide layer on the grid electrode; depositing schottky metal in the source electrode groove to form an SBD; within the source trenchAnd depositing Al metal to form a source electrode, and depositing Al metal on the other surface of the N+ type substrate to form a drain SBD12, wherein the drain SBD12 is deposited on the side of the N-type drift region between the P+ type doped region and the P type doped region. So arranged, the integrated SBD on the side wall of the source trench can optimize the reverse recovery characteristic of the silicon carbide trench MOSFET without increasing the cell size, including reducing the reverse recovery peak current I rm Reverse recovery time T rr Reverse recovery charge Q rr . In addition, the invention also applies the split gate technology, can reduce the Miller capacitance (gate-drain capacitance) C of the silicon carbide trench MOSFET gd And gate charge Q gd Thereby reducing the on and off loss of the device. The invention integrates SBD and split gate technology, so that the switching loss of the device is lower, the dynamic and static characteristics of the device are better, the high-frequency performance of the silicon carbide trench MOSFET can be exerted to the greatest extent, the size of the device is not increased, and the cost of the device under the same performance can be reduced.
According to the scheme of the invention, when the silicon carbide split gate trench MOSFET integrated with the SBD is in reverse recovery, carriers accumulated in the body can flow out of the SBD rapidly, so that the reverse recovery peak current I of the device is greatly reduced rm Reverse recovery time T rr Reverse recovery charge Q rr . In addition, the split gate structure to ground reduces the miller capacitance C of the device gd And gate charge Q gd Thereby reducing switching losses of the device.
According to the scheme of the invention, the silicon carbide-based power device has far better device performance than a Si-based device.
The invention provides a silicon carbide split gate MOSFET device, a device miller capacitance C gd Gate charge Q gd And the switching loss is lower than that of the traditional silicon carbide MOSFET device, and the dynamic characteristic is better.
The invention relates to an SiC integrated SBD split gate trench MOSFET device, which has better reverse recovery characteristic: reverse recovery peak current I rm Reverse recovery time T rr Reverse recovery charge Q rr Are lower.
The silicon carbide split gate trench MOSFET of the integrated SBD provided by the invention has lower switching loss.
The silicon carbide split gate trench MOSFET of the integrated SBD does not require an external SBD resulting in lower cost of use.
Drawings
Fig. 1 schematically illustrates a cross-sectional view of a silicon carbide split gate trench MOSFET of an integrated SBD according to an embodiment of the invention.
Detailed Description
The present disclosure will now be discussed with reference to exemplary embodiments. It should be understood that the embodiments discussed are merely to enable those of ordinary skill in the art to better understand and thus practice the teachings of the present invention and do not imply any limitation on the scope of the invention.
As used herein, the term "comprising" and variants thereof are to be interpreted as meaning "including but not limited to" open-ended terms. The term "based on" is to be interpreted as "based at least in part on". The terms "one embodiment" and "an embodiment" are to be interpreted as "at least one embodiment.
Fig. 1 schematically illustrates a cross-sectional view of a silicon carbide split gate trench MOSFET of an integrated SBD according to an embodiment of the invention. Referring to fig. 1, in this embodiment, the method for manufacturing a silicon carbide split gate trench MOSFET of an integrated SBD according to the present invention includes the steps of:
an n+ type substrate 1, an n+ type buffer layer 2 is grown on one surface (upper surface in the figure) of the n+ type substrate 1;
growing an N-type drift region 3 on the N+ type buffer layer 2;
forming a P-type doped region 4 on the N-type drift region 3 by Al ion implantation;
forming an N+ type doped region 5 on the P type doped region 4 through N ion implantation;
etching a gate trench 6 and a source trench 7 on the n+ type doped region 5, the P type doped region 4 and the N-type drift region 3, wherein the gate trench 6 is spaced apart from the source trench 7, and the source trench 7 is located at both sides of the gate trench 6;
performing Al ion vertical implantation and lateral implantation on the bottom surface and the side surface of the source trench 7 so as to form an L-shaped p+ -type doped region 8 on the N-type drift region 3;
depositing an oxide layer 9 at the bottom and on both sides of the gate trench 6;
polysilicon is deposited between the bottom and the oxide layers 9 on both sides to form split gates 10;
depositing a gate oxide layer 11 on the split gate 10;
polysilicon is deposited between the gate oxide layer and the oxide layers 9 on both sides of the gate trench 6 to form a gate 12;
depositing an oxide layer 9 on the gate electrode 12;
depositing a schottky metal in the source trench 7 to form an SBD13;
al metal is deposited in the source trench 7 to form a source 14, and Al metal is deposited on the other surface (lower surface in the drawing) of the n+ -type substrate 1 to form a drain 15.
In the present embodiment, as shown in fig. 1, the SBD13 is deposited laterally of the N-type drift region 3 between the p+ -type doped region 8 and the P-type doped region 4.
As set forth above, the integrated SBD on the side wall of the source trench 7 can optimize the reverse recovery characteristics of the silicon carbide trench MOSFET without increasing the cell size, including reducing the reverse recovery peak current I rm Reverse recovery time T rr Reverse recovery charge Q rr . In addition, the invention also applies the split gate technology, can reduce the Miller capacitance (gate-drain capacitance) C of the silicon carbide trench MOSFET gd And gate charge Q gd Thereby reducing the on and off loss of the device. The invention integrates SBD and split gate technology, so that the switching loss of the device is lower, the dynamic and static characteristics of the device are better, the high-frequency performance of the silicon carbide trench MOSFET can be exerted to the greatest extent, the size of the device is not increased, and the cost of the device under the same performance can be reduced.
In particular, the integrated SBD can enable the current carriers accumulated in the body to flow out of the SBD rapidly during reverse recovery of the MOSFET device, thus enabling the MOSFET device to be turned off rapidly, and reducing the reverse recovery peak value electricity of the deviceStream I rm Reverse recovery time T rr Reverse recovery charge Q rr 。
Furthermore, the grounded split gate structure separates the gate and the drain of the MOSFET device of the invention, thereby reducing the capacitance C between the gate and the drain gd Reducing the miller capacitance C of the MOSFET device gd (Gate-drain capacitance), and gate charge Q gd Is the integral of the miller capacitance with voltage, so the gate charge Q gd And also reduces the switching losses of the device.
In the present embodiment, the thickness of the N+ type substrate 1 is 100-500 μm, and the doping concentration is 1×10 19 -1×10 21 cm -3 ；
The thickness of the N+ type buffer layer 2 is 1-20 μm, and the doping concentration is 1×10 18 -1×10 20 cm -3 ；
The thickness of the N-type drift region 3 is 5-200 μm, and the doping concentration is 1×10 13 -1×10 17 cm -3 ；
The P+ type doped region 8 has a thickness of 0.1-10 μm, a length of 0.1-10 μm, and a doping concentration of 1×10 18 -1×10 20 cm -3 ；
The thickness of the P-type doped region 4 is 0.1-10 μm, the length is 0.1-20 μm, and the doping concentration is 1×10 16 -1×10 18 cm -3 ；
The N+ type doped region 5 has a thickness of 0.1-10 μm, a length of 0.2-30 μm, and a doping concentration of 1×10 18 -1×10 20 cm -3 ；
The depth of the source trench 7 is 0.5-50 μm and the length is 0.1-50 μm;
the thickness of the SBD is 0.1-20 mu m;
the depth of the gate trench 6 is 0.5-50 μm and the length is 0.2-50 μm;
the thickness of the grid electrode 12 is 0.2-30 mu m, and the length is 0.1-45 mu m;
the split gate 10 has a thickness of 0.2-20 μm and a length of 0.1-45 μm.
The distance between the gate electrode 12 and the P-type doped region 4 or the n+ -type doped region 5 is 0.05-0.5 μm, the distance between the gate electrode 12 and the split gate 10 is 0.05-10 μm, the distance between the side surface of the split gate 10 and the N-type drift region 3 is 0.05-10 μm, and the distance between the bottom surface of the split gate 10 and the N-type drift region 3 is 0.05-10 μm.
According to the arrangement of the invention, when the silicon carbide split gate trench MOSFET integrated with the SBD is in reverse recovery, carriers accumulated in the body can flow out of the SBD rapidly, so that the reverse recovery peak current I of the device is greatly reduced rm Reverse recovery time T rr Reverse recovery charge Q rr . In addition, the split gate structure to ground reduces the miller capacitance C of the device gd And gate charge Q gd Thereby reducing switching losses of the device.
In order to achieve the above purpose, the invention also provides a silicon carbide split gate trench MOSFET integrated with the SBD, which is prepared by the method. Specifically, as shown in fig. 1, the silicon carbide split gate trench MOSFET of the integrated SBD includes:
an n+ type substrate 1;
an n+ type buffer layer 2 provided on one surface of the n+ type substrate 1;
an N-type drift region 3 provided on the n+ type buffer layer 2;
the P-type doped region 4 is arranged on the N-type drift region 3;
an n+ type doped region 5 disposed on the P type doped region 4;
a grid groove 6 and a source groove 7 are arranged on the N+ type doped region 5, the P type doped region 4 and the N-type drift region 3, wherein the grid groove 6 and the source groove 7 are arranged at intervals, and the source grooves 7 are positioned on two sides of the grid groove 6;
the bottom surface and the side surface of the source electrode groove 7 are provided with P+ type doped regions 8, and the P+ type doped regions 8 are positioned on the N-type drift region 3;
the bottom and two sides in the grid electrode groove 6 are provided with an oxide layer 9;
a split gate 10 is arranged between the bottom and the oxide layers 9 on the two sides;
a gate oxide layer 11 is arranged on the split gate 10;
a grid electrode 12 is arranged between the grid electrode oxide layer 11 and the oxide layers 9 at two sides of the grid electrode groove 6;
an oxide layer 9 is arranged on the grid electrode 12;
an SBD13 is arranged in the source electrode groove 7;
a source 14 is arranged in the source trench 7;
the other surface of the n+ -type substrate 1 is provided with a drain electrode 15.
In the present embodiment, as shown in fig. 1, the SBD13 is deposited laterally of the N-type drift region 3 between the p+ -type doped region 8 and the P-type doped region 4.
According to the scheme, the silicon carbide-based power device has better device performance than a Si-based device. Specifically, the invention provides a silicon carbide split gate MOSFET device, and a device miller capacitance C gd Gate charge Q gd And the switching loss is lower than that of the traditional silicon carbide MOSFET device, and the dynamic characteristic is better.
The invention relates to an SiC integrated SBD split gate trench MOSFET device, which has better reverse recovery characteristic: reverse recovery peak current I rm Reverse recovery time T rr Reverse recovery charge Q rr Are lower.
The silicon carbide split gate trench MOSFET of the integrated SBD provided by the invention has lower switching loss.
The silicon carbide split gate trench MOSFET of the integrated SBD does not require an external SBD resulting in lower cost of use.
Finally, it is noted that the above-mentioned preferred embodiments are only intended to illustrate rather than limit the invention, and that, although the invention has been described in detail by means of the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention as defined by the appended claims.
Claims (15)
1. The preparation method of the silicon carbide split gate trench MOSFET of the integrated SBD is characterized by comprising the following steps of:
providing an N+ type substrate, and growing an N+ type buffer layer on one surface of the N+ type substrate;
growing an N-type drift region on the N+ type buffer layer;
forming a P-type doped region on the N-type drift region through Al ion implantation;
forming an N+ type doped region on the P type doped region through N ion implantation;
etching a grid groove and a source groove on the N+ type doped region, the P type doped region and the N-type drift region, wherein the grid groove and the source groove are arranged at intervals, and the source groove is positioned at two sides of the grid groove;
al ion implantation is carried out on the bottom surface and the side surface of the source electrode groove, and a P+ type doped region is formed on the N-type drift region;
depositing oxide layers at the bottom and at both sides of the gate trench;
polysilicon is deposited between the bottom and the oxide layers on the two sides to form split gates;
depositing a gate oxide layer on the split gate;
polysilicon is deposited between the gate oxide layer and the oxide layers on two sides to form a gate;
depositing an oxide layer on the gate;
depositing schottky metal in the source electrode groove to form an SBD;
and depositing Al metal in the source electrode groove to form a source electrode, and depositing Al metal on the other surface of the N+ type substrate to form a drain electrode.
2. The method of forming a silicon carbide split gate trench MOSFET of an integrated SBD according to claim 1, wherein said SBD is deposited laterally of said N-type drift region between said p+ type doped region and said P type doped region.
3. The method for manufacturing an SBD integrated silicon carbide split gate trench MOSFET of claim 1, wherein the n+ type substrate has a thickness of 100-500 μm and a doping concentration of 1×10 19 -1×10 21 cm -3 。
4. The method for manufacturing an SBD integrated silicon carbide split gate trench MOSFET of claim 1, wherein the n+ buffer layer has a thickness of 1-20 μm and a doping concentration of 1×10 18 -1×10 20 cm -3 。
5. According to claimThe method for manufacturing the silicon carbide split gate trench MOSFET of the integrated SBD as described in 1, wherein the thickness of the N-type drift region is 5-200 μm, and the doping concentration is 1×10 13 -1×10 17 cm -3 。
6. The method for manufacturing an SBD integrated silicon carbide split gate trench MOSFET of claim 1, wherein the P+ doped region has a thickness of 0.1-10 μm, a length of 0.1-10 μm, and a doping concentration of 1×10 18 -1×10 20 cm -3 。
7. The method of forming an SBD integrated silicon carbide split gate trench MOSFET of claim 1, wherein the P-type doped region has a thickness of 0.1-10 μm, a length of 0.1-20 μm, and a doping concentration of 1X 10 16 -1×10 18 cm -3 。
8. The method for manufacturing an SBD integrated silicon carbide split gate trench MOSFET of claim 1, wherein the n+ doped region has a thickness of 0.1-10 μm, a length of 0.2-30 μm, and a doping concentration of 1×10 18 -1×10 20 cm -3 。
9. The method for fabricating a silicon carbide split gate trench MOSFET of an integrated SBD according to claim 1, wherein said source trench has a depth of 0.5-50 μm and a length of 0.1-50 μm.
10. The method for fabricating a silicon carbide split gate trench MOSFET of an integrated SBD according to claim 1, wherein said SBD has a thickness of 0.1-20 μm.
11. The method of forming a silicon carbide split gate trench MOSFET of an integrated SBD according to claim 1, wherein the gate trench has a depth of 0.5-50 μm and a length of 0.2-50 μm.
12. The method for fabricating a silicon carbide split gate trench MOSFET of an integrated SBD according to claim 1, wherein said gate has a thickness of 0.2-30 μm and a length of 0.1-45 μm.
13. The method for fabricating a silicon carbide split gate trench MOSFET of an integrated SBD according to claim 1, wherein said split gate has a thickness of 0.2-20 μm and a length of 0.1-45 μm.
14. The method for manufacturing a silicon carbide split gate trench MOSFET of an integrated SBD according to any of claims 1-13, wherein the distance between the gate and the P-type doped region or n+ -type doped region is 0.05-0.5 μm, the distance between the gate and the split gate is 0.05-10 μm, the distance between the side of the split gate and the N-type drift region is 0.05-10 μm, and the distance between the bottom of the split gate and the N-type drift region is 0.05-10 μm.
15. An SBD integrated silicon carbide split gate trench MOSFET comprising:
an n+ type substrate;
an n+ type buffer layer disposed on one surface of the n+ type substrate;
an N-type drift region arranged on the N+ type buffer layer;
the P-type doped region is arranged on the N-type drift region;
the N+ type doped region is arranged on the P type doped region;
a grid groove and a source groove are arranged on the N+ type doped region, the P type doped region and the N-type drift region, wherein the grid groove and the source groove are arranged at intervals, and the source groove is positioned at two sides of the grid groove;
p+ type doped regions are arranged on the bottom surface and the side surface of the source electrode groove, and the P+ type doped regions are positioned on the N-type drift region;
an oxide layer is arranged at the bottom and two sides in the grid electrode groove;
split gates are arranged between the bottom and the oxide layers on the two sides;
a grid oxide layer is arranged on the split grid;
a grid electrode is arranged between the grid electrode oxide layer and the oxide layers at two sides of the grid electrode groove;
an oxide layer is arranged on the grid electrode;
an SBD is arranged in the source electrode groove;
a source electrode is arranged in the source electrode groove;
and the other surface of the N+ type substrate is provided with a drain electrode.
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