CN116759460A - Shielded gate trench transistor and manufacturing method thereof - Google Patents
Shielded gate trench transistor and manufacturing method thereof Download PDFInfo
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- CN116759460A CN116759460A CN202311041676.0A CN202311041676A CN116759460A CN 116759460 A CN116759460 A CN 116759460A CN 202311041676 A CN202311041676 A CN 202311041676A CN 116759460 A CN116759460 A CN 116759460A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 135
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000011241 protective layer Substances 0.000 claims abstract description 12
- 210000000746 body region Anatomy 0.000 claims description 34
- 238000005468 ion implantation Methods 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- -1 nitrogen ions Chemical class 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000011084 recovery Methods 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 17
- 229910010271 silicon carbide Inorganic materials 0.000 description 17
- 230000015556 catabolic process Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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Abstract
The application provides a shielded gate trench transistor and a manufacturing method thereof, wherein the transistor comprises: a first conductivity type substrate; the first conductive type drift region is arranged on one side of the first conductive type substrate, and a gate groove is arranged on one side of the first conductive type drift region, which is away from the first conductive type substrate; the second conductive type gate oxide protection layer is arranged at the bottom of the gate groove; the first source electrode layer is arranged on one side of the second conductive type gate oxide protective layer, which is away from the first conductive type substrate; the two Schottky contact areas are oppositely arranged on the side wall of the gate groove; the shielding grid is arranged between the two Schottky contact areas; the oxidation layer is arranged on one side of the shielding gate away from the first source electrode layer; the control gate is wrapped by the oxide layer; the source region is arranged on the outer side of the side wall of the gate groove; the drain electrode is arranged on one side of the first conductive type substrate, which is away from the first conductive type drift region. The application can reduce reverse recovery current.
Description
Technical Field
The application relates to the field of integrated circuit application, in particular to a shielded gate trench transistor and a manufacturing method thereof.
Background
Compared with the traditional silicon material, the silicon carbide has the characteristics of wide band gap, high melting point, low dielectric constant, high breakdown field strength, high heat conductivity coefficient, high saturated electron drift speed and the like, and can be manufactured into devices to work under the scenes of higher temperature, closer distance, higher power level and the like. However, there are also many problems in the power device made of silicon carbide, and in the case of silicon carbide transistor, the existing SiC MOSFET has poor reverse recovery characteristics and reverse recovery peak current I rm Reverse recovery time T rr Reverse recovery charge Q rr The switching speed and the switching loss of the SiC MOSFET are seriously affected. Further, the miller capacitance C of the conventional SiC MOSFET gd And gate charge Q g The device has larger power consumption in high-frequency and high-power application due to larger switching loss, and the use cost of the device can be greatly increased; the specific on-resistance is higher, and the breakdown voltage is lower; the body diode can generate a conductivity modulation effect in a reverse follow current state; the low reliability has weaker protection capability to the gate oxide.
Disclosure of Invention
In view of the above problems in the prior art, the present application provides a shielded gate trench transistor and a method for manufacturing the same, which mainly solve the problem of poor reliability of the existing transistor.
In order to achieve the above and other objects, the present application adopts the following technical scheme.
The application provides a shielded gate trench transistor, comprising: a first conductivity type substrate; a first conductive type drift region arranged on one side of the first conductive type substrate, and a gate trench arranged on one side of the first conductive type drift region away from the first conductive type substrate; the second conductive type gate oxide protection layer is arranged at the bottom of the gate groove; the first source electrode layer is arranged on one side of the second conductive type gate oxide protection layer, which is away from the first conductive type substrate, and forms ohmic contact with the first conductive type drift region; the two Schottky contact areas are arranged on one side of the first source electrode layer, which is away from the second conductive type gate oxide protection layer, and the two Schottky contact areas are oppositely arranged on the side wall of the gate groove; a shielding gate arranged between the two Schottky contact areas; an oxide layer arranged on one side of the shielding gate away from the first source electrode layer; a control gate surrounded by the oxide layer; a source region which is arranged outside the side wall of the gate trench and is in contact with the oxide layer; and the drain electrode is arranged on one side of the first conductive type substrate, which is away from the first conductive type drift region.
In one embodiment of the present application, the source region includes: a second conductive type body region arranged outside the side wall of the gate trench; a first conductivity type source region arranged on one side of the second conductivity type body region away from the first conductivity type drift region, wherein the first conductivity type source region is close to the gate trench; a second conductivity type source region disposed side by side with the first conductivity type source region, and the second conductivity type source region being remote from the gate trench; and a second source electrode layer forming ohmic contacts with the first and second conductive type source regions, respectively.
In an embodiment of the present application, a width of the second conductive type gate oxide protection layer is not smaller than a width of the gate trench.
In an embodiment of the present application, the first conductivity type is N-type, and the second conductivity type is P-type.
In an embodiment of the present application, the second conductivity type body region, the second conductivity type source region and the second conductivity type gate oxide protection layer are all obtained by means of aluminum ion implantation, wherein the second conductivity type body region is lightly doped, and the second conductivity type source region is heavily doped; the first conduction type source region is obtained through nitrogen ion implantation, wherein the first conduction type source region is heavily doped.
In one embodiment of the present application, the material of the oxide layer includes silicon dioxide.
The application also provides a manufacturing method of the shielded gate trench transistor, which comprises the following steps: providing a first conductive type substrate; a first conduction type drift region is arranged on one side of the first conduction type substrate, a source region and a gate trench are arranged on one side, away from the first conduction type substrate, of the first conduction type drift region, and the source region is positioned on two sides of the gate trench; a second conductive type gate oxide protection layer is arranged at the bottom of the gate trench; a first source electrode layer is arranged on one side, away from the first conductive type substrate, of the second conductive type gate oxide protection layer, so that ohmic contact is formed between the first source electrode layer and the first conductive type drift region; two Schottky contact areas are arranged on one side, away from the second conductive type gate oxide protective layer, of the first source electrode layer, and the two Schottky contact areas are oppositely arranged on the side wall of the gate groove; a shielding grid is arranged between the two Schottky contact areas; an oxide layer is arranged on one side of the shielding grid away from the first source electrode layer; manufacturing a control grid, wherein the control grid is wrapped by the oxide layer; a drain is provided on a side of the first conductivity type substrate facing away from the first conductivity type drift region.
In an embodiment of the present application, the step of fabricating the source region includes: forming a second conductive type body region on one side of the first conductive type drift region, which is away from the first conductive type substrate, through ion implantation, wherein the second conductive type body region is arranged on the outer side of the side wall of the gate groove; growing a semiconductor layer on one side of the second conductive type body region, which is away from the first conductive type drift region, and carrying out first conductive type ion implantation on a partial region of the semiconductor layer, which is close to the gate trench, so as to obtain a first conductive type source region; performing second conductivity type ion implantation on a partial region of the semiconductor layer far away from the gate trench to obtain a second conductivity type source region, wherein the second conductivity type source region and the first conductivity type source region are arranged side by side and are in contact with each other; and manufacturing a second source electrode layer, wherein the second source electrode layer forms ohmic contact with the first conductive type source region and the second conductive type source region respectively.
In one embodiment of the present application, the first conductivity type ions comprise nitrogen ions and the second conductivity type ions comprise aluminum ions.
In an embodiment of the present application, the step of fabricating the control gate includes: depositing an oxide layer in the gate trench, wherein the oxide layer covers the Schottky contact area and the shielding gate; forming a groove body by opening holes on the oxide layer, wherein the groove body and the shielding grid are separated by the oxide layer; depositing a polysilicon layer in the groove body to serve as a control gate; and depositing an oxide layer on the control gate again to fill up the gate trench.
As described above, the shielded gate trench transistor and the method for manufacturing the same provided by the application have the following beneficial effects.
According to the application, the doping concentration of the drift region is increased by introducing the shielding grid, so that the specific on-resistance of the drift region is reduced, the grid-drain capacitance and the grid charge are reduced, and the switching frequency is increased. Because the reduction of gate drain capacitance and grid charge, the switching time reduces, and the energy that every turn switch was lost is lower, and integrated schottky contact area in the gate slot, need not external schottky diode, has reduced whole chip packaging cost, can accomplish only schottky contact area under the circumstances of low current freewheel simultaneously and open the freewheel, can reduce reverse recovery current and charge, under the heavy current circumstances, ohmic contact freewheel that the source electrode layer that accessible gate slot is inside formed, the body diode that can be fine is opened in suppression, reduction device performance decline risk.
Drawings
Fig. 1 is a schematic cross-sectional view of a shielded gate trench transistor according to an embodiment of the present application.
Fig. 2 is a flow chart of a method for manufacturing a shielded gate trench transistor according to an embodiment of the application.
Fig. 3 is a schematic cross-sectional view illustrating an active region according to an embodiment of the application.
Fig. 4 is a schematic cross-sectional structure of a second conductive type gate oxide protection layer according to an embodiment of the application.
Fig. 5 is a schematic cross-sectional view of a first source electrode layer with a second source electrode region and an ohmic contact region deposited thereon according to an embodiment of the present application.
Fig. 6 is a schematic cross-sectional view of a shielding gate according to an embodiment of the application.
Fig. 7 is a schematic cross-sectional view of a control gate according to an embodiment of the application.
Reference numerals illustrate:
1-first conductivity type substrate, 2-first conductivity type drift region, 3-second conductivity type gate oxide protective layer, 4-second conductivity type body region, 5-first conductivity type source region, 6-second conductivity type source region, 7-first source electrode layer, 8-schottky contact region, 9-shield gate, 10-control gate, 11-oxide layer, 12-second source electrode layer, 13-drain electrode.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a trench type transistor with a shield gate 9 according to an embodiment of the application. The shielded gate 9 trench transistor of the embodiment of the application comprises: a first conductivity type substrate 1, a first conductivity type drift region 2, a second conductivity type gate oxide protective layer 3, a first source electrode layer 7, two schottky contact regions 8, a shield gate 9, an oxide layer 11, a control gate 10, a source region and a drain electrode 13. The material of the first conductivity type substrate 1 may be silicon carbide, and the first conductivity type substrate 1 is obtained by heavily doping on the basis of the silicon carbide material. The thickness of the first conductive type substrate 1 may be set to 150 μm, although the specific thickness may be set and adjusted according to practical application requirements. A first conductivity type drift region 2 may be provided on one of the sides of the first conductivity type substrate 1, and a gate trench may be provided on a side of the first conductivity type drift region 2 facing away from the first conductivity type substrate 1. The second conductive type gate oxide protective layer 3 is arranged at the bottom of the gate trench; the first source electrode layer 7 is arranged on one side of the second conductive type gate oxide protection layer 3 away from the first conductive type substrate 1 and forms ohmic contact with the first conductive type drift region 2; the two Schottky contact areas 8 are arranged on one side of the first source electrode layer 7, which is away from the second conductive type gate oxide protective layer 3, and the two Schottky contact areas 8 are oppositely arranged on the side wall of the gate groove; the shielding grids 9 are arranged between the two Schottky contact areas 8 and are respectively contacted with the two Schottky contact areas 8; the oxidation layer 11 is arranged on one side of the shielding grid 9 away from the first source electrode layer 7; the control gate 10 is surrounded by an oxide layer 11, the control gate 10 and the shielding gate 9 being separated by the oxide layer 11; the source region is arranged on the outer side of the side wall of the gate trench and is in contact with the oxide layer 11; the drain electrode 13 is arranged on the side of the first conductivity type substrate 1 facing away from the first conductivity type drift region 2.
In an embodiment, the source regions may include a second conductivity type body region 4, a first conductivity type source region 5, a second conductivity type source region 6, and a second source electrode layer 12. Specifically, a second conductivity type body region 4 is respectively disposed at two sides of the gate trench, that is, the second conductivity type body regions 4 at two sides are symmetrically disposed with respect to the gate trench, and a first conductivity type source region 5 and a second conductivity type source region 6 are disposed side by side at one side of each second conductivity type body region 4 facing away from the first conductivity type drift region 2, wherein the first conductivity type source region 5 is located close to the gate trench, and the second conductivity type source region 6 is located away from the gate trench. Second source electrode layers 12 are provided on both sides of the gate trench, the second source electrode layers 12 of each side forming ohmic contact with the first conductivity type source region 5 and the second conductivity type source region 6 of the corresponding side. The second source electrode layer 12 is exemplarily provided at a side of the first conductive type source region 5 facing away from the second conductive type body region 4, and entirely covers the side surface of the first conductive type source region 5, and partially extends to the second conductive type source region 6 to form an ohmic contact. In the layout of the shielded gate trench transistor, the first source electrode layer 7, the second source electrode layer 12 and the schottky contact region 8 are mutually communicated and commonly serve as the source electrode of the transistor. The schottky contact area 8 can realize follow current under the condition of small current, and when the current level is gradually increased, the ohmic contact of the first source electrode layer 7 realizes large current follow current, so that the energy consumption of the whole device is reduced, and meanwhile, the heating power consumption is reduced.
In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type. Specifically, the substrate may be formed by growing silicon carbide, and an n+ type substrate may be obtained by N type heavy doping on the substrate. Continuously growing silicon carbide with a certain thickness on an N+ type substrate, obtaining an N-type drift region through N-type light doping on the newly grown silicon carbide, and carrying out light doping through Al ion implantation on the basis of the N-type drift region to obtain a P-type body region; and growing a semiconductor layer on the basis of the P-type body region, heavily doping part of the region on the basis of the semiconductor layer through Al ion implantation to obtain a P+ type source region, and heavily doping the other part of the region through N ion implantation to obtain an N+ type source region.
In an embodiment, the width of the second conductive type gate oxide protection layer 3 may be set to be not smaller than the width of the gate trench so that a band-shaped structure is formed by the second conductive type gate oxide protection layer 3. The second conductive type gate oxide protection layer 3 may be a p+ type protection layer obtained by performing Al ion implantation at the bottom of the gate trench, and gate oxide breakdown at corners may be effectively prevented by the p+ type protection layer. In addition, the design of the second conductive type gate oxide protective layer 3 covering the bottom of the gate trench is not easy to cause overlay deviation like the existing island design when the first source electrode layer 7 is formed by depositing metal on the second conductive type gate oxide protective layer 3.
In one embodiment, silicon dioxide may be used as the oxide layer 11.
Based on the technical scheme, the P+ type protective layer is formed at the bottom of the gate trench, so that the problem of electric field concentration of the gate oxide layer at the corner of the gate trench can be solved, and gate oxide breakdown can be effectively prevented; the second conductive type gate oxide protective layer 3 at the bottom of the gate trench and the depletion layer formed by the second conductive type body region 4 can be connected into a whole during the gate negative bias, so that the source electrode of the Schottky contact region 8 is well prevented from being electrically leaked, and the power consumption is reduced. In addition, the Schottky contact region 8 is embedded into the gate groove, so that the current density can be greatly improved, the specific on-resistance of the whole device is reduced, the reverse recovery charge is reduced, the switching speed of the silicon carbide transistor is improved, and the overall heating loss of the device is reduced; the schottky contact region 8 is embedded at the bottom of the gate trench, so that the pitch size of the whole cell can be reduced without increasing extra area, and the current density is higher under the same area. According to the embodiment of the application, the insulated gate is introduced to play a role of a field plate in the gate groove, so that the drift region can be assisted to be exhausted during forward blocking, and higher breakdown voltage is achieved; the shielding grid 9 can also isolate the control grid 10 from the drain electrode 13, and the electric field distribution in the grid groove is disturbed by the shielding grid 9, so that the grid drain capacitance (namely the Miller capacitance) is greatly reduced, the switching rate of the transistor is effectively improved, and the switching loss is reduced. The schottky contact areas 8 are arranged on the side walls of the gate grooves, so that a lower schottky barrier can be obtained, starting voltage is reduced, under the condition of small current follow current, the follow current can be started only through the schottky contact areas 8 on the two sides below the grooves, reverse recovery current and charge can be reduced, and switching loss is further reduced; under the condition of large current, the ohmic contact formed below the groove can be used for freewheeling, so that the opening of the body diode can be well restrained, and the risk of performance degradation of the device is reduced.
The embodiment of the application also provides a manufacturing method of the shielded gate 9 trench transistor. Referring to fig. 2, fig. 2 is a flow chart of a method for manufacturing a trench type transistor with a shielding gate 9 according to an embodiment of the application. The manufacturing method comprises the following steps:
in step S200, a first conductivity type substrate 1 is provided.
In an embodiment, the first conductivity type is N type, silicon carbide may be used as a substrate, and N type heavily doped to obtain an n+ type substrate, and the specific doping manner and doping concentration may be set and adjusted according to practical application requirements, which is not limited herein.
In step S210, a first conductivity type drift region 2 is disposed on one side of the first conductivity type substrate 1, and a source region and a gate trench are disposed on one side of the first conductivity type drift region 2 facing away from the first conductivity type substrate 1, the source region being located on two sides of the gate trench.
In an embodiment, silicon carbide continues to grow on the n+ type substrate to form a drift region, and N type light doping is performed on the drift region to obtain an N type drift region, where the specific doping mode and doping concentration can be set and adjusted according to practical application requirements, and the method is not limited herein.
Referring to fig. 3, fig. 3 is a schematic cross-sectional structure of an active region according to an embodiment of the application. In an embodiment, a source region may be disposed on a side of the first conductivity type drift region 2 away from the first conductivity type substrate 1, and the source region may be formed by:
in step S300, a second conductivity type body region 4 is formed by ion implantation on a side of the first conductivity type drift region 2 facing away from the first conductivity type substrate 1, and in particular, a P-type body region may be formed by Al ion implantation on an N-type drift region. The P-type body regions may include two, and the two P-type body regions are symmetrically disposed on the same side of the N-type drift region.
In step S310, a semiconductor layer is grown on the side of the second conductivity type body region 4 away from the first conductivity type drift region 2, and a first conductivity type ion implantation is performed on a partial region of the semiconductor layer close to the gate trench, so as to obtain a first conductivity type source region 5. Specifically, a silicon carbide semiconductor layer may be grown on the basis of the P-type body region, and ion implantation is performed in two regions of the silicon carbide semiconductor layer, wherein N ions are implanted into one region to form an n+ type source region (i.e., the first conductivity type source region 5).
In step S320, a second conductivity type ion implantation is performed on a partial area of the semiconductor layer away from the gate trench, so as to obtain a second conductivity type source region 6, where the second conductivity type source region 6 and the first conductivity type source region 5 are disposed side by side and contact with each other. Specifically, al ions are injected into another region of the silicon carbide semiconductor layer on the same P-type body region to form a P+ type source region, the P+ type source region and the N+ type source region are arranged side by side, wherein two pairs of N+ type source regions on the two P-type body regions are deviated from each other.
After the p+ type source region, the n+ type source region and the P-type body region are obtained, a U-type trench may be formed as a gate trench between the two P-type body regions by dry etching. The P-type body region is in contact with the side wall of the gate trench, the N-type source region is close to the gate trench, and the P+ type source region is far away from the gate trench.
In step S220, a second conductive type gate oxide protection layer 3 is disposed at the bottom of the gate trench.
Referring to fig. 4, fig. 4 is a schematic cross-sectional structure of a second conductive type gate oxide protection layer 3 according to an embodiment of the application. In an embodiment, an Al ion implantation is performed at the bottom of the gate trench to form a p+ type doped region (i.e., the second conductive type gate oxide protection layer 3), so that the p+ doping at the bottom of the gate trench can effectively place gate oxide breakdown at the corner. The implantation of the p+ doped region is a sheeted rather than island design, which makes the metal deposited on the p+ region less prone to overlay bias.
In step S230, the first source electrode layer 7 is disposed on the side of the second conductive type gate oxide protection layer 3 facing away from the first conductive type substrate 1, so that the first source electrode layer 7 forms an ohmic contact with the first conductive type drift region 2.
Referring to fig. 5, fig. 5 is a schematic cross-sectional structure of the first source electrode layer 7 and the second source electrode region and the ohmic contact region deposited thereon according to an embodiment of the application. In one embodiment, metal is deposited on the upper surface of the n+ type source region and the bottom of the gate trench to form a first source electrode layer 7 and a second source electrode layer 12, and the second source electrode layer 12 extends partially to the surface of the p+ type source region, so that the p+ type source region and the n+ type source region respectively form ohmic contact with the second source electrode layer 12. The first source electrode layer 7 forms an ohmic contact with the N-type drift region.
In step S240, two schottky contact regions 8 are disposed on the side of the first source electrode layer 7 facing away from the second conductive type gate oxide protection layer 3, and the two schottky contact regions 8 are disposed on the sidewalls of the gate trench.
Referring to fig. 5, two schottky contact regions 8 are embedded in the first source electrode layer 7, the two schottky contact regions 8 are oppositely disposed on the sidewalls of the gate trench, and the first source electrode layer 7, the second source electrode layer 12 and the two schottky contact regions 8 can be interconnected in the layout to serve as the source of the transistor. The integrated schottky contact area 8 can realize follow current under the condition of small current, when the current level is gradually increased, the ohmic contact of the first source electrode layer 7 is opened, and large current follow current is realized, so that the energy consumption of the whole device is reduced, and meanwhile, the heating power consumption is reduced.
In step S250, a shield gate 9 is disposed between the two schottky contact regions 8.
Referring to fig. 6, fig. 6 is a schematic cross-sectional view of the shielding gate 9 according to an embodiment of the application. In one embodiment, silicon dioxide is deposited on the basis of the structure shown in fig. 5. A shield gate 9 is deposited open-pore on the first source electrode layer 7, which shield gate 9 is obtained by polysilicon doping. The shielding grid 9 formed in the grid groove can be used as a field plate to adjust the distribution of the electric field in the transistor in the longitudinal direction of the grid groove, so that the rated withstand voltage of the whole chip is improved.
In step S260, an oxide layer 11 is provided on the side of the shield gate 9 facing away from the first source electrode layer 7.
In an embodiment, the oxide layer 11 may be redeposited on the basis of the shield gate 9, the gate trench being filled with the oxide layer 11.
In step S270, the control gate 10 is fabricated, and the control gate 10 is wrapped by the oxide layer 11.
Referring to fig. 7, fig. 7 is a schematic cross-sectional view of the control gate 10 according to an embodiment of the application. In one embodiment, openings are made on the basis of the oxide layer 11, trenches are etched to a certain depth, and control gates 10 are deposited in the trenches. Wherein the control gate 10 may be obtained by polysilicon doping. After the control gate 10 is completed, silicon oxide is deposited to fill up the gate trench, and then a polishing process (Chemical Mechanical Polishing, CMP) is used to remove the excess silicon oxide from the surface of the second source electrode layer 12.
In step S280, a drain electrode 13 is disposed on a side of the first conductivity type substrate 1 facing away from the first conductivity type drift region 2.
In one embodiment, the substrate may be thinned to 150 μm, and metal is deposited on the side of the substrate facing away from the drift region, and laser annealed to form an ohmic contact layer, i.e., the drain electrode 13.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A shielded gate trench transistor comprising:
a first conductivity type substrate;
a first conductive type drift region arranged on one side of the first conductive type substrate, and a gate trench arranged on one side of the first conductive type drift region away from the first conductive type substrate;
the second conductive type gate oxide protection layer is arranged at the bottom of the gate groove;
the first source electrode layer is arranged on one side of the second conductive type gate oxide protection layer, which is away from the first conductive type substrate, and forms ohmic contact with the first conductive type drift region;
the two Schottky contact areas are arranged on one side of the first source electrode layer, which is away from the second conductive type gate oxide protection layer, and the two Schottky contact areas are oppositely arranged on the side wall of the gate groove;
a shielding gate arranged between the two Schottky contact areas;
an oxide layer arranged on one side of the shielding gate away from the first source electrode layer;
a control gate surrounded by the oxide layer;
a source region which is arranged outside the side wall of the gate trench and is in contact with the oxide layer;
and the drain electrode is arranged on one side of the first conductive type substrate, which is away from the first conductive type drift region.
2. The shielded gate trench transistor of claim 1 wherein the source region comprises:
a second conductive type body region arranged outside the side wall of the gate trench;
a first conductivity type source region arranged on one side of the second conductivity type body region away from the first conductivity type drift region, wherein the first conductivity type source region is close to the gate trench;
a second conductivity type source region disposed side by side with the first conductivity type source region, and the second conductivity type source region being remote from the gate trench;
and a second source electrode layer forming ohmic contacts with the first and second conductive type source regions, respectively.
3. The shielded gate trench transistor of claim 1 wherein the second conductivity type gate oxide protection layer has a width that is not less than a width of the gate trench.
4. A shielded gate trench transistor according to any of claims 1-3 wherein the first conductivity type is N-type and the second conductivity type is P-type.
5. The shielded gate trench type transistor of claim 2 wherein the second conductivity type body region, the second conductivity type source region and the second conductivity type gate oxide protective layer are all obtained by means of aluminum ion implantation, wherein the second conductivity type body region is lightly doped and the second conductivity type source region is heavily doped; the first conduction type source region is obtained through nitrogen ion implantation, wherein the first conduction type source region is heavily doped.
6. The shielded gate trench transistor of claim 1 wherein the material of the oxide layer comprises silicon dioxide.
7. A method of fabricating a shielded gate trench transistor, comprising:
providing a first conductive type substrate;
a first conduction type drift region is arranged on one side of the first conduction type substrate, a source region and a gate trench are arranged on one side, away from the first conduction type substrate, of the first conduction type drift region, and the source region is positioned on two sides of the gate trench;
a second conductive type gate oxide protection layer is arranged at the bottom of the gate trench;
a first source electrode layer is arranged on one side, away from the first conductive type substrate, of the second conductive type gate oxide protection layer, so that ohmic contact is formed between the first source electrode layer and the first conductive type drift region;
two Schottky contact areas are arranged on one side, away from the second conductive type gate oxide protective layer, of the first source electrode layer, and the two Schottky contact areas are oppositely arranged on the side wall of the gate groove;
a shielding grid is arranged between the two Schottky contact areas;
an oxide layer is arranged on one side of the shielding grid away from the first source electrode layer;
manufacturing a control grid, wherein the control grid is wrapped by the oxide layer;
a drain is provided on a side of the first conductivity type substrate facing away from the first conductivity type drift region.
8. The method of manufacturing a shielded gate trench transistor of claim 7, wherein said source region manufacturing step comprises:
forming a second conductive type body region on one side of the first conductive type drift region, which is away from the first conductive type substrate, through ion implantation, wherein the second conductive type body region is arranged on the outer side of the side wall of the gate groove;
growing a semiconductor layer on one side of the second conductive type body region, which is away from the first conductive type drift region, and carrying out first conductive type ion implantation on a partial region of the semiconductor layer, which is close to the gate trench, so as to obtain a first conductive type source region;
performing second conductivity type ion implantation on a partial region of the semiconductor layer far away from the gate trench to obtain a second conductivity type source region, wherein the second conductivity type source region and the first conductivity type source region are arranged side by side and are in contact with each other;
and manufacturing a second source electrode layer, wherein the second source electrode layer forms ohmic contact with the first conductive type source region and the second conductive type source region respectively.
9. The method of manufacturing a shielded gate trench transistor of claim 8 wherein the first conductivity type ions comprise nitrogen ions and the second conductivity type ions comprise aluminum ions.
10. The method of fabricating a shielded gate trench transistor of claim 7, wherein the step of fabricating a control gate comprises:
depositing an oxide layer in the gate trench, wherein the oxide layer covers the Schottky contact area and the shielding gate;
forming a groove body by opening holes on the oxide layer, wherein the groove body and the shielding grid are separated by the oxide layer;
depositing a polysilicon layer in the groove body to serve as a control gate;
and depositing an oxide layer on the control gate again to fill up the gate trench.
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