CN117080269A - Silicon carbide MOSFET device and preparation method thereof - Google Patents
Silicon carbide MOSFET device and preparation method thereof Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 210
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 239000010410 layer Substances 0.000 claims abstract description 128
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 78
- 229920005591 polysilicon Polymers 0.000 claims abstract description 62
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 24
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- 238000005468 ion implantation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The application provides a silicon carbide MOSFET device and a preparation method thereof, comprising the following steps: the silicon carbide N-type epitaxial layer is arranged on the silicon carbide N-type current expansion layer; a silicon carbide P-type shielding layer is arranged in the silicon carbide N-type current expansion layer, P-type polysilicon is arranged at the top of the silicon carbide P-type shielding layer, and two ends and the bottom of the P-type polysilicon are in contact with the silicon carbide N-type current expansion layer; and a grid structure is arranged in the P-type polycrystalline silicon, and an interlayer dielectric layer is arranged at the top of the grid structure. Through the contact of the two ends and the bottom of the P-type polycrystalline silicon with the silicon carbide N-type current expansion layer, heterojunction contact with rectification characteristic is formed, and meanwhile, a plurality of current paths are formed, so that current concentration of the device under reverse continuous flow is avoided, and the reliability of the device is improved.
Description
Technical Field
The application relates to the field of power electronics, in particular to a silicon carbide MOSFET device and a preparation method thereof.
Background
The electric energy is an energy source which is economical, clean, convenient to transport and easy to convert. The power semiconductor device is used as a basic stone of power electronic technology and is also a core control element for realizing electric energy conversion and transmission, so that the performance of the power semiconductor device determines the electric energy efficiency. The development of the domestic power semiconductor device starts in the 60 th century, and starts from a simpler silicon-based power diode, and the development and manufacturing capabilities of silicon-based power thyristors, bipolar junction transistors, power MOSFETs, insulated gate bipolar transistors and other devices are already provided. With the continuous innovation and iterative update of device structure design and the fine development of manufacturing process, silicon-based power semiconductor devices are still mainstream devices at present, but the performance of the silicon-based power semiconductor devices is gradually approaching the limit of silicon-based materials.
The development of power semiconductor devices is still aimed at increasing switching speed, reducing energy loss, increasing power density, etc. to be suitable for application demands of high power and high frequency. The third generation wide bandgap semiconductor material represented by silicon carbide (SiC) has a larger bandgap width, higher critical breakdown electric field strength, higher electron saturation drift velocity and higher thermal conductivity than silicon-based materials, and can be applied to the fields of high temperature, high frequency, high power and the like.
Silicon carbide metal oxide semiconductor field effect transistors (silicon carbide MOSFETs) combine the advantages of silicon carbide materials with the advantages of high switching speed, simple driving and the like of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and have been widely studied and applied. The trench gate silicon carbide MOSFET has high channel mobility due to low vertical crystal face defect density, eliminates the advantages of a parasitic junction field effect transistor structure, and has larger on-current density. However, the bottom of the trench gate is easy to generate an electric field concentration effect to influence the reliability of the gate dielectric, so that the device fails in advance.
In addition, the turn-on voltage of the parasitic body diode (PIN diode) in silicon carbide MOSFET devices is high, and there is a storage of minority carriers during turn-off of the PIN diode, resulting in longer reverse recovery time and larger losses. Accordingly, current silicon carbide MOSFET devices are typically either antiparallel with a schottky diode in the application or integrated with a schottky diode in the silicon carbide MOSFET device. However, the silicon carbide MOSFET integrated with the schottky diode has a large reverse leakage current when the device is in a reverse withstand voltage. Some of the above problems have limited practical applications for silicon carbide MOSFET devices.
Disclosure of Invention
In view of the above problems, the present application has been made to provide a silicon carbide MOSFET device and a method of manufacturing the same, which overcomes the problems or at least partially solves the problems, including:
a silicon carbide MOSFET device comprises a drain metal layer, a silicon carbide N-type substrate layer, a silicon carbide N-type epitaxial layer and a silicon carbide N-type current expansion layer which are sequentially stacked;
a silicon carbide P-type shielding layer is arranged in the silicon carbide N-type current expansion layer, P-type polysilicon is arranged at the top of the P-type shielding layer, and two ends and the bottom of the P-type polysilicon are in contact with the silicon carbide N-type current expansion layer; and a grid structure is arranged in the P-type polycrystalline silicon, and an interlayer dielectric layer is arranged at the top of the grid structure.
Further, a silicon carbide P-type well region is arranged at the top of the silicon carbide N-type current expansion layer, a silicon carbide N-type source region and a silicon carbide P-type contact region are arranged at the top of the silicon carbide P-type well region, and source contact metal is arranged above the silicon carbide N-type source region and the silicon carbide P-type contact region.
Further, the P-type polysilicon penetrates through the gate structure, and the middle and bottom of the gate structure are covered by the P-type polysilicon.
Further, the gate structure comprises a gate medium and a polysilicon gate arranged in the gate medium, the top of the polysilicon gate is in contact with the interlayer dielectric layer, and other surfaces of the polysilicon gate are wrapped by the gate medium.
Further, at least one silicon carbide P-type shielding layer is arranged at each of two bottom corners of the P-type polysilicon, and the silicon carbide P-type shielding layers are not contacted with each other.
Further, the width of the interval between the plurality of silicon carbide P-type shielding layers positioned at the same bottom angle of the P-type polysilicon is 0.3 μm-0.8 μm.
Further, the thickness of the P-type polycrystalline silicon is 1-2 mu m, and the thickness of the P-type polycrystalline silicon is larger than that of the grid electrode structure.
Further, the thickness of the silicon carbide N-type current expansion layer is 0.5-1.5 mu m.
A method of making a silicon carbide MOSFET device, the method for making a silicon carbide MOSFET as set forth in any one of the preceding claims, comprising:
generating a silicon carbide N-type epitaxial layer on the silicon carbide N-type substrate layer according to preset conditions and processes, generating a silicon carbide N-type current expansion layer on the silicon carbide N-type epitaxial layer, and generating a silicon carbide P-type well region on the silicon carbide N-type current expansion layer;
arranging an implantation mask according to a preset structure, and sequentially implanting a silicon carbide P-type contact region, a silicon carbide N-type source region and a silicon carbide P-type shielding layer through the implantation mask; before the silicon carbide P-type shielding layer is implanted, etching a silicon carbide groove according to a preset structure;
p-type polycrystalline silicon is deposited in the silicon carbide groove, and the polycrystalline silicon groove is formed by etching according to a preset structure; setting a gate dielectric and a polysilicon gate in the polysilicon trench;
generating an interlayer dielectric layer through deposition and etching processes, stripping metal and performing rapid thermal annealing to form source electrode contact metal;
evaporating metal on the top of the device, etching to form a metal pad, sputtering metal on the bottom of the device, and annealing to form a drain metal layer, thereby completing the preparation.
The application has the following advantages:
in the embodiment of the application, compared with the silicon carbide MOSFET device in the prior art, which has lower reliability of a parasitic PIN diode and larger reverse leakage current of an integrated Schottky diode, the application provides a solution of integrating a heterojunction diode, which comprises the following steps: the silicon carbide N-type epitaxial layer is arranged on the silicon carbide N-type current expansion layer; a silicon carbide P-type shielding layer is arranged in the silicon carbide N-type current expansion layer, P-type polysilicon is arranged at the top of the silicon carbide P-type shielding layer, and two ends and the bottom of the P-type polysilicon are in contact with the silicon carbide N-type current expansion layer; and a grid structure is arranged in the P-type polycrystalline silicon, and an interlayer dielectric layer is arranged at the top of the grid structure. Through the contact of the two ends and the bottom of the P-type polycrystalline silicon with the silicon carbide N-type current expansion layer, heterojunction contact with rectification characteristic is formed, and meanwhile, a plurality of current paths are formed, so that current concentration of the device under reverse continuous flow is avoided, and the reliability of the device is improved.
Drawings
For a clearer description of the technical solutions of the present application, the drawings that are needed in the description of the present application will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art;
fig. 1 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a silicon carbide MOSFET device with multiple silicon carbide P-type shielding layers according to an embodiment of the present application;
fig. 3 is a flow chart illustrating steps of a method for forming a silicon carbide MOSFET device according to an embodiment of the application;
fig. 4 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present application after forming a silicon carbide N-type epitaxial layer;
fig. 5 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present application after forming a silicon carbide N-type current spreading layer;
fig. 6 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present application after forming a silicon carbide P-type well region;
fig. 7 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present application after forming a silicon carbide P-type contact region;
FIG. 8 is a schematic diagram of a silicon carbide MOSFET device according to an embodiment of the present application after forming a silicon carbide N-type source region;
fig. 9 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present application after forming a silicon carbide trench;
fig. 10 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present application after forming a silicon carbide P-type shield layer;
fig. 11 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present application after forming P-type polysilicon;
fig. 12 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present application after forming a polysilicon trench;
fig. 13 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present application after forming a gate dielectric and a polysilicon gate;
fig. 14 is a schematic diagram of a silicon carbide MOSFET device according to an embodiment of the application after source contact metal is formed;
fig. 15 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present application after forming a drain metal layer.
Reference numerals illustrate:
1: a silicon carbide N-type substrate layer; 2: silicon carbide N-type epitaxial layers; 3: silicon carbide N-type current expansion layer; 4: silicon carbide P-type well region; 5: silicon carbide P-type contact regions; 6: a silicon carbide N-type source region; 7: a silicon carbide P-type shielding layer; 8: p-type polycrystalline silicon; 9: a gate dielectric; 10: a polysilicon gate; 11: an interlayer dielectric layer; 12: a source contact metal; 13: a metal pad;14: a drain metal layer; 51: a first implant mask; 61: a second implant mask; 72: a third injection mask; 71: a first etching mask; 81: and etching the mask plate.
Detailed Description
In order that the manner in which the above recited objects, features and advantages of the present application are obtained will become more readily apparent, a more particular description of the application briefly described above will be rendered by reference to the appended drawings. It will be apparent that the described embodiments are some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The inventors found by analyzing the prior art that: the traditional planar gate silicon carbide MOSFET greatly limits the on-current density due to the low channel mobility and parasitic junction field effect transistor structure, and meanwhile, when the device is in reverse withstand voltage, the electric field concentration effect at the Schottky contact metal of the silicon carbide MOSFET integrating the Schottky diode can reduce the Schottky barrier, so that larger reverse leakage current is caused.
Referring to fig. 1, a silicon carbide MOSFET device according to an embodiment of the present application is shown, which includes a drain metal layer 14, a silicon carbide N-type substrate layer 1, a silicon carbide N-type epitaxial layer 2, and a silicon carbide N-type current spreading layer 3, which are stacked in this order; a silicon carbide P-type shielding layer 7 is arranged in the silicon carbide N-type current expansion layer 3, P-type polysilicon 8 is arranged at the top of the silicon carbide P-type shielding layer 7, and two ends and the bottom of the P-type polysilicon 8 are in contact with the silicon carbide N-type current expansion layer 3; a gate structure is arranged in the P-type polysilicon 8, and an interlayer dielectric layer 11 is arranged on the top of the gate structure.
It should be noted that the present application structurally implements the integration of a polysilicon/silicon carbide heterojunction diode. The on voltage of the parasitic PIN diode in the traditional silicon carbide MOSFET device is high (generally about 3V), and the PIN diode is a bipolar device, and longer reverse recovery time and larger turn-off loss are caused by carrier storage effect in the turn-off process. The silicon carbide MOSFET integrated with the Schottky diode forms a conduction voltage of 0.6V-2V by adjusting metal types and processes, and the conduction loss of the device in reverse conduction is reduced, but the barrier reduction effect exists at the Schottky contact position of the device in a reverse withstand voltage state, so that the reverse leakage current is larger. The turn-on voltage of the integrated polysilicon/silicon carbide heterojunction diode is similar to that of the integrated schottky diode. In addition, the integrated polysilicon/silicon carbide heterojunction integrated Schottky diode is a multi-sub device and has better reverse recovery characteristic.
In the embodiment of the application, compared with the silicon carbide MOSFET device in the prior art, which has lower reliability of a parasitic PIN diode and larger reverse leakage current of an integrated Schottky diode, the application provides a solution of integrating a heterojunction diode, which comprises the following steps: the silicon carbide N-type epitaxial layer comprises a drain metal layer 14, a silicon carbide N-type substrate layer 1, a silicon carbide N-type epitaxial layer 2 and a silicon carbide N-type current expansion layer 3 which are sequentially stacked; a silicon carbide P-type shielding layer 7 is arranged in the silicon carbide N-type current expansion layer 3, P-type polysilicon 8 is arranged at the top of the silicon carbide P-type shielding layer 7, and two ends and the bottom of the P-type polysilicon 8 are in contact with the silicon carbide N-type current expansion layer 3; a gate structure is arranged in the P-type polysilicon 8, and an interlayer dielectric layer 11 is arranged on the top of the gate structure. Through the contact of the two ends and the bottom of the P-type polycrystalline silicon 8 and the silicon carbide N-type current expansion layer, heterojunction contact with rectification characteristic is formed, and meanwhile, a plurality of current paths are formed, so that the current concentration of the device under reverse continuous flow is avoided, and the reliability of the device is improved.
Next, a silicon carbide MOSFET device and a method of manufacturing the same in this exemplary embodiment will be further described.
In an embodiment of the present application, a silicon carbide P-type well region 4 is disposed on top of the silicon carbide N-type current expansion layer 3, a silicon carbide N-type source region 6 and a silicon carbide P-type contact region 5 are disposed on top of the silicon carbide P-type well region 4, and a source contact metal 12 is disposed above the silicon carbide N-type source region 6 and the silicon carbide P-type contact region 5.
In an embodiment of the present application, the P-type polysilicon 8 penetrates through the gate structure, and the middle and bottom of the gate structure are covered by the P-type polysilicon 8.
In one implementation, the gate structure is a split gate structure.
In one embodiment of the present application, the gate structure includes a gate dielectric 9 and a polysilicon gate 10 disposed inside the gate dielectric 9, the top of the polysilicon gate 10 is in contact with the interlayer dielectric layer 11, and other surfaces of the polysilicon gate 10 are wrapped by the gate dielectric 9.
It should be noted that, the scheme realizes the split gate structure, reduces the overlapping area of the gate and the drain, thereby reducing the gate-drain capacitance, improving the switching capacity of the device and realizing lower switching loss.
In an embodiment of the present application, at least one of the silicon carbide P-type shielding layers 7 is disposed at two bottom corners of the P-type polysilicon 8, and the silicon carbide P-type shielding layers 7 are not in contact with each other.
It should be noted that, the plurality of silicon carbide P-type shielding layers 7 may be regarded as a silicon carbide MOSFET device formed by dividing one silicon carbide P-type shielding layer 7 into a plurality of discontinuous portions and disposing the discontinuous portions near the bottom corners of the P-type polysilicon 8, and referring to fig. 2, a plurality of silicon carbide P-type shielding layers 7 are disposed near each bottom corner of the P-type polysilicon 8. The separated silicon carbide P-type shielding layer can be used for increasing the contact between polysilicon and silicon carbide to form a plurality of current paths, so that the current concentration of the device under the reverse follow-up flow is avoided, and the reliability of the device is improved.
In one embodiment of the present application, the width of the space between the P-type shielding layers 7 of silicon carbide located at the same bottom corner of the P-type polysilicon 8 is 0.3 μm to 0.8 μm.
The silicon carbide P-type shielding layers 7 are not in contact with each other, are discontinuous with each other, have a space therebetween, and form a device with a plurality of current paths, wherein the width between the silicon carbide P-type shielding layers is 0.3-0.8 μm, and the thickness of the silicon carbide P-type shielding layers 7 is 0.1-0.5 μm, so that the silicon carbide MOSFET device is ensured to be optimal.
In an embodiment of the present application, the thickness of the P-type polysilicon 8 is 1 μm-2 μm, and the thickness of the P-type polysilicon 8 is greater than the thickness of the gate structure.
In an embodiment of the present application, a metal pad is disposed on top of the silicon carbide mosfet.
The metal pad forms a metal region on the device for connecting the chip pins with external circuits.
In one embodiment of the present application, the silicon carbide N-type current spreading layer has a thickness of 0.5 μm to 1.5 μm. The thickness of the silicon carbide N-type epitaxial layer 2 is 6-12 mu m. The thickness of the polysilicon gate 10 is 0.8-1.8 mu m, and the thickness of the gate dielectric 9 is 20-80 nm. The thickness of the silicon carbide P-type well region 4 is 0.5-1 mu m, the thickness of the silicon carbide N-type source region 6 is 0.2-0.3 mu m, and the thickness of the silicon carbide P-type contact region 5 is 0.2-0.3 mu m.
Referring to fig. 3, there is shown a method of fabricating a silicon carbide metal-oxide semiconductor field effect transistor device for fabricating a silicon carbide metal-oxide semiconductor field effect transistor as defined in any one of the preceding claims, comprising:
s110, generating a silicon carbide N-type epitaxial layer on a silicon carbide N-type substrate layer according to preset conditions and a process, generating a silicon carbide N-type current expansion layer on the silicon carbide N-type epitaxial layer, and generating a silicon carbide P-type well region on the silicon carbide N-type current expansion layer;
s120, arranging an implantation mask according to a preset structure, and sequentially implanting a silicon carbide P-type contact region, a silicon carbide N-type source region and a silicon carbide P-type shielding layer through the implantation mask; before the silicon carbide P-type shielding layer is implanted, etching a silicon carbide groove according to a preset structure;
s130, depositing P-type polycrystalline silicon in the silicon carbide groove, and etching according to a preset structure to form a polycrystalline silicon groove; setting a gate dielectric and a polysilicon gate in the polysilicon trench;
s140, generating an interlayer dielectric layer through a deposition and etching process, stripping metal and performing rapid thermal annealing to form source electrode contact metal;
and S150, evaporating metal at the top of the device, etching to form a metal pad, sputtering metal at the bottom of the device, and annealing to form a drain metal layer, thereby completing the preparation.
As an example, a silicon carbide MOSFET device is prepared by:
a silicon carbide N-type epitaxial layer 2 is formed on a silicon carbide N-type substrate layer 1 by an epitaxial growth process, as shown in fig. 4.
A silicon carbide N-type current spreading layer 3 is formed on the silicon carbide N-type epitaxial layer 2 by an epitaxial growth process or a high-energy nitrogen ion implantation process, as shown in fig. 5.
A silicon carbide P-type well region 4 is formed on the silicon carbide N-type current spreading layer 4 by an epitaxial growth process or a high-energy aluminum ion implantation process, as shown in fig. 6.
A first implantation mask 51 is arranged on the device structure, and ion implantation is performed through the first implantation mask 51 to form a silicon carbide P-type contact region 5, as shown in fig. 7. In this embodiment, the silicon carbide P-type contact region 5 is a heavily doped region.
And removing the first implantation mask 51, arranging a second implantation mask 61 on the device structure, and performing ion implantation through the second implantation mask 61 to form a silicon carbide N-type source region 6, as shown in fig. 8. In this embodiment, the silicon carbide N-type source region 6 is a heavily doped region.
Removing the second implantation mask 61, arranging a first etching mask 71 on the device structure, and etching the first etching mask to form silicon carbide grooves with specified dimensions, as shown in fig. 9
The first etching mask 71 is removed, a third implantation mask 72 is arranged on the device structure, and aluminum ion implantation is performed through the third implantation mask 72 to form a silicon carbide P-type shielding layer 7, as shown in fig. 10. In the present embodiment, the thickness of the silicon carbide P-type shielding layer 7 is 0.1 μm to 0.5 μm. And the silicon carbide P-type shielding layer 7 is of a discontinuous structure, and the interval width is 0.3-0.8 mu m.
The third implantation mask 72 is removed, P-type polysilicon 8 is deposited in the silicon carbide trench, and the excess P-type polysilicon 8 is removed by surface planarization, as shown in fig. 11.
A second etching mask 81 is arranged on the device structure, and a polysilicon trench with a specified size is formed by etching through the second etching mask 81, as shown in fig. 12.
The second etching mask 81 is removed, the gate dielectric 9 is formed by thermal oxidation in the polysilicon trench and the polysilicon gate 10 is formed by filling, or the gate dielectric 9 and the polysilicon gate 10 are formed by filling by deposition in sequence, and then the surface is planarized, as shown in fig. 13.
An interlayer dielectric layer 11 is formed on the device structure by a deposition, etching process as an isolation, the metal is stripped and a rapid thermal anneal is performed to form a source contact metal 12, as shown in fig. 14.
Metal is evaporated and etched on the front side to form metal pad13, and then sputtered on the back side and annealed to form drain metal layer 14, completing the fabrication as shown in fig. 15.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The above description has been made in detail for a semiconductor field effect transistor device and a method for manufacturing the same, and specific examples are applied herein to illustrate the principles and embodiments of the present application, the above examples are only for helping to understand the method and core ideas of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (9)
1. The silicon carbide MOSFET device is characterized by comprising a drain electrode metal layer, a silicon carbide N-type substrate layer, a silicon carbide N-type epitaxial layer and a silicon carbide N-type current expansion layer which are sequentially stacked;
a silicon carbide P-type shielding layer is arranged in the silicon carbide N-type current expansion layer, P-type polysilicon is arranged at the top of the silicon carbide P-type shielding layer, and two ends and the bottom of the P-type polysilicon are in contact with the silicon carbide N-type current expansion layer; and a grid structure is arranged in the P-type polycrystalline silicon, and an interlayer dielectric layer is arranged at the top of the grid structure.
2. The silicon carbide MOSFET device of claim 1, wherein a silicon carbide P-type well region is provided atop the silicon carbide N-type current spreading layer, a silicon carbide N-type source region and a silicon carbide P-type contact region are provided atop the silicon carbide P-type well region, and a source contact metal is provided above the silicon carbide N-type source region and the silicon carbide P-type contact region.
3. The silicon carbide MOSFET device of claim 1, wherein the P-type polysilicon extends through the gate structure, and wherein both a middle and bottom of the gate structure are covered by the P-type polysilicon.
4. The silicon carbide MOSFET device of claim 1, wherein the gate structure comprises a gate dielectric and a polysilicon gate disposed within the gate dielectric, the top of the polysilicon gate being in contact with the interlayer dielectric layer, the polysilicon gate being surrounded by the gate dielectric on other sides.
5. The silicon carbide MOSFET device of claim 1, wherein at least one of said silicon carbide P-type shield layers is disposed at each of said two bottom corners of said P-type polysilicon, said silicon carbide P-type shield layers being non-contacting each other.
6. The silicon carbide MOSFET device of claim 5, wherein a width of a gap between a plurality of said silicon carbide P-type shield layers at a same bottom corner of said P-type polysilicon is between 0.3 μm and 0.8 μm.
7. The silicon carbide MOSFET device of claim 1, wherein the P-type polysilicon has a thickness of 1 μιη -2 μιη and the P-type polysilicon thickness is greater than the gate structure thickness.
8. The silicon carbide MOSFET device of claim 1, wherein the silicon carbide N-type current spreading layer has a thickness of 0.5 μm to 1.5 μm.
9. A method of making a silicon carbide MOSFET device according to any one of claims 1-8, comprising:
generating a silicon carbide N-type epitaxial layer on the silicon carbide N-type substrate layer according to preset conditions and processes, generating a silicon carbide N-type current expansion layer on the silicon carbide N-type epitaxial layer, and generating a silicon carbide P-type well region on the silicon carbide N-type current expansion layer;
arranging an implantation mask according to a preset structure, and sequentially implanting a silicon carbide P-type contact region, a silicon carbide N-type source region and a silicon carbide P-type shielding layer through the implantation mask; before the silicon carbide P-type shielding layer is implanted, etching a silicon carbide groove according to a preset structure;
p-type polycrystalline silicon is deposited in the silicon carbide groove, and the polycrystalline silicon groove is formed by etching according to a preset structure; setting a gate dielectric and a polysilicon gate in the polysilicon trench;
generating an interlayer dielectric layer through deposition and etching processes, stripping metal and performing rapid thermal annealing to form source electrode contact metal;
evaporating metal on the top of the device, etching to form a metal pad, sputtering metal on the bottom of the device, and annealing to form a drain metal layer, thereby completing the preparation.
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