CN111276545B - Novel groove silicon carbide transistor device and manufacturing method thereof - Google Patents

Novel groove silicon carbide transistor device and manufacturing method thereof Download PDF

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CN111276545B
CN111276545B CN202010087560.0A CN202010087560A CN111276545B CN 111276545 B CN111276545 B CN 111276545B CN 202010087560 A CN202010087560 A CN 202010087560A CN 111276545 B CN111276545 B CN 111276545B
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conductive type
epitaxial layer
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silicon carbide
well region
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CN111276545A (en
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郑柳
何钧
刘敏
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Chongqing Weitesen Electronic Technology Co ltd
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Abstract

A novel groove silicon carbide transistor device and a manufacturing method thereof are provided, on the basis of MOSFET or IGBT, the edge of a main junction is etched into a double-mesa shape by means of etching and the like, and the double-mesa shape is respectively a second conductive type well region mesa and an epitaxial layer mesa, so that the purpose of changing the appearance of the junction edge in the device is achieved, the electric field distribution of the surface near the junction is improved, the electric field concentration near the junction edge is relieved, the reverse breakdown voltage of the device is improved, and the voltage resistance and the reliability of the device are improved. Under the condition of not increasing the cell area of the device, the electric field aggregation of the gate dielectric layer is reduced, and the breakdown voltage of the device is improved.

Description

Novel groove silicon carbide transistor device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a novel groove silicon carbide transistor device and a manufacturing method thereof.
Background
With the rapid development of power electronic technology, the demand of high-power semiconductor devices is more and more remarkable. Due to the limitation of materials, the characteristics of the conventional silicon device reach the theoretical limit, and silicon carbide, which is one of the wide bandgap semiconductor materials rapidly developed in the last ten years, has the advantages of wide bandgap, high thermal conductivity, high carrier saturation mobility, high power density and the like, and can be applied to the application fields of high power, high temperature, radiation resistance and the like.
Among silicon carbide semiconductor devices, vertical trench silicon carbide transistors have a nonpolar surface on the channel surface, and have higher mobility and higher cell integration, so that the trench silicon carbide transistors become a key research object of next-generation power electronic devices, and can be widely applied to the fields of electric vehicles, charging piles, uninterruptible power supplies, smart grids and the like.
However, the critical breakdown electric field of the silicon carbide in the trench-type silicon carbide transistor is large, so that the electric field concentration phenomenon in the gate dielectric is serious, and the gate dielectric layer with high electric field concentration is easy to break down under a small reverse voltage.
Disclosure of Invention
The invention aims to provide a novel structure of a groove silicon carbide transistor, which has a double-mesa structure compared with a traditional device, and changes the appearance of a junction edge in the device, thereby improving the electric field distribution of the surface near the junction and relieving the electric field concentration near the junction edge.
The invention also aims to provide a manufacturing method of the novel groove silicon carbide transistor device.
The invention aims to realize the technical scheme, and the novel groove silicon carbide transistor device comprises a first conduction type SiC epitaxial layer with a convex-shaped structure on the cross section;
a first conductive type SiC buffer layer, a SiC semiconductor substrate and a drain electrode are sequentially arranged at the lower part of the first conductive type SiC epitaxial layer;
the groove is formed in the middle of the boss of the first conductive type SiC epitaxial layer;
the second conduction type well region and the first conduction type source region are arranged on the upper part of the first conduction type SiC epitaxial layer boss from bottom to top and are positioned on two sides of the groove;
the insulating medium film is arranged at the bottom of the groove;
an oxide film formed by oxidizing the sidewall of the trench;
a gate source isolation dielectric film arranged on the upper part of the trench;
a gate electrode which is arranged in the groove and is coated by the gate source isolation medium film, an oxidation film formed by oxidizing the side wall of the groove and an insulation medium film, and the gate electrode is flush with the first conduction type source region;
the base regions are arranged on two sides of the boss of the first conductive type SiC epitaxial layer and correspond to the corner of the boss;
the source electrode covers the base region, the second conductive type well region, the first conductive type source region and the grid source isolation medium film (20);
the conductive types are divided into an N type and a P type, and the first conductive type is opposite to the doping type of the second conductive type.
Another object of the present invention is achieved by the above technical solution, which provides a method for manufacturing a novel trench silicon carbide transistor device, specifically comprising the following steps:
step S1: selecting a semiconductor epitaxial wafer consisting of a SiC semiconductor substrate (11), a first conductive type SiC buffer layer (12) and a first conductive type SiC epitaxial layer (13), and forming a second conductive type well region on the upper surface of the first conductive type SiC epitaxial layer through secondary epitaxy or ion implantation;
step S2: forming a first conductive type source region on the upper surface of the second conductive type well region through secondary epitaxy or ion implantation;
and step S3: photoetching and etching the second conductive type well region and two sides of the first conductive type source region, wherein the device is in a convex structure after the etching is finished, the two sides of the first conductive type source region are completely etched, and part of the second conductive type well region, the bottoms of which are in contact with the first conductive type SiC epitaxial layer, is reserved;
and step S4: photoetching and etching the table tops on the two sides of the convex structure formed in the step S3 again, wherein the device is in a double-table top after etching is finished, one table top is a second conductive type well region table top, and the other table top is an epitaxial layer table top;
step S5: performing arc treatment on the corner of the epitaxial layer table top;
step S6: carrying out ion implantation mask deposition, photoetching, ion implantation mask etching and ion implantation on the second conductivity type well region table board, the epitaxial layer table board and the side wall between the second conductivity type well region table board and the epitaxial layer table board to form a base region corresponding to the corner of the epitaxial layer (13) table board;
step S7: photoetching and etching the middle part of the lug boss on the upper surface of the convex epitaxial layer by adopting a photoetching technology to form a groove penetrating through the second conductive type well region and the first conductive type source region;
step S8: growing an insulating medium film on the bottom of the groove;
step S9: performing high-temperature oxidation on the side wall of the groove to oxidize the first conductive type SiC epitaxial layer, the second conductive type well region and the first conductive type source region on the side wall of the groove to form an oxidation film;
step S10: filling the blank area in the groove with a gate electrode, wherein the upper surface of the gate electrode is not lower than that of the first conductive type source area;
step S11: forming a gate source isolation dielectric film completely covering the upper surface of the gate electrode and part of the first conduction type source region above the gate electrode, wherein the width of the gate source isolation dielectric film is smaller than that of the first conduction type source region;
step S12: and forming a drain electrode on the lower surface of the SiC substrate and forming a source electrode covering the base region, the second conductive type well region, the first conductive type source region of the first conductive type and the grid source isolation medium film on the upper surface of the device.
By adopting the manufacturing method of the invention, the edge of the main junction is etched into a mesa shape by means of etching and the like, and the appearance of the junction edge in the device is changed, so that the electric field distribution of the surface near the junction is improved, the electric field concentration near the junction edge is relieved, the reverse breakdown voltage of the device is improved, and the voltage resistance and the reliability of the device are improved. Under the condition of not increasing the cell area of the device, the electric field aggregation of the gate dielectric layer is reduced, and the breakdown voltage of the device is improved.
Drawings
Fig. 1 is a schematic structural diagram after step S1 is completed.
Fig. 2 is a schematic structural diagram after step S2 is completed.
Fig. 3 is a schematic structural diagram after step S3 is completed.
Fig. 4 is a schematic structural diagram after step S4 is completed.
Fig. 5 is a schematic structural diagram after step S6 is completed.
Fig. 6 is a schematic structural diagram after step S7 is completed.
Fig. 7 is a schematic structural diagram after step S8 is completed.
Fig. 8 is a schematic structural diagram after step S9 is completed.
Fig. 9 is a schematic structural diagram after step S12 is completed.
A SiC semiconductor substrate; 12. a first conductivity type SiC buffer layer; 13. a first conductivity type SiC epitaxial layer; 14. a source region double-mesa structure; 15. a base region; 16. a first conductivity type source region; 17. a second conductivity type well region; 18. a dielectric film; 180. an insulating dielectric film; 181. oxidizing the thin film; 19. a gate electrode; 20. a gate-source isolation dielectric layer; 21. a source electrode; 22. and a drain electrode.
Detailed Description
The trench silicon carbide IGBT structure and the method for manufacturing the same according to the present invention will be described in detail below with reference to the accompanying drawings and the detailed description.
Example 1
A novel groove silicon carbide transistor device comprises an N-type SiC epitaxial layer 13 with a convex-shaped structure in cross section and subjected to arc treatment at the corners of table tops on two sides;
an N-type SiC buffer layer 12, an N-type SiC substrate 11 and a drain electrode 22 are sequentially arranged below the N-type SiC epitaxial layer 13 from top to bottom in the cross section of the trench silicon carbide transistor device;
the groove is arranged in the middle of the boss of the N-type SiC epitaxial layer 13;
the P-type well region 17 and the N-type source region 16 are arranged on the upper part of the boss of the N-type SiC epitaxial layer 13 from bottom to top and are positioned on two sides of the groove;
an insulating dielectric film 180 disposed at the bottom of the trench;
an oxide film 181 formed by oxidizing the sidewall of the trench;
a gate source isolation dielectric film 20 disposed on the upper portion of the trench; a gate electrode 19 which is arranged in the trench and is covered by the gate source isolation dielectric film 20, an oxidation film 181 formed by oxidizing the side wall of the trench and an insulation dielectric film 180, and the gate electrode 19 is flush with the N-type source region 16;
base regions 15 which are arranged on two sides of the lug boss of the N-type SiC epitaxial layer 13 and correspond to the corner of the lug boss;
a source electrode 21 covering the base region 15, the P-type well region 17, the N-type source region 16 and the gate-source isolation dielectric film 20;
further, the crystal form of the SiC epitaxial wafer is 4H-SiC or 6H-SiC or 3C-SiC, the thickness of the whole SiC epitaxial wafer is 1-800 μm, wherein the thickness of the SiC substrate 11 is 0.1-500um, the thickness of the SiC buffer layer 12 is 0.1-100um, and the thickness of the SiC epitaxial layer 13 is 0.1-500 um.
Further, the N-type doping impurity is nitrogen (N) or phosphorus (P); the P-type doping impurity is aluminum (Al) or boron (B) with a doping concentration of 1 × 10 14 -5×10 21 cm -3 。
Further, the source region 16 and the well region 17 are each 0.1um to 100um thick.
Further, the widths of the P-type well region 17 and the N-type source region 16 are equal and smaller than the width of the boss of the N-type SiC epitaxial layer 13, and the width of the gate-source isolation medium film 20 is smaller than the width of the N-type source region 16.
Further, the gate-source isolation dielectric film 20 and the insulating dielectric film 180 are made of one or more of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.
The manufacturing method for realizing the novel groove silicon carbide transistor device structure comprises the following steps:
step S1: selecting a semiconductor epitaxial wafer consisting of an N-type SiC substrate 11, a first conductive type N-type SiC buffer layer 12 and an N-type SiC epitaxial layer 13, and forming a P-type well region 17 on the upper surface of the N-type SiC epitaxial layer 13 through secondary epitaxy or ion implantation, as shown in fig. 1 specifically;
step S2: forming an N-type source region 16 on the upper surface of the P-type well region 17 by secondary epitaxy or ion implantation, as shown in fig. 2;
and step S3: photoetching and etching two sides of the P-type well region 17 and the N-type source region 16, wherein the device is in a convex structure after the etching is finished, the two sides of the N-type source region 16 are completely etched, and the part of the P-type well region 17, which is in contact with the N-type SiC epitaxial layer 13, on the two sides of the bottom is reserved, as shown in fig. 3 specifically;
and step S4: photoetching and etching the table tops on the two sides of the convex structure formed in the step S3 again, wherein the device is in a double-table top 14 after the etching is finished, one table top is a P-type well region 17 table top, and the other table top is an epitaxial layer 13 table top, as shown in fig. 4 specifically;
step S5: performing arc treatment on the corner of the table top of the epitaxial layer 13;
step S6: performing ion implantation mask deposition, photoetching, ion implantation mask etching and ion implantation on the mesa of the P-type well region 17, the mesa of the epitaxial layer 13 and the side wall between the mesa of the P-type well region 17 and the mesa of the epitaxial layer 13 to form a base region 15 corresponding to the corner of the mesa of the N-type SiC epitaxial layer 13, as shown in fig. 5 specifically;
step S7: photoetching and etching the boss center on the upper surface of the convex epitaxial layer 13 by adopting a photoetching and etching technology to form a groove penetrating through the P-type well region 17 and the N-type source region 16, as shown in fig. 6 specifically;
step S8: growing an insulating dielectric film 180 on the bottom of the trench, as shown in fig. 7;
step S9: performing high-temperature oxidation on the side wall of the trench, so that the N-type SiC epitaxial layer 13, the P-type well region 17 and the N-type source region 16 on the side wall of the trench are all oxidized to form an oxide film 181, as shown in fig. 8 specifically;
step S10: filling the blank area in the groove with a gate electrode 19, wherein the upper surface of the gate electrode 19 is not lower than the upper surface of the N-type source region 16;
step S11: forming a gate-source isolation dielectric film 20 which completely covers the upper surface of the gate electrode 19 and part of the N-type source region 16 above the gate electrode 19, wherein the width of the gate-source isolation dielectric film 20 is smaller than that of the N-type source region 16;
step S12: a drain electrode 22 is formed on the lower surface of the SiC substrate 11 and a source electrode 21 is formed on the upper surface of the device to cover the base region 15, the P-type well region 17, the N-type source region 16 and the gate-source isolation dielectric film 20, as shown in fig. 9.
Further, the base region15 ion implantation material is N, P, B or Al, the energy of the ion implantation is 10Kev-15Mev, the temperature of the ion implantation is 22-1000 ℃, and the dosage of the ion implantation is 1 multiplied by 10 10 -5×10 16 cm -2 。
Further, the thickness of the oxide film 181 formed on the side wall of the trench is 0.01um to 1um, and the thickness of the oxide film 181 is smaller than half of the width of the trench.
Further, the thickness of the insulating dielectric film 180 formed at the bottom of the trench is 0.01um-200um, and the thickness of the insulating dielectric film 180 is smaller than the depth of the trench.
Further, the source electrode 21 and the drain electrode 22 are metal thin films of Ti, ni, al, cu, au, ag, mo, W, tiW, tiC, fe, cr, etc., metal silicides formed by reacting metal with silicon carbide through high temperature treatment, or other conductive materials, and the thickness of the thin films is 0.001um to 10um.
Furthermore, in the photoetching technology and the wet method or dry method etching technology, the pattern of the mask plate is an interdigital structure or a parallel long strip-shaped or polygonal table top or a combined pattern of the interdigital structure and the parallel long strip-shaped or polygonal table top, the width of a window area is 0.01-200 mu m, the etching depth is 0.01-200 mu m, and the width of the table top area is 0.01-200 mu m; wherein the length of the parallel long strip patterns and the interdigital patterns is 0.01 mu m-20cm.
Example 2
A novel groove silicon carbide transistor device comprises a P-type SiC epitaxial layer 13 with a convex-shaped structure on the cross section and arc-shaped corners of table tops on two sides;
a P-type SiC buffer layer 12, a P-type SiC substrate 11 and a drain electrode 22 which are arranged below the P-type SiC epitaxial layer 13 in sequence from top to bottom in a cross-sectional view of the trench silicon carbide transistor device;
the groove is arranged in the middle of the boss of the P-type SiC epitaxial layer 13;
the N-type well region 17 and the P-type source region 16 are arranged on the upper part of the boss of the P-type SiC epitaxial layer 13 from bottom to top and are positioned on two sides of the groove;
an insulating dielectric film 180 disposed at the bottom of the trench;
an oxide film 181 formed by oxidizing the sidewall of the trench;
a gate source isolation dielectric film 20 arranged on the upper part of the trench; a gate electrode 19 which is arranged in the trench and is covered by the gate source isolation dielectric film 20, an oxidation film 181 formed by oxidizing the side wall of the trench and an insulation dielectric film 180, and the gate electrode 19 is flush with the P-type source region 16;
base regions 15 which are arranged on two sides of the boss of the P-type SiC epitaxial layer 13 and correspond to the corner of the boss;
a source electrode 21 covering the base region 15, the N-type well region 17, the P-type source region 16 and the gate-source isolation dielectric film 20;
further, the crystal form of the SiC epitaxial wafer is 4H-SiC or 6H-SiC or 3C-SiC, the thickness of the whole SiC epitaxial wafer is 1-800 μm, wherein the thickness of the SiC substrate 11 is 0.1-500um, the thickness of the SiC buffer layer 12 is 0.1-100um, and the thickness of the SiC epitaxial layer 13 is 0.1-500 um.
Further, the N-type doping impurity is nitrogen (N) or phosphorus (P); the P-type doping impurity is aluminum (Al) or boron (B) with a doping concentration of 1 × 10 14 -5×10 21 cm -3 。
Further, the thickness of the source region 16 and the well region 17 is 0.1um-100um.
Further, the widths of the P-type well region 17 and the N-type source region 16 are equal and smaller than the width of the boss of the N-type SiC epitaxial layer 13, and the width of the gate-source isolation dielectric film 20 is smaller than the width of the N-type source region 16.
Further, the gate-source isolation dielectric film 20 and the insulating dielectric film 180 are made of one or more of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.
The manufacturing method for realizing the novel groove silicon carbide transistor device structure comprises the following steps:
step S1: selecting a semiconductor epitaxial wafer consisting of a P-type SiC substrate 11, a P-type SiC buffer layer 12 and a P-type SiC epitaxial layer 13, wherein the semiconductor epitaxial wafer is specifically shown in FIG. 1;
step S2: forming a P-type source region 16 on the upper surface of the N-type well region 17 by secondary epitaxy or ion implantation, as shown in fig. 2;
and step S3: photoetching and etching both sides of the N-type well region 17 and the P-type source region 16, wherein the device is in a convex structure after the etching is finished, both sides of the P-type source region 16 are completely etched, and a part of the N-type well region 17, which is in contact with the P-type SiC epitaxial layer 13, is reserved on both sides of the bottom, as shown in FIG. 3 specifically;
and step S4: photoetching and etching the table tops on the two sides of the convex structure formed in the step S3 again, wherein the device is in a double-table top 14 after the etching is finished, one table top is an N-type well region 17 table top, and the other table top is an epitaxial layer 13 table top, as shown in fig. 4 specifically;
step S5: performing arc treatment on the corner of the table top of the epitaxial layer 13;
step S6: performing ion implantation mask deposition, photoetching, ion implantation mask etching and ion implantation on the mesa surface of the N-type well region 17, the mesa surface of the epitaxial layer 13 and the side wall between the mesa surface of the N-type well region 17 and the mesa surface of the epitaxial layer 13 to form a base region 15 corresponding to the corner of the mesa surface of the epitaxial layer 13, as shown in fig. 5 specifically;
step S7: photoetching and etching the middle part of the boss on the upper surface of the convex epitaxial layer 13 by adopting a photoetching technology to form a groove penetrating through the N-type well region 17 and the P-type source region 16, as shown in fig. 6 specifically;
step S8: growing an insulating dielectric film 180 on the bottom of the trench, as shown in fig. 7;
step S9: performing high-temperature oxidation on the side wall of the trench, so that the P-type SiC epitaxial layer 13, the N-type well region 17 and the P-type source region 16 on the side wall of the trench are all oxidized to form an oxide film 181, as shown in fig. 8 specifically;
step S10: filling the blank area in the groove with a gate electrode 19, wherein the upper surface of the gate electrode 19 is not lower than the upper surface of the P-type source region 16;
step S11: forming a gate source isolation dielectric film 20 which completely covers the upper surface of the gate electrode 19 and part of the P-type source region 16 above the gate electrode 19, wherein the width of the gate source isolation dielectric film 20 is smaller than that of the P-type source region 16;
step S12: a drain electrode 22 is formed on the lower surface of the SiC substrate 11 and a source electrode 21 is formed on the upper surface of the device to cover the base region 15, the N-type well region 17, the P-type source region 16 and the gate-source isolation dielectric film 20, as shown in fig. 9.
Furthermore, the ion implanted substance in the base region 15 is N, P,B or Al, the energy of ion implantation is 10Kev-15Mev, the temperature of the ion implantation is 22-1000 ℃, and the dose of the ion implantation is 1 x 10 10 -5×10 16 cm -2 。
Further, the thickness of the oxide film 181 formed on the sidewall of the trench is 0.01um to 1um, and the thickness of the oxide film 181 is less than half of the width of the trench.
Further, the thickness of the insulating dielectric film 180 formed at the bottom of the trench is 0.01um-200um, and the thickness of the insulating dielectric film 180 is smaller than the depth of the trench.
Further, the source electrode 21 and the drain electrode 22 are metal thin films of Ti, ni, al, cu, au, ag, mo, W, tiW, tiC, fe, cr, etc., metal silicides formed by reacting metal with silicon carbide through high temperature treatment, or other conductive materials, and the thickness of the thin films is 0.001um to 10um.
Furthermore, in the photoetching technology and the wet method or dry method etching technology, the pattern of the mask plate is an interdigital structure or a parallel long strip-shaped or polygonal table top or a combined pattern of the interdigital structure and the parallel long strip-shaped or polygonal table top, the width of a window area is 0.01-200 mu m, the etching depth is 0.01-200 mu m, and the width of the table top area is 0.01-200 mu m; wherein the length of the parallel long strip patterns and the interdigital patterns is 0.01 mu m-20cm.
Example 3
A novel groove silicon carbide transistor device comprises a P-type SiC epitaxial layer 13 with a convex-shaped structure on the cross section and arc-shaped corners of table tops on two sides;
a P-type SiC buffer layer 12, an N-type SiC substrate 11 and a drain electrode 22 which are sequentially arranged below the P-type SiC epitaxial layer 13 from top to bottom in the cross-sectional view of the trench silicon carbide transistor device;
the groove is arranged in the middle of the boss of the P-type SiC epitaxial layer 13;
the N-type well region 17 and the P-type source region 16 are arranged on the upper part of the boss of the P-type SiC epitaxial layer 13 from bottom to top and are positioned on two sides of the groove;
an insulating dielectric film 180 disposed at the bottom of the trench;
an oxide film 181 formed by oxidizing the sidewall of the trench;
a gate source isolation dielectric film 20 disposed on the upper portion of the trench; a gate electrode 19 which is arranged in the trench and is covered by the gate source isolation dielectric film 20, an oxidation film 181 formed by oxidizing the side wall of the trench and an insulation dielectric film 180, and the gate electrode 19 is flush with the P-type source region 16;
base regions 15 which are arranged on two sides of the boss of the P-type SiC epitaxial layer 13 and correspond to the corner of the boss;
further, the crystal form of the SiC epitaxial wafer is 4H-SiC or 6H-SiC or 3C-SiC, the thickness of the whole SiC epitaxial wafer is 1-800 μm, wherein the thickness of the SiC substrate 11 is 0.1-500um, the thickness of the SiC buffer layer 12 is 0.1-100um, and the thickness of the SiC epitaxial layer 13 is 0.1-500 um.
Further, the N-type doping impurity is nitrogen (N) or phosphorus (P); the P-type doping impurity is aluminum (Al) or boron (B), and the doping concentration is 1 × 10 14 -5×10 21 cm -3 。
Further, the thickness of the source region 16 and the well region 17 is 0.1um-100um.
Further, the widths of the P-type well region 17 and the N-type source region 16 are equal and smaller than the width of the boss of the N-type SiC epitaxial layer 13, and the width of the gate-source isolation medium film 20 is smaller than the width of the N-type source region 16.
Further, the gate-source isolation dielectric film 20 and the insulating dielectric film 180 are made of one or more of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.
The manufacturing method for realizing the novel groove silicon carbide transistor device structure comprises the following steps:
step S1: selecting a semiconductor epitaxial wafer consisting of an N-type SiC substrate 11, a P-type SiC buffer layer 12 and a P-type SiC epitaxial layer 13, and forming an N-type well region 17 on the upper surface of the P-type SiC epitaxial layer 13 through secondary epitaxy or ion implantation, as shown in FIG. 1 specifically;
step S2: forming a P-type source region 16 on the upper surface of the N-type well region 17 by secondary epitaxy or ion implantation, as shown in fig. 2;
and step S3: photoetching and etching both sides of the N-type well region 17 and the P-type source region 16, wherein the device is in a convex structure after the etching is finished, both sides of the P-type source region 16 are completely etched, and a part of the N-type well region 17, which is in contact with the P-type SiC epitaxial layer 13, is reserved on both sides of the bottom, as shown in FIG. 3 specifically;
and step S4: photoetching and etching the table tops on the two sides of the convex structure formed in the step S3 again, wherein the device is in a double-table top 14 after the etching is finished, one table top is an N-type well region 17 table top, and the other table top is an epitaxial layer 13 table top, as shown in fig. 4 specifically;
step S5: performing arc treatment on the corner of the table top of the epitaxial layer 13;
step S6: performing ion implantation mask deposition, photoetching, ion implantation mask etching and ion implantation on the mesa surface of the N-type well region 17, the mesa surface of the epitaxial layer 13 and the side wall between the mesa surface of the N-type well region 17 and the mesa surface of the epitaxial layer 13 to form a base region 15 corresponding to the corner of the mesa surface of the epitaxial layer 13, as shown in fig. 5 specifically;
step S7: photoetching and etching the middle part of the boss on the upper surface of the convex epitaxial layer 13 by adopting a photoetching technology to form a groove penetrating through the N-type well region 17 and the P-type source region 16, as shown in fig. 6 specifically;
step S8: growing an insulating dielectric film 180 on the bottom of the trench, as shown in fig. 7;
step S9: performing high-temperature oxidation on the side wall of the trench, so that the P-type SiC epitaxial layer 13, the N-type well region 17 and the P-type source region 16 on the side wall of the trench are all oxidized to form an oxide film 181, as shown in fig. 8 specifically;
step S10: filling the blank area in the groove with a gate electrode 19, wherein the upper surface of the gate electrode 19 is not lower than the upper surface of the P-type source region 16;
step S11: forming a gate-source isolation dielectric film 20 completely covering the upper surface of the gate electrode 19 and part of the P-type source region 16 above the gate electrode 19, wherein the width of the gate-source isolation dielectric film 20 is smaller than that of the P-type source region 16, as shown in fig. 1;
step S12: a drain electrode 22 is formed on the lower surface of the SiC substrate 11 and a source electrode 21 is formed on the upper surface of the device to cover the base region 15, the N-type well region 17, the P-type source region 16 and the gate-source isolation dielectric film 20, as shown in fig. 9.
Furthermore, the ion implantation material of the base region 15 is N, P, B or Al, and the energy of the ion implantation is 10Kev-15Mev, soThe temperature of the ion implantation is 22-1000 ℃, and the dose of the ion implantation is 1 x 10 10 -5×10 16 cm -2 。
Further, the thickness of the oxide film 181 formed on the sidewall of the trench is 0.01um to 1um, and the thickness of the oxide film 181 is less than half of the width of the trench.
Further, the thickness of the insulating dielectric film 180 formed at the bottom of the trench is 0.01um to 200um, and the thickness of the insulating dielectric film 180 is smaller than the depth of the trench.
Further, the source electrode 21 and the drain electrode 22 are metal thin films of Ti, ni, al, cu, au, ag, mo, W, tiW, tiC, fe, cr, etc., metal silicides formed by reacting metal with silicon carbide through high temperature treatment, or other conductive materials, and the thickness of the thin films is 0.001um to 10um.
Furthermore, in the photoetching technology and the wet method or dry method etching technology, the pattern of the mask plate is an interdigital structure or a parallel long strip-shaped or polygonal table top or a combined pattern of the interdigital structure and the parallel long strip-shaped or polygonal table top, the width of a window area is 0.01-200 mu m, the etching depth is 0.01-200 mu m, and the width of the table top area is 0.01-200 mu m; wherein the length of the parallel long strip patterns and the interdigital patterns is 0.01 mu m-20cm.
Example 4
A novel groove silicon carbide transistor device comprises an N-type SiC epitaxial layer 13, wherein the section of the N-type SiC epitaxial layer is of a convex structure, and corners of table tops on two sides are subjected to circular arc treatment;
an N-type SiC buffer layer 12, a P-type SiC substrate 11 and a drain electrode 22 which are sequentially arranged below the N-type SiC epitaxial layer 13 from top to bottom in a cross-sectional view of the trench silicon carbide transistor device;
the groove is formed in the middle of the boss of the N-type SiC epitaxial layer 13;
the P-type well region 17 and the N-type source region 16 are arranged on the upper part of the boss of the N-type SiC epitaxial layer 13 from bottom to top and are positioned on two sides of the groove;
an insulating dielectric film 180 disposed at the bottom of the trench;
an oxide film 181 formed by oxidizing the sidewall of the trench;
a gate source isolation dielectric film 20 disposed on the upper portion of the trench; a gate electrode 19 which is arranged in the trench and is covered by the gate source isolation dielectric film 20, an oxidation film 181 formed by oxidizing the side wall of the trench and an insulation dielectric film 180, and the gate electrode 19 is flush with the N-type source region 16;
base regions 15 which are arranged on two sides of the lug boss of the N-type SiC epitaxial layer 13 and correspond to the corner of the lug boss;
a source electrode 21 covering the base region 15, the P-type well region 17, the N-type source region 16 and the gate-source isolation dielectric film 20;
further, the crystal form of the SiC epitaxial wafer is 4H-SiC or 6H-SiC or 3C-SiC, the thickness of the whole SiC epitaxial wafer is 1-800 μm, wherein the thickness of the SiC substrate 11 is 0.1-500um, the thickness of the SiC buffer layer 12 is 0.1-100um, and the thickness of the SiC epitaxial layer 13 is 0.1-500 um.
Further, the N-type doping impurity is nitrogen (N) or phosphorus (P); the P-type doping impurity is aluminum (Al) or boron (B) with a doping concentration of 1 × 10 14 -5×10 21 cm -3 。
Further, the thickness of the source region 16 and the well region 17 is 0.1um-100um.
Further, the widths of the P-type well region 17 and the N-type source region 16 are equal and smaller than the width of the boss of the N-type SiC epitaxial layer 13, and the width of the gate-source isolation medium film 20 is smaller than the width of the N-type source region 16.
Further, the gate-source isolation dielectric film 20 and the insulating dielectric film 180 are made of one or more of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.
The manufacturing method for realizing the novel groove silicon carbide transistor device structure comprises the following steps:
step S1: selecting a semiconductor epitaxial wafer consisting of a P-type SiC substrate 11, an N-type SiC buffer layer 12 and an N-type SiC epitaxial layer 13, and forming a P-type well region 17 on the upper surface of the N-type SiC epitaxial layer 13 through secondary epitaxy or ion implantation, as shown in fig. 1 specifically;
step S2: forming an N-type source region 16 on the upper surface of the P-type well region 17 by secondary epitaxy or ion implantation, as shown in fig. 2;
and step S3: photoetching and etching two sides of the P-type well region 17 and the N-type source region 16, wherein the device is in a convex structure after the etching is finished, the two sides of the N-type source region 16 are completely etched, and the part of the P-type well region 17, which is in contact with the N-type SiC epitaxial layer 13, on the two sides of the bottom is reserved, as shown in fig. 3 specifically;
and step S4: photoetching and etching the table tops on the two sides of the convex structure formed in the step S3 again, wherein the device is in a double-table top 14 after the etching is finished, one table top is a P-type well region 17 table top, and the other table top is an epitaxial layer 13 table top, as shown in fig. 4 specifically;
step S5: performing arc treatment on the corner of the table top of the epitaxial layer 13;
step S6: performing ion implantation mask deposition, photoetching, ion implantation mask etching and ion implantation on the mesa of the P-type well region 17, the mesa of the epitaxial layer 13 and the side wall between the mesa of the P-type well region 17 and the mesa of the epitaxial layer 13 to form a base region 15 corresponding to the corner of the mesa of the epitaxial layer 13, as shown in fig. 5 specifically;
step S7: photoetching and etching the middle part of the boss on the upper surface of the convex epitaxial layer 13 by adopting a photoetching technology to form a groove penetrating through the P-type well region 17 and the N-type source region 16, as shown in fig. 6 specifically;
step S8: growing an insulating dielectric film 180 on the bottom of the trench, as shown in fig. 7;
step S9: performing high-temperature oxidation on the side wall of the trench, so that the N-type SiC epitaxial layer 13, the P-type well region 17 and the N-type source region 16 on the side wall of the trench are all oxidized to form an oxide film 181, as shown in fig. 8 specifically;
step S10: filling the blank area in the groove with a gate electrode 19, wherein the upper surface of the gate electrode 19 is not lower than the upper surface of the N-type source region 16;
step S11: forming a gate-source isolation dielectric film 20 which completely covers the upper surface of the gate electrode 19 and part of the N-type source region 16 above the gate electrode 19, wherein the width of the gate-source isolation dielectric film 20 is smaller than that of the N-type source region 16;
step S12: a drain electrode 22 is formed on the lower surface of the SiC substrate 11 and a source electrode 21 is formed on the upper surface of the device to cover the base region 15, the P-type well region 17, the N-type source region 16 and the gate-source isolation dielectric film 20, as shown in fig. 9.
Furthermore, the ion-implanted substance of the base region 15 is N,P, B or Al, the energy of ion implantation is 10Kev-15Mev, the temperature of the ion implantation is 22-1000 deg.C, and the dose of the ion implantation is 1 × 10 10 -5×10 16 cm -2 。
Further, the thickness of the oxide film 181 formed on the sidewall of the trench is 0.01um to 1um, and the thickness of the oxide film 181 is less than half of the width of the trench.
Further, the thickness of the insulating dielectric film 180 formed at the bottom of the trench is 0.01um to 200um, and the thickness of the insulating dielectric film 180 is smaller than the depth of the trench.
Further, the source electrode 21 and the drain electrode 22 are metal thin films of Ti, ni, al, cu, au, ag, mo, W, tiW, tiC, fe, cr, etc., metal silicides or other conductive materials formed by reacting metal with silicon carbide through high temperature treatment, and the thickness of the thin films is 0.001um to 10um.
Furthermore, in the photoetching technology and the wet method or dry method etching technology, the pattern of the mask plate is an interdigital structure or a parallel long strip-shaped or polygonal table top or a combined pattern of the interdigital structure and the parallel long strip-shaped or polygonal table top, the width of a window area is 0.01-200 mu m, the etching depth is 0.01-200 mu m, and the width of the table top area is 0.01-200 mu m; wherein the length of the parallel long strip patterns and the interdigital patterns is 0.01 mu m-20cm.
The doping types of the substrate, the buffer layer and the epitaxial layer are the same in the embodiment 1 and the embodiment 2 of the invention, and the device is an MOS device; the doping types of the substrate and the buffer layer and the epitaxial layer are opposite in the embodiment 3 and the embodiment 4, and the device is an IGBT device.
The experimental data in examples 1 to 4 of the present invention were compared with those of the ordinary MOSFET and ordinary IGBT devices, and the data were as follows:
Figure 737820DEST_PATH_IMAGE002
compared with the experimental data, the reverse breakdown voltage of the MOSFET device and the IGBT device is higher than that of the common device by adopting the method in the embodiment of the invention, and the preparation method changes the appearance of the junction edge in the device, thereby improving the electric field distribution of the surface near the junction, relieving the electric field concentration near the junction edge, improving the reverse breakdown voltage of the device, improving the voltage resistance and the reliability of the device and greatly prolonging the service life of the device.
The above-mentioned embodiments are further described in detail for the purpose of illustrating the invention, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the invention and are not intended to limit the invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit of the invention should be included in the scope of the invention.

Claims (9)

1. A novel groove silicon carbide transistor device is characterized by comprising a first conductive type SiC epitaxial layer (13) with a convex-shaped structure in cross section;
a first conductive type SiC buffer layer (12), a SiC semiconductor substrate (11) and a drain electrode (22) are sequentially arranged on the lower portion of the first conductive type SiC epitaxial layer (13);
the groove is arranged in the middle of the boss of the first conductive type SiC epitaxial layer (13);
the second conductive type well region (17) and the first conductive type source region (16) are arranged on the upper part of the lug boss of the first conductive type SiC epitaxial layer (13) from bottom to top and are positioned on two sides of the groove;
an insulating dielectric film (180) arranged at the bottom of the trench;
an oxide film (181) formed by oxidation of the trench sidewall;
a gate source isolation dielectric film (20) arranged on the upper part of the trench;
a gate electrode (19) which is arranged in the groove and is coated by the gate source isolation medium film (20), an oxidation film (181) formed by oxidizing the side wall of the groove and an insulation medium film (180), and the gate electrode (19) is flush with the first conduction type source region (16);
base regions (15) which are arranged on two sides of a boss of the first conductive type SiC epitaxial layer (13) and correspond to the corner of the boss;
a source electrode (21) covering the base region (15), the second conductive type well region (17), the first conductive type source region (16) and the grid source isolation medium film (20);
the conductive types are divided into an N type and a P type, and the first conductive type is opposite to the doping type of the second conductive type.
2. The novel trench silicon carbide transistor device of claim 1 wherein: if the silicon carbide transistor is a silicon carbide MOSFET device, the doping type of the SiC semiconductor substrate (11) is a first conduction type; if the silicon carbide transistor is a silicon carbide IGBT device, the doping type of the SiC semiconductor substrate (11) is a second conduction type.
3. The novel trench silicon carbide transistor device of claim 1 or 2, wherein: the widths of the second conduction type well region (17) and the first conduction type source region (16) are equal and smaller than the width of the boss of the first conduction type SiC epitaxial layer (13); the width of the gate-source isolation medium film (20) is smaller than that of the first conduction type source region (16).
4. The novel trench silicon carbide transistor device of claim 1 wherein: the gate source isolation medium film (20) and the insulating medium film (180) are made of one or more of silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.
5. A novel trench silicon carbide transistor device according to any of claims 1 to 4, wherein the method of fabrication comprises the steps of:
step S1: selecting a semiconductor epitaxial wafer consisting of a SiC semiconductor substrate (11), a first conductive type SiC buffer layer (12) and a first conductive type SiC epitaxial layer (13), and forming a second conductive type well region (17) on the upper surface of the first conductive type SiC epitaxial layer (13) through secondary epitaxy or ion implantation;
step S2: forming a first conductive type source region (16) on the upper surface of the second conductive type well region (17) through secondary epitaxy or ion implantation;
and step S3: photoetching and etching the two sides of the second conductive type well region (17) and the first conductive type source region (16), wherein the device is in a convex structure after the etching is finished, the two sides of the first conductive type source region (16) are completely etched, and a part of the second conductive type well region (17) of which the two sides of the bottom are in contact with the first conductive type SiC epitaxial layer (13) is reserved;
and step S4: photoetching and etching the table tops on the two sides of the convex structure formed in the step S3 again, wherein the device is in a double-table top (14) shape after the etching is finished, one table top is a second conductive type well region (17) table top, and the other table top is an epitaxial layer (13) table top;
step S5: performing arc treatment on the corner of the table top of the epitaxial layer (13);
step S6: carrying out ion implantation mask deposition, photoetching, ion implantation mask etching and ion implantation on the table top of the second conductive type well region (17), the table top of the epitaxial layer (13) and the side wall between the table top of the second conductive type well region (17) and the table top of the epitaxial layer (13) to form a base region (15) corresponding to the corner of the table top of the epitaxial layer (13);
step S7: photoetching and etching the middle part of a lug boss on the upper surface of the convex epitaxial layer (13) by adopting a photoetching and etching technology to form a groove penetrating through the second conductive type well region (17) and the first conductive type source region (16);
step S8: growing an insulating medium film (180) at the bottom of the trench;
step S9: performing high-temperature oxidation on the side wall of the groove to oxidize the first conduction type SiC epitaxial layer (13), the second conduction type well region (17) and the first conduction type source region (16) on the side wall of the groove to form an oxidation film (181);
step S10: filling the blank area in the groove with a gate electrode (19), wherein the upper surface of the gate electrode (19) is not lower than that of the first conductive type source area (16);
step S11: forming a gate-source isolation dielectric film (20) which completely covers the upper surface of the gate electrode (19) and part of the first conduction type source region (16) above the gate electrode (19), wherein the width of the gate-source isolation dielectric film (20) is smaller than that of the first conduction type source region (16);
step S12: and forming a drain electrode (22) on the lower surface of the SiC substrate (11) and forming a source electrode (21) covering the base region (15), the second conductive type well region (17), the first conductive type source region (16) and the gate source isolation medium film (20) on the upper surface of the device.
6. The method of claim 5 wherein said silicon carbide transistor device is formed by: the material of ion implantation of the base region (15) is N, P, B or Al, the energy of the ion implantation is 10Kev-15Mev, the temperature of the ion implantation is 22-1000 ℃, and the dose of the ion implantation is 1 x 10 10 -5×10 16 cm -2 。
7. The method of claim 5 wherein said silicon carbide transistor device is formed by: the thickness of the oxide film (181) formed on the side wall of the trench is 0.01um-1um, and the thickness of the oxide film (181) is less than half of the width of the trench.
8. The method of claim 5 wherein said silicon carbide transistor comprises: the thickness of the insulating dielectric film (180) formed at the bottom of the groove is 0.01um-200um, and the thickness of the insulating dielectric film (180) is smaller than the depth of the groove.
9. The method of claim 5 wherein said silicon carbide transistor device is formed by: the source electrode (21) and the drain electrode (22) are metal or metal silicide, and the thickness of the film is 0.001um-10um.
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CN113299748A (en) * 2021-05-25 2021-08-24 重庆伟特森电子科技有限公司 T-gate groove silicon carbide transistor with accumulation type channel structure and manufacturing method thereof
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Family Cites Families (12)

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JP5498431B2 (en) * 2011-02-02 2014-05-21 ローム株式会社 Semiconductor device and manufacturing method thereof
JP5817204B2 (en) * 2011-04-28 2015-11-18 トヨタ自動車株式会社 Silicon carbide semiconductor device
JP2013243179A (en) * 2012-05-18 2013-12-05 Sumitomo Electric Ind Ltd Silicon carbide semiconductor device
JP6354525B2 (en) * 2014-11-06 2018-07-11 株式会社デンソー Method for manufacturing silicon carbide semiconductor device
JP6871562B2 (en) * 2016-11-16 2021-05-12 富士電機株式会社 Silicon carbide semiconductor device and its manufacturing method
JP6928336B2 (en) * 2016-12-28 2021-09-01 富士電機株式会社 Silicon Carbide Semiconductor Device and Method for Manufacturing Silicon Carbide Semiconductor Device
CN106684132B (en) * 2016-12-29 2019-10-01 西安电子科技大学 Silicon carbide bipolar transistor npn npn and preparation method thereof based on active area groove structure
CN106847879B (en) * 2017-01-19 2021-12-03 北京世纪金光半导体有限公司 SiC MOSFET device with inclined channel and preparation method
CN107591455B (en) * 2017-09-05 2020-02-18 西安理工大学 SiC trench type step-like junction barrier Schottky diode
CN109148566B (en) * 2018-08-28 2020-11-13 电子科技大学 Silicon carbide MOSFET device and method of manufacturing the same
CN108807504B (en) * 2018-08-28 2022-01-25 电子科技大学 Silicon carbide MOSFET device and method of manufacturing the same
CN109509706B (en) * 2018-12-29 2023-05-02 重庆伟特森电子科技有限公司 Preparation method of silicon carbide diode and silicon carbide diode

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
段宝兴 ; 杨银堂 ; .阶梯AlGaN外延新型Al_(0.25)Ga_(0.75)N/GaNHEMTs击穿特性分析.2014,(第05期),全文. *
罗小梦 ; 王立新 ; 杨尊松 ; 王路璐 ; .一种电荷平衡结构的沟槽MOSFET的优化设计.2017,(第04期),全文. *

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