CN113506826B - Groove type silicon carbide transistor and preparation method thereof - Google Patents

Groove type silicon carbide transistor and preparation method thereof Download PDF

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CN113506826B
CN113506826B CN202110672504.8A CN202110672504A CN113506826B CN 113506826 B CN113506826 B CN 113506826B CN 202110672504 A CN202110672504 A CN 202110672504A CN 113506826 B CN113506826 B CN 113506826B
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film
doping
region
trench
gate
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CN113506826A (en
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郑柳
何志
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Chongqing Weitesen Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention belongs to the technical field of semiconductors, and discloses a trench type silicon carbide transistor which comprises a silicon carbide semiconductor film, a base region doping region, a source region doping region, a gate trench, an insulating medium film I, an insulating medium film II, a gate electrode, a base region conducting film, an isolating medium film, a source electrode and a drain electrode. According to the invention, the edge of the main junction is etched into a mesa shape, so that the shape of the edge of the junction in the device is changed, the electric field concentration near the edge of the junction is relieved, and the reverse breakdown voltage, the voltage resistance and the reliability of the device are improved. The invention also discloses a preparation method of the trench type silicon carbide transistor, when preparing the gate oxide layer, firstly, polysilicon or amorphous silicon is deposited in the gate trench, and then etching and oxidizing are carried out on the polysilicon or amorphous silicon, so that the thickness of the gate oxide layer at the bottom of the trench is reinforced, the gate oxide layer is prevented from being broken down, and the reliability of the transistor is further improved.

Description

Groove type silicon carbide transistor and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a trench type silicon carbide transistor and a manufacturing method thereof.
Background
With the rapid development of modern electronic technology and application thereof, power devices have been greatly developed in terms of structure and performance, and particularly, power devices represented by silicon (Si) have been promoting rapid development of optoelectronic and microelectronic technologies. However, with the advent and popularization of technologies such as superjunction, trench and insulated gate bipolar transistor, the performance of the silicon-based power device has approached the limit of materials, and in many cases, the silicon-based power device can only work in an environment below 250 ℃, especially when high temperature, high power, high frequency or extremely strong radiation is encountered and the environment exists at the same time, the conventional silicon-based power device cannot meet the working requirements, and each tiny improvement of the performance of the silicon-based power device needs to pay a huge cost, which has led people to search for a novel semiconductor material with more excellent performance, namely silicon carbide (SiC).
Silicon carbide is used as a third-generation semiconductor material, has the outstanding advantages of large forbidden bandwidth, high breakdown field strength, high thermal conductivity, high carrier saturation mobility, strong irradiation resistance and the like, and is particularly suitable for severe application environments such as high temperature, high voltage, high current, high frequency, high irradiation and the like related to a modern power electronic system. In the aspects of design, development and application technology of the silicon carbide power device, compared with the silicon-based power device with the same power voltage class, the on-resistance and the switching loss of the silicon carbide power device are greatly reduced, so that the silicon carbide power device is more suitable for the working scene under the conditions of high working frequency and high temperature. Although silicon carbide power device samples of various voltage classes are continuously emerging, the limitations of epitaxial material quality and surface treatment processes remain. Along with the continuous maturation of key technologies such as epitaxial technology, surface treatment, ion implantation and the like, bulk defects of the silicon carbide epitaxial material are improved to a great extent, and the surface mobility is gradually improved. The patent with publication number CN111276545A discloses a novel trench silicon carbide transistor and a manufacturing method thereof, and the novel trench silicon carbide transistor is characterized in that on the basis of MOSFET or IGBT, main junction edges are etched into double mesa shapes by means of etching and the like to form a second conductive type well region mesa and an epitaxial layer mesa respectively, so that the purpose of changing the morphology of the junction edges in a device is achieved, the electric field distribution of the surface near the junction is improved, the electric field concentration near the junction edges is relieved, the reverse breakdown voltage of the device is improved, and the voltage resistance and the reliability of the device are improved. However, the trench on the substrate of the patent with publication number CN111276545a is a vertical trench, and the vertical trench type silicon carbide transistor is beneficial to high-current and high-integration components, but the conventional vertical trench type silicon carbide transistor still has the following defects:
(1) Because the forbidden bandwidth of the silicon carbide material is large, compared with the traditional semiconductor devices such as silicon materials, larger gate voltage is needed to form the inversion layer, the carrier concentration in the inversion layer of the silicon carbide device under the same gate voltage is generally smaller than that of the traditional semiconductor device, and the overlarge gate voltage can exceed the bearing range of the gate oxide layer to cause early breakdown.
(2) The low channel mobility in the vertical channel results in a large channel resistance, reducing the effect of emitter injection to affect the effect of conductivity modulation in the drift region.
(3) The double-mesa structure has high requirements on processing, complex processing technology and low reliability.
Based on the analysis, the conventional vertical trench type silicon carbide transistor generally has the problems that a device channel inversion layer is difficult to form, channel resistance is overlarge, a gate oxide layer is easy to break down, a processing process is complex, process reliability is poor and the like. Accordingly, there is a need in the art to provide a novel trench silicon carbide transistor and a method of fabricating the same that eliminates the drawbacks of the prior art.
Disclosure of Invention
The invention aims to provide a trench silicon carbide transistor, which adopts the following technical scheme:
the trench type silicon carbide transistor comprises a silicon carbide film, wherein the silicon carbide film sequentially comprises a substrate, a buffer layer and an epitaxial film from bottom to top, and the epitaxial film is in a convex shape;
the upper surface of a boss in the middle of the base region doping region is provided with an active region doping region;
the gate groove penetrates through the base region doping region and the source region doping region, extends into the epitaxial film, and is arranged at the bottom of the gate groove above the bottoms of the platforms at two sides of the boss of the epitaxial film in the vertical direction;
the bottom of the gate groove is provided with a concave-shaped insulating medium film I, the side wall of the gate groove is provided with an insulating medium film II, and the gate groove is also filled with a T-shaped gate electrode matched with the concave-shaped bottom insulating medium film;
base region conductive films are further arranged on the platforms at two sides of the boss of the base region doping region;
the top of the gate electrode, the source region doped region and the base region conductive film is also provided with an isolation medium thin and a source electrode from bottom to top;
the lower surface of the substrate is also provided with a drain electrode.
The silicon carbide film in the invention is a film in the prior art, and mainly comprises a substrate, a buffer layer and an epitaxial film. Wherein the epitaxial film is a multilayer epitaxial film or a single-layer epitaxial film. The silicon carbide film is 4H-SiC or 6H-SiC or 3C-SiC, and the invention preferably selects 4H-SiC because the mobility of the crystal face of the 4H-SiC material is higher than that of the 3C-SiC material and the 6H-SiC material, thereby further improving the surface mobility and reducing the bulk defect of the transistor. The overall thickness of the silicon carbide film is 50 μm to 800. Mu.m, preferably 500. Mu.m. Wherein the thickness of the substrate is 10 mu m-300 mu m, the thickness of the buffer layer is 20 mu m-100 mu m, the number of layers of the epitaxial thin film is 2-100, and the thickness of each epitaxial thin film is 20 mu m-200 mu m. The thickness of the base region doped region and the source region doped region is 20 μm-100 μm.
The invention further provides a manufacturing method of the trench silicon carbide transistor, which adopts the following technical scheme:
the manufacturing method of the trench type silicon carbide transistor specifically comprises the following steps:
step S1, sequentially forming a first base region doping region and a source region doping region on the upper surface of an epitaxial film of a silicon carbide film through secondary epitaxy or ion implantation;
s2, forming a patterned mask layer I on the upper surface of the doped region of the source region through dielectric film deposition, photoetching and etching, and forming base region channels on two sides of the upper end of the sample through etching, so that the whole sample is in a convex shape;
s3, forming a second base region doped region along the outlines of two sides of the epitaxial film through an ion implantation process;
s4, removing the patterned mask layer I, performing high-temperature annealing on the sample, and activating the injected impurities;
s5, forming a patterned mask layer II on the upper surface of the sample again through dielectric film deposition, photoetching and etching, forming a gate groove in the middle of the upper end of the sample through etching, wherein the bottom of the gate groove is above the bottoms of the platforms on two sides of the boss of the epitaxial film in the vertical direction;
s6, depositing a layer of semiconductor film on the bottom, the side wall and the surface of the mask layer II of the gate trench;
step S7, oxidizing the semiconductor film deposited in the step S6 to form an oxidized film;
step S8, coating photoresist on the outer surface of the oxidized film, and filling the gate groove with the photoresist;
step S9, etching the photoresist in the step S8, and only keeping all the photoresist in the gate trench;
step S10, removing all mask layers II on two sides of the gate trench, an oxide film on the upper surface of the mask layer II and an oxide film on the upper part of the side wall of the gate trench by adopting an etching or corrosion process, only retaining the lower part of the side wall of the gate trench and the oxide film on the bottom of the gate trench to obtain an insulating medium film I, and removing residual photoresist;
step S11, oxidizing the side wall of the groove to obtain an insulating medium film II, and then depositing a gate film in the gate groove to form a gate electrode; depositing a base region conductive film on the upper surface of a base region channel; then depositing an isolating dielectric thin on top of the gate electrode, the source region doped region and the conductive film;
and S12, photoetching and etching the sample to form ohmic contact openings of a source electrode and a base electrode, forming ohmic contact and a pressure welding source electrode on the upper surfaces of the doping region of the base region and the doping region of the source region, and forming ohmic contact and a pressure welding drain electrode on the back surface of the lower surface of the substrate.
The invention has the beneficial effects that:
(1) When the gate oxide layer is prepared, firstly, polysilicon or amorphous silicon is deposited in the gate groove, and then etching and oxidizing are carried out on the polysilicon or amorphous silicon, so that the thickness of the gate oxide layer at the bottom of the groove is reinforced, the gate oxide layer is prevented from being broken down, and the reliability of the transistor is further improved. The critical breakdown field strength of silicon carbide is high, the field strength born by the gate oxide layer of the trench type silicon carbide transistor at the trench corner is often high, and when the field strength exceeds the range born by the oxide layer, the field strength is easy to cause destructive failure of the device.
(2) The method can also avoid the ion implantation of the gate channel region, reduce the damage of ions to the gate oxide layer and ensure the reliability of the device.
(3) The invention etches the edge of the main junction into a mesa shape by means of etching and the like, and changes the shape of the edge of the junction in the device, thereby improving the electric field distribution of the surface near the junction, relieving the electric field concentration near the edge of the junction, and improving the reverse breakdown voltage, the voltage-resistant performance and the reliability of the device.
(4) The processing technology of the invention is simple, easy to realize and convenient for mass production.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a structure during the processing of step S1 of the present invention.
Fig. 2 is a schematic structural diagram of the present invention after the completion of step S1.
Fig. 3 is a schematic structural diagram of the present invention after the completion of step S3.
Fig. 4 is a schematic structural diagram of the present invention after the completion of step S5.
Fig. 5 is a schematic structural diagram of the present invention after the completion of step S6.
Fig. 6 is a schematic structural diagram of the present invention after step S7 is completed.
Fig. 7 is a schematic structural diagram of the present invention after the completion of step S8.
Fig. 8 is a schematic structural diagram of the present invention after step S9 is completed.
Fig. 9 is a schematic structural diagram of the processing in step S10 of the present invention.
Fig. 10 is a schematic structural diagram of the process of step S11 of the present invention.
Fig. 11 is a schematic structural diagram of the present invention after the completion of step S11.
Fig. 12 is a schematic structural diagram of the present invention after the completion of step S12.
In the figure: 1. a silicon carbide film; 101. a substrate; 102. a buffer layer; 103. an epitaxial thin film; 2. a base region doping region; 201. the first base region doping region; 202. the second base region doping region; 3. a source region doped region; 4. a gate trench; 5. an insulating medium film I; 6. an insulating medium film II; 7. a gate electrode; 8. a base region conductive film; 9. a dielectric film; 10. a source electrode; 11. a drain electrode; 12. a mask layer I; 13. a base region channel; 14. a mask layer II; 15. a semiconductor thin film; 16. oxidizing the film; 17. and (3) photoresist.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiments and the drawings are only to be regarded as reference embodiments for describing the invention, which is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. For the purpose of further explanation of the invention, the dimensions of some of the elements in the figures may be exaggerated and not drawn on scale. The dimensions and relative dimensions do not correspond to the actual reduction in practicing the present invention. Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
Furthermore, the terms top, bottom, over, under and the like in the description and in the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein. It is to be noticed that the term 'comprising', used in the claims, should not be interpreted as being restricted to the means listed thereafter, but not excluding other elements or steps. Thus, it should be interpreted as specifying the presence of the stated features, parameters, steps or components, but not excluding the presence or addition of one or more other features, parameters, steps or components, or groups thereof.
Example 1
In this embodiment, the trench silicon carbide transistor is a MOSFET device. The doping types of the substrate 101, the buffer layer 102, the epitaxial film 103 and the source region doping region 3 are all of a first conductivity type, and the doping type of the base region doping region 2 is of a second conductivity type, wherein the first conductivity type is of an N type, and the second conductivity type is of a P type. The doping concentration is 1 multiplied by 10 14 ～5×10 21 cm -3 。
The trench type silicon carbide transistor comprises a silicon carbide film 1, wherein the silicon carbide film 1 sequentially comprises a substrate 101, a buffer layer 102 and an epitaxial film 103 from bottom to top, and the epitaxial film 103 is in a shape of a Chinese character 'tu'; the top outline of the epitaxial film 103 is provided with a base region doping region 2 in a shape like a Chinese character 'ji', and the upper surface of a boss in the middle of the base region doping region 2 is provided with an active region doping region 3; the epitaxial thin film comprises a base region doping region 2, a source region doping region 3 and a gate groove 4, wherein the base region doping region 2 and the source region doping region 3 are arranged in the epitaxial thin film 103 in a penetrating manner, and the bottom of the gate groove 4 is arranged above the bottoms of the platforms on two sides of the boss of the epitaxial thin film 103 in the vertical direction; the bottom of the gate groove 4 is provided with a concave-shaped insulating medium film I5, the side wall of the gate groove 4 is provided with an insulating medium film II 6, and the gate groove 4 is also filled with a T-shaped gate electrode 7 matched with the concave-shaped bottom insulating medium film; base region conductive films 8 are further arranged on the platforms on two sides of the boss of the base region doping region 2; the top of the gate electrode 7, the source region doped region 3 and the base region conductive film 8 is also provided with an isolating dielectric film and a source electrode 10 from bottom to top; the lower surface of the substrate 101 is also provided with a drain electrode 11.
The manufacturing method of the groove type silicon carbide transistor comprises the following steps:
step S1, sequentially forming a first base region doping region 201 and a source region doping region 3 on the upper surface of an epitaxial film 103 of a silicon carbide film 1 through secondary epitaxy or ion implantation, as shown in FIGS. 1 and 2;
s2, forming a patterned mask layer I12 on the upper surface of the source region doped region 3 through dielectric film deposition, photoetching and etching, and forming base region channels 13 on two sides of the upper end of the sample through etching, so that the whole sample is in a convex shape;
the dielectric film is a single-layer film or a composite layer film formed by silicon dioxide, silicon nitride, polysilicon, amorphous silicon and common metal (Ni, al, W, ti or any alloy compound thereof), and the thickness of the film is 10um-100um.
In the photoetching technology and the wet or dry etching technology, the mask plate pattern is an interdigital structure or a parallel strip or polygonal table board or a combination pattern thereof, the width of a window area is 1-200 mu m, the etching depth is 1-200 mu m, and the width of a table board area is 1-200 mu m; wherein the length of the patterns in the parallel strip patterns and the interdigital patterns is 1 mu m-20 cm.
Step S3, forming a second base region doped region 202 along the profile of the two sides of the epitaxial thin film 103 by an ion implantation process, as shown in fig. 3;
by adopting an ion mode, the implantation dosage, implantation angle, implantation depth, lateral diffusion and other aspects can be accurately controlled, the limit of the conventional process is overcome, the integration level, the opening speed, the yield and the service life of the circuit are improved, and the cost and the power consumption are reduced. The ion implantation material is aluminum or boron, and the ion implantation energy is 10 Kev-15 Mev. Preferably, the ion implantation energy is 50Kev to 1Mev; more preferably, the ion implantation energy is preferably 200Kev. The temperature of the ion implantation is 22-1000 ℃. Preferably, the ion implantation temperature is 150-800 ℃; more preferably, the ion implantation temperature is 450 ℃. The ion implantation dose is 1×10 10 ～5×10 16 cm -2 . Preferably, the ion implantation dose is; 2X 10 11 ～5×10 15 cm -2 。
S4, removing the patterned mask layer I12, performing high-temperature annealing on the sample, and activating the injected impurities;
the high-temperature annealing can activate interstitial atoms to move to lattice positions, repair lattice damage and defects and eliminate residual stress generated in the ion implantation process. The annealing mode adopts high temperature furnace annealing, rapid annealing or rapid thermal annealing (RTP) because of higher speed. The rapid annealing is preferred, so that the advantages of better inter-sheet uniformity, minimized impurity diffusion and the like can be realized. The annealing atmosphere is vacuum, nitrogen or argon atmosphere, the annealing temperature is 300-3000 ℃, and the annealing time is 0.1 min-2 h. Preferably, the annealing temperature is 600-1000 ℃; more preferably, the annealing temperature is 800 ℃.
Step S5, forming a patterned mask layer II 14 on the upper surface of the sample again through dielectric film deposition, photoetching and etching, forming a gate groove 4 in the middle of the upper end of the sample through etching, wherein the bottom of the gate groove 4 is above the bottoms of the platforms on two sides of the boss of the epitaxial film 103 in the vertical direction, as shown in FIG. 4;
the dielectric film is a single-layer film or a composite layer film formed by silicon dioxide, silicon nitride, polysilicon, amorphous silicon, common metal (Ni, al, W, ti or any alloy compound thereof) or any combination. The thickness of the film is 10um-100um.
The etching is a reactive ion etching technology or an inductively coupled plasma etching technology or a combination thereof; etching gases include, but are not limited to SF 6 、CF 4 、O 2 Any combination of atmospheres such as HBr. The mesa patterns are of interdigital structures or parallel strip-shaped or polygonal mesas or combination patterns thereof, the width of the window area is 1-200 mu m, the etching depth is 1-200 mu m, and the width of the mesa area is 1-200 mu m; wherein the length of the patterns in the parallel strip patterns and the interdigital patterns is 1 mu m-20 cm.
Step S6, depositing a layer of semiconductor film 15 on the bottom, the side wall and the surface of the mask layer II 14 of the gate trench 4, as shown in FIG. 5;
the semiconductor film is a polycrystalline silicon or amorphous silicon or monocrystalline silicon monolayer or composite film, and the thickness of the film is 10-200 mu m.
Step S7 of oxidizing the semiconductor thin film 15 deposited in step S6 to form an oxidized thin film 16, as shown in fig. 6;
step S8, coating photoresist 17 on the outer surface of the oxidation film 16, and filling the gate trench 4 with the photoresist 17, as shown in FIG. 7;
the photoresist is a common photoresist and can be positive photoresist or negative photoresist.
Step S9, etching the photoresist 17 in step S8, and only keeping all the photoresist 17 in the gate trench 4, as shown in FIG. 8;
step S10, removing all mask layers II 14 on two sides of the gate trench 4, an oxide film 16 on the upper surface of the mask layer II 14 and an oxide film 16 on the upper part of the side wall of the gate trench 4 by adopting an etching or corrosion process, and only reserving the lower part of the side wall of the gate trench 4 and the oxide film 16 on the bottom of the gate trench 4 to obtain an insulating medium film I5, as shown in FIG. 9; removing the residual photoresist 17;
the etching is a reactive ion etching technology or an inductively coupled plasma etching technology or a combination thereof; etching gases include, but are not limited to SF 6 、CF 4 、O 2 Any combination of atmospheres such as HBr; the corrosion is hydrofluoric acid or mixed solution of hydrofluoric acid, hydrogen peroxide and deionized water in any proportion.
Step S11, oxidizing the side wall of the groove to obtain an insulating medium film II 6, as shown in FIG. 10; subsequently depositing a gate thin film in the gate trench 4 to form a gate electrode 7; depositing a base region conductive film 8 on the upper surface of a base region channel 13; then depositing a thin isolating medium on top of the gate electrode 7, the source region doped region 3 and the conductive film, as shown in fig. 11;
the grid film is a single-layer film of highly doped polysilicon or common metal (Al, ni, ti, W, ag, au) or a composite film of any combination thereof, and the thickness of the film is 10-200 mu m.
The isolating dielectric film 9 is a single-layer or multi-layer composite film of insulating silicon dioxide, silicon nitride, polysilicon, amorphous silicon, phosphosilicate glass, borosilicate glass, TEOS and the like.
In step S12, ohmic contact openings of the source electrode and the base electrode are formed by photoetching and etching the sample, ohmic contact and bonding source electrode 10 are formed on the upper surfaces of the base region doping region 2 and the source region doping region 3, and ohmic contact and bonding drain electrode 11 is formed on the back surface of the lower surface of the substrate 101, as shown in fig. 12.
The ohmic contact, the source electrode and the drain electrode are all made of metal or conductive materials, and the thickness of the film is 0.001-100 um. Wherein, the metal can be a single-layer film such as Ti, ni, al, cu, au, ag, mo, W, tiW, tiC, fe, cr or a plurality of composite films.
The ohmic contact may be realized by a high-temperature treatment process, wherein the treatment mode comprises Rapid Thermal Annealing (RTA) or Laser Annealing (LA) or other high-temperature furnaces, and the gas atmosphere in the treatment process is a vacuum environment or an inert gas atmosphere such as nitrogen, argon and the like.
Example 2
In this embodiment, the trench silicon carbide transistor of the present invention is a MOSFET device. The doping types of the substrate 101, the buffer layer 102, the epitaxial film 103 and the source region doping region 3 are all of a first conductivity type, and the doping type of the base region doping region 2 is of a second conductivity type, wherein the first conductivity type is of a P type, and the second conductivity type is of an N type. The doping concentration is 1 multiplied by 10 14 ～5×10 21 cm -3 . In this embodiment, the trench silicon carbide transistor is identical to that of embodiment 1 in both structure and processing steps, except that the doping types of the respective portions are different.
Example 3
In this embodiment, the trench silicon carbide transistor of the present invention is an IGBT device. The doping types of the buffer layer 102, the epitaxial film 103 and the source region doping region 3 are all of the first conductivity type; the doping type of the substrate 101 and the doping type of the base region doping region 2 are both the second conductivity type, wherein the first conductivity type is N-type and the second conductivity type is P-type. The doping concentration is 1 multiplied by 10 14 ～5×10 21 cm -3 . In this embodiment, the trench silicon carbide transistor is identical to that of embodiment 1 in both structure and processing steps, except that the doping types of the respective portions are different.
Example 4
In the present practiceIn an embodiment, the trench silicon carbide transistor of the present invention is an IGBT device. The doping types of the buffer layer 102, the epitaxial film 103 and the source region doping region 3 are all of the first conductivity type; the doping type of the substrate 101 and the doping type of the base region doping region 2 are both the second conductivity type, wherein the first conductivity type is P-type and the second conductivity type is N-type. The doping concentration is 1 multiplied by 10 14 ～5×10 21 cm -3 . In this embodiment, the trench silicon carbide transistor is identical to that of embodiment 1 in both structure and processing steps, except that the doping types of the respective portions are different.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (8)

1. The utility model provides a trench type carborundum transistor, includes carborundum film (1), carborundum film (1) are from bottom to top including substrate (101), buffer layer (102) and epitaxial film (103) in proper order, its characterized in that:
the epitaxial film (103) is in a shape of a Chinese character 'tu';
a base region doping region (2) in a shape like a Chinese character 'ji' is arranged along the top outline of the epitaxial film (103), and an active region doping region (3) is arranged on the upper surface of a middle boss of the base region doping region (2);
the epitaxial thin film structure further comprises a gate groove (4) penetrating through the base region doping region (2) and the source region doping region (3), and the gate groove (4) extends into the epitaxial thin film (103);
the bottom of the gate groove (4) is provided with a concave-shaped insulating medium film I (5), the side wall of the gate groove (4) is provided with an insulating medium film II (6), and the gate groove (4) is also filled with a T-shaped gate electrode (7) matched with the concave-shaped bottom insulating medium film;
base region conductive films (8) are further arranged on the platforms at two sides of the boss of the base region doping region (2);
the top parts of the gate electrode (7), the source region doping region (3) and the base region conductive film (8) are also provided with an isolation medium film (9) and a source electrode (10) from bottom to top;
the lower surface of the substrate (101) is also provided with a drain electrode (11);
the preparation method of the trench silicon carbide transistor comprises the following steps:
step S1, sequentially forming a first base region doping region (201) and a source region doping region (3) on the upper surface of an epitaxial film (103) of a silicon carbide film (1) through secondary epitaxy or ion implantation;
s2, forming a patterned mask layer I (12) on the upper surface of the source region doped region (3) through dielectric film deposition, photoetching and etching, and forming base region channels (13) on two sides of the upper end of the sample through etching, so that the whole sample is in a convex shape;
s3, forming a second base region doped region (202) along the outlines of two sides of the epitaxial film (103) through an ion implantation process;
s4, removing the patterned mask layer I (12), performing high-temperature annealing on the sample, and activating the injected impurities;
s5, forming a patterned mask layer II (14) on the upper surface of the sample again through dielectric film deposition, photoetching and etching, and forming a gate groove (4) in the middle of the upper end of the sample through etching;
s6, depositing a layer of semiconductor film (15) on the bottom, the side wall and the surface of the mask layer II (14) of the gate trench (4);
step S7, oxidizing the semiconductor film (15) deposited in the step S6 to form an oxidized film (16);
step S8, coating photoresist (17) on the outer surface of the oxidation film (16), and filling the gate trench (4) with the photoresist (17);
step S9, etching the photoresist (17) in the step S8, and only keeping all the photoresist (17) in the gate trench (4);
step S10, removing all mask layers II (14) on two sides of the gate trench (4), an oxide film (16) on the upper surface of the mask layers II (14) and an oxide film (16) on the upper part of the side wall of the gate trench (4) by adopting an etching or corrosion process, only reserving the lower part of the side wall of the gate trench (4) and the oxide film (16) on the bottom of the gate trench (4) to obtain an insulating medium film I (5), and removing residual photoresist (17);
step S11, oxidizing the side wall of the groove to obtain an insulating medium film II (6), and then depositing a gate film in the gate groove (4) to form a gate electrode (7); depositing a base region conductive film (8) on the upper surface of a base region channel (13); then depositing an isolating medium thin on the tops of the gate electrode (7), the source region doped region (3) and the conductive film;
step S12, photoetching and etching a sample to form ohmic contact openings of a source electrode and a base electrode, forming ohmic contact and a pressure welding source electrode (10) on the upper surfaces of a base region doping region (2) and a source region doping region (3), and forming ohmic contact and a pressure welding drain electrode (11) on the back surface of the lower surface of a substrate (101);
in step S3, the ion implantation is performed at an energy of 200Kev, the ion implantation temperature is 450 ℃, and the ion implantation dose is 2×10 11 ～5×10 15 cm -2 。
2. The trench silicon carbide transistor of claim 1, wherein:
the trench type silicon carbide transistor is a MOSFET device, the doping types of the substrate (101), the buffer layer (102), the epitaxial thin film (103) and the source region doping region (3) are all of a first conduction type, the doping type of the base region doping region (2) is of a second conduction type, and the doping types of the first conduction type and the second conduction type are opposite; the doping type is N type or P type, and if the doping type is N type doping, the doping impurity is nitrogen or phosphorus; in the case of P-type doping, the doping impurity is aluminum or boron, and the doping concentration is 1×10 14 ～5×10 21 cm -3 。
3. The trench silicon carbide transistor of claim 1, wherein:
the groove type silicon carbide transistor is an IGBT device, and doping types of the buffer layer (102), the epitaxial film (103) and the source region doping region (3) are all of a first conductivity type; the doping types of the substrate (101) and the base region doping region (2) are both of a second conductivity type, and the doping types of the first conductivity type and the second conductivity type are opposite;the doping type is N type or P type, and if the doping type is N type doping, the doping impurity is nitrogen or phosphorus; in the case of P-type doping, the doping impurity is aluminum or boron, and the doping concentration is 1×10 14 ～5×10 21 cm -3 。
4. The method of manufacturing a trench silicon carbide transistor as claimed in claim 1, wherein,
the dielectric film in the step S2 and the step S5 is a single-layer film or a composite layer film formed by silicon dioxide, silicon nitride, polysilicon, amorphous silicon or metal.
5. The method of manufacturing a trench silicon carbide transistor as claimed in claim 1, wherein,
in the step S4, the annealing atmosphere is vacuum, nitrogen or argon atmosphere, the annealing temperature is 300-3000 ℃, and the annealing time is 0.1 min-1000 hours.
6. The method of manufacturing a trench silicon carbide transistor as claimed in claim 1, wherein,
in step S5, the etching is a reactive ion etching technology or an inductively coupled plasma etching technology or a combination thereof; the etching gas is SF 6 、CF 4 、O 2 Or more than one HBr.
7. The method of manufacturing a trench silicon carbide transistor as claimed in claim 1, wherein,
in step S6, the semiconductor thin film (15) is made of one or more of polycrystalline silicon, amorphous silicon, and single crystal silicon.
8. The method of manufacturing a trench silicon carbide transistor as claimed in claim 1, wherein,
in step S12, the ohmic contact, the source electrode (10) and the drain electrode (11) are all made of metal or conductive material.
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