CN108417617B - Silicon carbide groove type MOSFETs and preparation method thereof - Google Patents

Silicon carbide groove type MOSFETs and preparation method thereof Download PDF

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CN108417617B
CN108417617B CN201810164916.9A CN201810164916A CN108417617B CN 108417617 B CN108417617 B CN 108417617B CN 201810164916 A CN201810164916 A CN 201810164916A CN 108417617 B CN108417617 B CN 108417617B
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layer
type
silicon carbide
contact
gate electrode
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CN108417617A (en
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申占伟
张峰
赵万顺
王雷
温正欣
闫果果
刘兴昉
孙国胜
曾一平
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Institute of Semiconductors of CAS
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Abstract

The disclosure provides silicon carbide trench MOSFETs and a method of making the same. The gate electrode contact of the MOSFETs is positioned on the side wall of the main groove, the bottom of the groove forms a source electrode metal contact, and when the MOSFETs are conducted in the forward direction, electrons flow through the inversion layer on the side wall of the groove from bottom to top to form a reverse conducting channel different from the traditional groove type MOSFETs; when reverse blocking is carried out, the metal contact of the source electrode at the bottom of the groove effectively shields the high electric field of the device body area, so that the electric field of a device gate medium is greatly reduced, avalanche occurs at a PN junction of the device body area, the prepared silicon carbide groove type MOSFETs have lower forward conduction resistance and higher reverse blocking capability, and the static and dynamic working reliability of the device is improved.

Description

Silicon carbide groove type MOSFETs and preparation method thereof
Technical Field
The invention relates to a structure of a silicon carbide groove type metal-oxide-semiconductor field effect transistor (MOSFET) and a preparation method thereof, in particular to a manufacturing method of silicon carbide groove type MOSFETs with reverse conduction channels.
Background
The silicon carbide MOSFET is the fastest-developing wide bandgap power semiconductor device at present, and the physical and electrical characteristics of the silicon carbide have obvious advantages compared with the traditional silicon material, and the silicon carbide MOSFET occupies an extremely important position in the aspects of energy conservation and emission reduction. The surface of the channel of the MOSFET with the vertical silicon carbide groove gate structure is a nonpolar surface and has higher mobility and higher cellular integration level, so that the silicon carbide groove MOSFET becomes a key research object of the next generation of power electronic devices, and can be widely applied to the fields of electric automobiles, charging piles, uninterruptible power supplies, smart power grids and the like.
However, on the one hand, the channel carrier mobility of the silicon carbide trench MOSFET is still much lower than that of the silicon carbide bulk material, thus reducing the on-state characteristics of the device; on the other hand, the critical breakdown electric field of the silicon carbide is larger, so that the electric field in the gate dielectric is sharply increased, particularly the two-dimensional electric field concentration phenomenon of the groove corner of the groove is serious, and the reliability of the gate dielectric of the silicon carbide MOSFET in high-frequency, high-temperature and high-power states is greatly reduced, so that the long-term stable operation of the device is not facilitated.
Disclosure of Invention
Technical problem to be solved
In view of the above, the present disclosure provides silicon carbide trench MOSFETs to alleviate the problems of reduced on-state characteristics, reduced reliability, and the like caused by silicon carbide MOSFET devices in the prior art.
(II) technical scheme
According to an aspect of the present disclosure, there is provided a silicon carbide trench MOSFETs, including: an n + + type silicon carbide substrate; the n + type buffer layer grows on the n + + type silicon carbide substrate; the n-drift layer grows on the n + type buffer layer; the n-type current transmission layer grows on the n-drift layer and comprises a p-type channel layer, a p + type shielding layer, an n + + type source region conducting layer and a p + + type base region conducting layer; the main groove region comprises a gate oxide layer and a gate electrode contact arranged on the surface of the gate oxide layer; and a drain electrode metal contact which is arranged on the lower surface of the n + + type silicon carbide substrate and is made of AlTi, Ni, TiW or AlTi and used for forming ohmic contact with an external component.
In some embodiments of the present disclosure, the main trench region further includes a main trench, a bottom surface of the main trench is located above an upper surface of the p + -type shielding layer and below an upper surface of the n + + type source region conductive layer; the bottom insulating layer is positioned at the bottom of the main groove, the thickness of the bottom insulating layer is 300-800 nm, and the bottom insulating layer is made of silicon dioxide, silicon nitride and the like; the internal insulating substance completely covers the gate electrode contact and the gate oxide layer, is made of insulating media such as silicon dioxide, silicon nitride and the like, and has a flattened surface; the contact through hole is positioned in the center of the main groove, the width of the contact through hole is smaller than the distance between the gate electrode contacts on the two sides of the main groove, and the lower surface of the contact through hole is flush with the lower surface of the main groove; the source electrode is in metal contact and is positioned at the bottom of the contact through hole and on the n + + type source region conducting layer and the p + + type base region conducting layer, and the material is a metal combination of AlTi, Ni, TiW, AlTi and the like; and a source region metal pad 58 disposed on the source electrode metal contact, made of Al, filled in the contact via hole and on the upper portion of the horizontal surface of the internal insulating material, and kept insulated from the gate electrode contact.
In some embodiments of the present disclosure, the gate oxide layer is formed on the upper surface of the n-type current transmission layer and on the surfaces of the two sidewalls in the main trench.
In some embodiments of the present disclosure, the gate electrode is contacted and closely disposed on the surface of the gate oxide layer, the lower portion is closely attached to the upper surface of the bottom insulating layer, the top end is higher than the upper surface of the P-type channel layer, and the material is highly doped polysilicon; when the top end of the gate electrode contact is not higher than the upper surface of the n-type current transmission layer, the gate electrode contact is arranged on the surfaces of the gate oxide layers on the two side walls in the main groove; when the gate electrode is in contact with and extends out of the main groove, the gate electrode is in contact with the gate oxide layers arranged on the two side walls in the main groove and the gate oxide layer on the upper surface of the n-type current transmission layer outside the main groove.
In some embodiments of the present disclosure, wherein the p-type channel layer has a doping concentration in a range of 1 × 1016cm-3～1×1018cm-3The distance between the upper surface of the n-type current transmission layer and the upper surface of the n-type current transmission layer is 0.0-0.7 mu m; the p + type shielding layerDoping concentration range 1X 1018cm-3～1×1020cm-3The upper surface of the p-type channel layer is tightly attached to the lower surface of the p-type channel layer, and the distance between the upper surface of the p + type shielding layer and the upper surface of the p-type channel layer is 0.3-1 mu m; the doping concentration range of the n + + type source region conducting layer is 5 multiplied by 1019cm-3～1×1020cm-3The whole body is positioned in the p-type channel layer and the p + type shielding layer at the same time, the upper surface of the whole body is lower than the upper surface of the p-type channel layer, and the lower surface of the whole body is higher than the lower surface of the p + type shielding layer; and the p + + type base region conductive layer with a doping concentration range of 1 × 1020cm-3～1×1021cm-3The lower surface of the p-type channel layer is tightly attached to the upper surface of the n + + type source region conducting layer, and the upper surface of the p-type channel layer is tightly attached to the lower surface of the n + + type source region conducting layer.
In accordance with another aspect of the present disclosure, there is also provided a method of manufacturing silicon carbide trench MOSFETs according to any one of claims 1 to 5, the method comprising:
step A: manufacturing a silicon carbide epitaxial wafer substrate; sequentially epitaxially growing an n + -type buffer layer, an n-drift layer and an n-type current transmission layer on an n + + type silicon carbide substrate from bottom to top;
and B: manufacturing active region doping in the n-type current transmission layer;
and C: making a contact through hole of the main groove region on the n-type current transmission layer and the upper part of the n-type current transmission layer;
step D: manufacturing a source electrode metal contact and a drain electrode metal contact; and
step E: manufacturing a source region metal pad; the source region metal pad completely covers the contact via and is insulated from the gate electrode contact.
In some embodiments of the present disclosure, wherein the step B comprises:
substep B1: a p-type channel layer and a p + type shielding layer are formed in the n-type current transmission layer from top to bottom;
substep B2: manufacturing an n + + type source region conducting layer in the p type channel layer and the p + type shielding layer, wherein the whole body is positioned in the p type channel layer and the p + type shielding layer at the same time, the upper surface of the n + + type source region conducting layer is lower than the upper surface of the p type channel layer, and the lower surface of the n + + type source region conducting layer is higher than the lower surface of the p + type shielding layer; and
substep B3: and manufacturing a p + + type base region conducting layer in the p type channel layer and the n + + type source region conducting layer, wherein the lower surface of the p + + type base region conducting layer is tightly attached to the lower surface of the n + + type source region conducting layer, and the upper surface of the p + + type base region conducting layer is tightly attached to the upper surface of the p type channel layer.
In some embodiments of the present disclosure, wherein the step C comprises:
substep C1: activating the ion implantation doping in the step B;
substep C2: manufacturing a main groove, wherein the bottom surface of the main groove is positioned above the upper surface of the p + type shielding layer and below the upper surface of the n + + type source region conducting layer;
substep C3: filling the main trench, wherein the filling material can be silicon dioxide or silicon nitride;
substep C4: dry etching the filling material in the substep C3 to finally form a bottom insulating layer at the bottom of the main trench, wherein the thickness of the bottom insulating layer is 300-800 nm;
a substep C5, cleaning the silicon carbide substrate and preparing a gate oxide layer;
a substep C6, forming a gate electrode contact on the surface of the gate oxide layer, wherein the gate electrode contact is closely arranged on the surface of the gate oxide layer, the lower part of the gate electrode contact is closely attached to the upper surface of the bottom insulating layer, and the top end of the gate electrode contact is higher than the upper surface of the P-type channel layer; when the gate electrode contact is completely arranged in the main groove, the gate electrode contact is made on the surfaces of the gate oxide layers at the two side walls in the main groove; and
substep C7: and filling an internal insulating substance in the main groove with the formed gate electrode contact and the upper part of the n-type current transmission layer, and performing dry etching on the internal insulating substance to form a contact through hole.
In some embodiments of the present disclosure, wherein the sub-step C6 in the step C, when the gate electrode contact extends out of the main trench arrangement, the gate electrode contact is made on the surface of the gate oxide layer at the two sidewalls inside the main trench and the surface of the gate oxide layer on the upper surface of the n-type current transport layer outside the main trench.
In some embodiments of the present disclosure, wherein the active region doping is prepared in step B, the active region doping may be directly fabricated under the upper surface of the n-type current transport layer.
(III) advantageous effects
According to the technical scheme, the silicon carbide trench type MOSFETs provided by the disclosure have at least one or part of the following beneficial effects:
(1) due to the blocking effect of the p-type shielding layer at the bottom of the groove, the doping of the channel region of the device can be further reduced, and the carrier mobility is improved;
(2) the carrier mobility of the device is improved, so that the conduction performance is enhanced;
(3) when reverse blocking is carried out, the metal contact of the source electrode at the bottom of the groove can effectively shield a high electric field of a device body area, so that the electric field of a device gate medium is greatly reduced;
(4) the reduction of the electric field of the device gate dielectric improves the blocking working reliability of the device;
(5) the bottom of the trench is surrounded by the p-type shielding layer, so that the overlapping area of the gate electrode contact and the drain electrode metal contact is reduced, and the device has smaller Miller charge.
(6) Compared with the traditional groove type MOSFETs, the silicon carbide groove type MOSFETs have higher Beri plus optimum value and smaller dynamic switching loss.
Drawings
Fig. 1 is a schematic structural view of silicon carbide trench MOSFETs provided by the present disclosure.
Fig. 2 is a flow chart of a method of fabricating silicon carbide trench MOSFETs according to the present disclosure.
FIG. 3 is a schematic structural view of the silicon carbide epitaxial wafer substrate produced in step A of the production method.
Fig. 4 is a schematic structural diagram of the p-type channel layer and the p + -type shielding layer after the processing in step B and the sub-step B1 in the preparation method.
Fig. 5 is a schematic structural diagram of the n + + type source region conductive layer after processing in sub-step B2 in step B of the preparation method.
Fig. 6 is a schematic structural diagram of the p + + type base region conductive layer after processing in sub-step B3 in step B of the preparation method.
Fig. 7 is a schematic structural diagram of a main groove processed after substep C2 in substep C of the preparation method.
Fig. 8 is a schematic structural view of the main trench and the upper portion of the n-type current transport layer filled with a substance after substep C3 in substep C of the above-described fabrication method.
Fig. 9 is a schematic structural diagram of a bottom insulating layer formed at the bottom of the main trench after substep C4 in substep C of the preparation method.
Fig. 10 is a schematic structural diagram of a gate oxide layer formed after substep C5 in substep C of the preparation method.
Fig. 11 is a schematic structural diagram of the method for preparing a gate oxide layer completely filled with highly doped polysilicon in substep C6 in substep C.
Fig. 12 is a schematic structural diagram of a gate electrode contact formed on the surface of the gate oxide layer on the two side walls inside the main trench after substep C6 in substep C of the preparation method.
Fig. 13 is a schematic structural diagram of the manufacturing method, in which in sub-step C7, the main trench where the gate electrode contact is formed and the upper portion of the n-type current transport layer are filled with the internal insulating material in step C.
Fig. 14 is a schematic structural diagram of a contact via formed after substep C7 in substep C of the fabrication process.
Fig. 15 is a schematic structural diagram of a source electrode metal contact and a drain electrode metal contact made after substep D1 in substep D of the method.
Fig. 16 is a schematic structural view of trench MOSFETs made of silicon carbide after step E in the above-described manufacturing method.
Fig. 17 is a schematic structural diagram of silicon carbide trench MOSFETs manufactured in step D and E after substep C6 in step C of the manufacturing method, in which gate electrode contacts are formed on the surfaces of the gate oxide layers on the two sidewalls in the main trench and the surface of the gate oxide layer on the upper surface of the n-type current transport layer outside the main trench, respectively.
Fig. 18 is a schematic structural view of silicon carbide trench MOSFETs fabricated by directly attaching active region dopants under the upper surface of the n-type current transport layer in step B, and then directly performing steps C, D, and E.
[ description of main reference numerals in the drawings ] of the embodiments of the present disclosure
A 10-n + + type silicon carbide substrate; a 20-n + type buffer layer; a 30-n-drift layer;
a 40-n type current transport layer;
a 41-p type channel layer; a 42-p + type shielding layer;
a 43-n + + type source region conductive layer; 44-p + + type base conductive layer;
50-a main trench region;
51-a main trench; 52-bottom insulating layer;
53-gate oxide layer; 54-gate electrode contact;
55-internal insulating substance; 56-contact vias;
57-source electrode metal contact; 58-source region metal pad;
60-drain electrode metal contact.
Detailed Description
In the present disclosure, a device of silicon carbide trench MOSFETs with reverse conducting channels and a method for fabricating the same are provided. The contact of a gate electrode of the device is positioned on the side wall of the main groove, a source electrode metal contact is formed at the bottom of the groove, and when the device is conducted in the forward direction, electrons flow through the inversion layer of the side wall of the groove from bottom to top to form a reverse conducting channel different from the traditional groove type MOSFETs; when reverse blocking is carried out, the metal contact of the source electrode at the bottom of the groove effectively shields the high electric field of the device body area, so that the electric field of the device gate dielectric is greatly reduced, and avalanche occurs at the PN junction of the device body area. The prepared silicon carbide groove type MOSFETs have lower forward on-resistance and higher reverse blocking capability, and the static and dynamic working reliability of the device is improved.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In an exemplary embodiment of the present disclosure, there is provided a silicon carbide trench MOSFETs, and fig. 1 is a schematic structural diagram of a silicon carbide trench mosfet provided in this embodiment, and as shown in fig. 1, the silicon carbide trench MOSFETs provided in the present disclosure include:
an n + + type silicon carbide substrate 10; an n + type buffer layer 20; an n-drift layer 30; an n-type current transport layer 40; a main trench region 50; and a drain electrode metal contact 60;
the following is a detailed description of each component of the silicon carbide trench MOSFETs provided by the present disclosure.
As shown in fig. 1, the present disclosure provides silicon carbide trench MOSFETs, wherein the n-type current transport layer 40 includes:
a p-type channel layer 41 with a doping concentration in the range of 1 × 1016cm-3～1×1018cm-3The distance from the upper surface of the n-type current transmission layer 40 to the upper surface of the n-type current transmission layer is 0.0-0.7 mu m;
p + type shielding layer 42 with doping concentration range of 1 × 1018cm-3～1×1020cm-3The upper surface of the p-type channel layer 41 is closely attached to the lower surface of the p-type channel layer 41, and the distance between the upper surface of the p + type shielding layer 42 and the upper surface of the p-type channel layer 41 is 0.3-1 mu m;
n + + type source region conductive layer 43 with doping concentration range of 5 × 1019cm-3～1×1020cm-3The whole of the p-type channel layer 41 and the p + type shielding layer 42 are positioned in the p-type channel layer 41 and the p + type shielding layer 42 at the same time, the upper surface of the p-type channel layer is lower than the upper surface of the p-type channel layer 41, and the lower surface of the p + type shielding layer is higher than the lower surface of the p + type shielding layer 42; and
p + + type base conductive layer 44 having a doping concentration range of 1 × 1020cm-3～1×1021cm-3The lower surface of the n + + type source region conductive layer 43 is closely attached to the lower surface of the n + + type source region conductive layer, and the upper surface of the n + + type source region conductive layer is closely attached to the upper surface of the p type channel layer 41.
As shown in fig. 1, the present disclosure provides silicon carbide trench MOSFETs, wherein the main trench region 50 includes:
a main trench 51, wherein the bottom surface of the main trench 51 is located above the upper surface of the p + -type shielding layer 42 and below the upper surface of the n + + type source region conductive layer 43;
the bottom insulating layer 52 is positioned at the bottom of the main groove 51, the thickness of the bottom insulating layer 52 is 300-800 nm, and the bottom insulating layer is made of silicon dioxide, silicon nitride and the like;
a gate oxide layer 53 formed on the upper surface of the n-type current transport layer 40 and the surfaces of both sidewalls in the main trench 51;
a gate electrode contact 54 closely arranged on the surface of the gate oxide layer 53, the lower part of the gate electrode contact is closely attached to the upper surface of the bottom insulating layer 52, the top end of the gate electrode contact is higher than the upper surface of the P-type channel layer 41, and the gate electrode contact is made of highly doped polysilicon; when the top end of the gate electrode contact 54 is not higher than the upper surface of the n-type current transmission layer 40, the gate electrode contact 54 is arranged on the surfaces of the gate oxide layers 53 at the two side walls in the main trench 51; when the gate electrode contact 54 extends out of the main trench 51, the gate electrode contact 54 is arranged on the surfaces of the gate oxide layer 53 at the two side walls in the main trench 51 and the surface of the gate oxide layer 53 on the upper surface of the n-type current transmission layer 40 outside the main trench 51;
an inner insulating material 55 covering the bottom insulating layer 52, the gate electrode contact 54 and the gate oxide layer 53, and made of insulating medium such as silicon dioxide and silicon nitride, and having a planarized surface;
a contact via 56 located in the center of the main trench, having a width smaller than the distance between the gate electrode contacts 54 on both sides of the main trench 51, and having a lower surface level with the lower surface of the main trench 51;
a source electrode metal contact 57 which is positioned at the bottom of the contact through hole and on the n + + type source region conducting layer 43 and the p + + type base region conducting layer 44 and is made of a metal combination of AlTi, Ni, TiW, AlTi and the like; and
a source metal pad 58, which is made of Al, is disposed on the source electrode metal contact 57, fills the contact via 56 and the upper portion of the horizontal surface of the inter-insulating material 55, and remains insulated from the gate electrode contact 54.
As shown in fig. 1, the silicon carbide trench MOSFETs provided by the present disclosure further include a drain metal contact 60 disposed on a lower surface of the n + + type silicon carbide substrate 10, and the material is AlTi, Ni, TiW, AlTi, or the like.
The disclosure also provides a preparation method of the silicon carbide groove type MOSFETs, which is used for preparing the silicon carbide groove type MOSFETs.
Fig. 2 is a schematic view of the steps of the preparation method, and as shown in fig. 2, the preparation method comprises the following steps:
step A: manufacturing a silicon carbide epitaxial wafer substrate; the method comprises the steps that an n + -type buffer layer 20, an n-drift layer 30 and an n-type current transmission layer 40 are sequentially epitaxially grown on an n + + type silicon carbide substrate 10 from bottom to top;
and B: making active region doping in the n-type current transport layer 40 includes:
substep B1: depositing an implantation mask on the n-type current transmission layer 40, carrying out photoetching patterning, and manufacturing a p-type channel layer 41 and a p + -type shielding layer 42 from top to bottom in the n-type current transmission layer 40 by using a doping method such as ion implantation;
the sub-step B1 in which the p-type channel layer 41 has a doping concentration in the range of 1 × 1016cm-3～1×1018cm-3The distance from the upper surface of the n-type current transmission layer 40 to the upper surface of the n-type current transmission layer is 0-0.7 mu m; p + type shielding layer 42 with doping concentration range of 1 × 1018cm-3～1×1020cm-3The distance between the upper surface of the p-type channel layer 41 and the upper surface of the p-type channel layer is 0.3-1 μm;
substep B2: forming an implantation mask layer by using a photoetching transfer pattern, and manufacturing an n + + type source region conducting layer 43 in the p type channel layer 41 and the p + type shielding layer 42 by using doping methods such as ion implantation and the like;
the sub-step B2, in which the n + + type source region conductive layer 43 has a doping concentration range of 5 × 1019cm-3～1×1020cm-3The whole of the p-type channel layer 41 and the p + type shielding layer 42 are positioned in the p-type channel layer 41 and the p + type shielding layer 42 at the same time, the upper surface of the p-type channel layer is lower than the upper surface of the p-type channel layer 41, and the lower surface of the p + type shielding layer is higher than the lower surface of the p + type shielding layer 42;
substep B3: forming an injection mask layer by utilizing a photoetching transfer pattern, and manufacturing a p + + type base region conducting layer 44 in the p type channel layer 41 and the n + + type source region conducting layer 43 by utilizing doping methods such as ion injection and the like;
the substep B3, in which the p + + type base conductive layer 44 is doped with a concentration ranging from 1 × 1020cm-3～1×1021cm-3The lower surface thereof andthe lower surface of the n + + type source region conductive layer 43 is closely attached, and the upper surface is closely attached to the upper surface of the p type channel layer 41.
And C: forming a contact via 56 in the n-type current carrying layer 40 and above it in the main trench region 50, comprising:
substep C1: removing the implantation mask layer in the step B, cleaning the silicon carbide surface, activating the ion implantation doping in the step B, removing a carbon film, an AlN film and the like covering the silicon carbide surface, and cleaning the silicon carbide surface in a standard manner;
the substep C1, wherein annealing is performed for 10-30 minutes at 1600-1800 ℃ and 600-700Torr for activating the ion implantation doping in the step B by using methods such as carbon film, AlN film covering, silane inhibition, etc.;
substep C2: making a main groove 51, depositing silicon dioxide or polysilicon or a metal medium with a certain thickness on the n-type current transmission layer 40 to form a barrier layer, carrying out photoetching and patterning, carrying out dry etching on the barrier layer, and carrying out dry etching on a silicon carbide substrate by using the barrier layer through physical and chemical etching means such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP) to form the main groove 51;
the sub-step C2, wherein the etching gas may be SF6/O2、NF3/Ar、CF4、HBr、CHF3/O2、C4F8/O2The etching conditions are as follows: ICP power is 600W-1000W, bias power is 100W-300W, and temperature is 15-70 ℃;
the sub-step C2, wherein the bottom surface of main trench 51 is located above the upper surface of p + -type shielding layer 42 and below the upper surface of n + + -type source region conductive layer 43;
the substep C2, wherein the silicon carbide substrate is annealed in a hydrogen or argon atmosphere at a temperature ranging from 1200 ℃ to 1700 ℃ to repair the main trench 51 and reduce the interface roughness of the sidewalls of the main trench 80 and the associated interface defects;
substep C3: filling the main trench 51 by using thin film deposition techniques such as physical vapor deposition, chemical vapor deposition, atomic layer deposition and the like, wherein the filling material can be a medium such as silicon dioxide, silicon nitride and the like, completely covers the inside of the main trench 51 and the upper part of the n-type current transmission layer 40, and has a flattened surface;
substep C4: dry etching the filling material in the substep C3 by physical, chemical or other etching means, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP), to finally form a bottom insulating layer 57 with a certain thickness at the bottom of the main trench 51, wherein the thickness of the bottom insulating layer 57 is 300nm to 800 nm;
the sub-step C4, wherein the etching gas may be SF6/O2、NF3/Ar、CF4、CHF3/O2、C4F8/O2And the like;
substep C5, cleaning the silicon carbide substrate by organic and inorganic methods, and finally obtaining the gate oxide layer 53 by physical or chemical vapor deposition, high-temperature thermal oxidation and post-oxidation annealing, atomic layer deposition and other methods;
the substep C5, wherein, firstly, ultrasonic cleaning is carried out by acetone and ethanol in sequence, and then deionized water is used for washing; boiling the SiC substrate subjected to organic ultrasound in concentrated sulfuric acid and hydrogen peroxide solution for at least 10 min; boiling the silicon carbide substrate which is boiled with concentrated sulfuric acid for more than 10min by using a first liquid and a second liquid in sequence, washing the silicon carbide substrate by using deionized water, and drying the silicon carbide substrate by using nitrogen for standby application, wherein the first liquid is a mixed liquid of ammonia water, hydrogen peroxide and deionized water, and the second liquid is a mixed liquid of hydrochloric acid, hydrogen peroxide and deionized water;
the substep C5, wherein the SiC substrate subjected to standard cleaning (RCA) is oxidized for about half an hour in a wet oxygen environment at about 1100 ℃ to form a sacrificial oxide layer, and the sacrificial oxide layer is removed by diluted HF ultrasonic rinsing;
and the substep C5, wherein, the dry oxygen oxidation is carried out for about half an hour under the condition of 1100-1300 ℃, and the annealing is carried out for 1-3 hours under the conditions of 1200-1300 ℃ and NO atmosphere, and the annealing atmosphere is not only NO but also POCl3，H2，N2O，P2O5Sb + NO, etc., finally obtained gate oxide layer 53；
In the sub-step C5, as an option, the gate oxide layer 53 may be formed by atomic layer deposition or the like;
and a sub-step C6 of filling the surface of the formed gate oxide layer 53 and the main trench 51 with highly doped polysilicon by using a thin film deposition technique such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. Then, by utilizing etching means such as physical and chemical etching, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP), the deposited high-doped polysilicon is etched in a dry method, and finally, a gate electrode contact 54 is formed on the surface of the gate oxide layer 53;
the sub-step C6, wherein the gate electrode contact 54 is closely attached to the surface of the gate oxide layer 53, the lower portion is closely attached to the upper surface of the bottom insulating layer 52, and the top end is higher than the upper surface of the P-type channel layer 41;
said sub-step C6, wherein, when the gate electrode contact 54 is completely disposed inside the main trench 51, the gate electrode contact 54 is located on the surface of the gate oxide layer 53 at both sidewalls inside the main trench 51;
said sub-step C6, wherein, when filling the highly doped polysilicon, the highly doped polysilicon is to completely cover the bottom insulating layer 52 and the gate oxide layer 53 and has a planarized surface;
the substep C6, wherein the etching gas used in etching is SF6/O2、NF3/Ar、CF4、CHF3/O2、C4F8/O2A gas or a combination.
Substep C7: the main trench 51 in which the gate electrode contact 54 has been formed and the upper portion of the n-type current transport layer 40 are filled with an inner insulating material 55 using a thin film deposition technique such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. Performing photoetching patterning, and performing dry etching on the internal insulating substance 55 by physical and chemical etching means, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP), to finally form a contact through hole 56;
in sub-step C7, the internal insulating material 55 may be an insulating medium such as silicon dioxide or silicon nitride, and the internal insulating material 55 completely covers the sidewall bottom insulating layer 52, the gate electrode contact 54 and the gate oxide layer 53 and has a planarized surface;
the sub-step C7, wherein the etching gas for the dry etching may be SF6/O2、NF3/Ar、CF4、CHF3/O2、C4F8/O2Combinations of gases, etc.;
the sub-step C7, in which the contact via 56 is located at the center of the main trench 51, has a width smaller than the distance between the gate electrode contacts 54 on both sides, and has a lower surface level with the lower surface of the main trench 51.
Step D: making a source electrode metal contact 57 and a drain electrode metal contact 60;
substep D1: photoetching and patterning, sequentially depositing multilayer metals of Ni, Ti and Al by using a film deposition method such as electron beam evaporation or sputtering, and stripping to form a source electrode metal contact 57;
in the substep D1, the source electrode metal contact 57 is located at the bottom of the contact via 56 and is closely attached to the n + + type source region conductive layer 43 and the p + + type base region conductive layer 44, and the preparation material is a metal or a combination of AlTi, Ni, TiW, AlTi, etc.;
substep D2: coating photoresist on the front side of the silicon carbide substrate for protection, removing an oxide layer on the back side of the n + + type silicon carbide substrate 10 by using diluted HF, depositing a Ni metal layer on the back side by using a film deposition method such as electron beam evaporation or sputtering to prepare a drain electrode metal contact 60, and removing the photoresist on the front side;
in the substep D2, the drain electrode metal contact 60 is optionally made of a metal or a combination of metals such as AlTi, Ni, TiW, AlTi;
substep D3: annealing the source electrode metal contact 57 and the drain electrode metal contact 60 at a temperature ranging from 900 ℃ to 1100 ℃ under the nitrogen or argon conditions to form ohmic contacts. And
step E: manufacturing a source region metal pad 58;
depositing a thicker metal A1 layer in the contact through hole 56 and on the upper part of the horizontal surface of the internal insulating material 55 by using a film deposition method such as electron beam evaporation or sputtering, carrying out photoetching patterning, and interconnecting to form a source region metal pad 58;
step E, wherein source region metal pad 58 completely covers contact via 56 and is insulated from gate electrode contact 54.
And a substep C6 in the step C, wherein when the gate electrode contact 54 extends out of the main trench 51, the gate electrode contact 54 is disposed on the surfaces of the gate oxide layer at the two sidewalls in the main trench 51 and the surface of the gate oxide layer 53 on the upper surface of the n-type current transport layer 40 outside the main trench 51, and then the step D, E is performed to manufacture the silicon carbide trench MOSFETs, as shown in fig. 17.
It should be noted that, the active region doping is prepared in the step B, or the active region doping may be first fabricated under the upper surface of the n-type current transmission layer 40, then a structure with a certain thickness identical to the material of the n-type current transmission layer 40 is epitaxially formed on the upper portion of the upper surface of the n-type current transmission layer 40, and then the steps C, D and E are continued to fabricate the silicon carbide trench MOSFETs.
It should be further noted that, the active region doping prepared in step B may be directly formed under the upper surface of the n-type current transport layer 40, and then steps C, D, and E are directly performed to prepare the silicon carbide trench MOSFETs, as shown in fig. 18.
After the steps a, B, C, D and E, the preparation of the silicon carbide trench MOSFETs bare chip device is completed, and the electron flow direction when the silicon carbide trench MOSFETs are in forward conduction is shown by dotted arrows in fig. 1, 16, 17 and 18, which is different from the conventional trench MOSFET conduction mode and is a trench MOSFET with a reverse conduction channel.
The substrate material used in the above embodiments is not limited to silicon carbide material, but may also include power electronic semiconductor materials such as silicon, gallium nitride, gallium oxide, and diamond. When other semiconductor materials are used as the substrate, the finally-formed trench MOSFETs and the manufacturing method thereof are all included in the scope of the present disclosure.
In light of the above description, those skilled in the art should clearly recognize the disclosed silicon carbide trench MOSFETs and methods of making the same.
In summary, according to the silicon carbide trench MOSFETs and the method for manufacturing the same provided by the present disclosure, the gate electrode contact of the device is located on the sidewall of the main trench, the source electrode metal contact is formed at the bottom of the trench, and when conducting in the forward direction, the reverse conducting channel different from the conventional trench MOSFETs is formed when the electron flow direction is from bottom to top (as shown by dotted arrows in fig. 1, 16, 17, and 18); when reverse blocking is carried out, the metal contact of the source electrode at the bottom of the groove can effectively shield a high electric field of a device body area, so that the electric field of a device gate medium is greatly reduced, and avalanche occurs at a PN junction of the device body area. The prepared silicon carbide groove type MOSFETs have lower forward on-resistance and higher reverse blocking capability, and the static and dynamic working reliability of the device is improved.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.
And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Unless otherwise indicated, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present disclosure. In particular, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Generally, the expression is meant to encompass variations of ± 10% in some embodiments, 5% in some embodiments, 1% in some embodiments, 0.5% in some embodiments by the specified amount.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (9)

1. Silicon carbide trench MOSFETs, comprising:
an n + + type silicon carbide substrate (10);
an n + type buffer layer (20) grown on the n + + type silicon carbide substrate (10);
an n-drift layer (30) grown on the n + -type buffer layer (20);
the n-type current transmission layer (40) grows on the n-drift layer (30) and comprises a p-type channel layer (41), a p + type shielding layer (42), an n + + type source region conducting layer (43) and a p + + type base region conducting layer (44); the upper surface of the p + type shielding layer (42) is closely attached to the lower surface of the p type channel layer (41); the whole n + + type source region conducting layer (43) is positioned in the p type channel layer (41) and the p + type shielding layer (42) at the same time, the upper surface of the n + + type source region conducting layer is lower than the upper surface of the p type channel layer (41), and the lower surface of the n + + type source region conducting layer is higher than the lower surface of the p + type shielding layer (42); the lower surface of the p + + type base region conducting layer (44) is closely attached to the lower surface of the n + + type source region conducting layer (43), and the upper surface of the p + + type base region conducting layer is closely attached to the upper surface of the p type channel layer (41);
a main trench region (50) comprising: a main groove (51); a gate oxide layer (53) and a gate electrode contact (54) are generated on the upper surface of the n-type current transmission layer (40) and the surfaces of the two side walls in the main groove (51); and
and the drain electrode metal contact (60) is arranged on the lower surface of the n + + type silicon carbide substrate (10), is made of AlTi, Ni, TiW or AlTi and is used for forming ohmic contact with an external component.
2. The silicon carbide trench MOSFETs of claim 1,
the bottom surface of the main groove (51) is positioned above the upper surface of the p + -type shielding layer (42) and below the upper surface of the n + + type source region conducting layer (43);
the main trench region (50) further comprises:
the bottom insulating layer (52) is positioned at the bottom of the main groove (51), the thickness of the bottom insulating layer (52) is 300-800 nm, and the bottom insulating layer is made of silicon dioxide or silicon nitride;
an inner insulating material (55) made of silicon dioxide or silicon nitride;
the contact through hole (56) is positioned in the center of the main groove, the width of the contact through hole is smaller than the distance between the gate electrode contacts (54) on the two sides of the main groove (51), and the lower surface of the contact through hole is flush with the lower surface of the main groove (51);
a source electrode metal contact (57) located at the bottom of the contact via and made of AlTi, Ni, TiW, AlTi metal or a combination thereof; and
a source region metal pad (58), of Al, is filled in the contact via (56) and on the upper portion of the horizontal surface of the internal insulating substance (55) and remains insulated from the gate electrode contact (54).
3. The silicon carbide trench MOSFETs of claim 1,
the distance between the upper surface of the p-type channel layer (41) and the upper surface of the n-type current transmission layer (40) is 0.0-0.7 mu m;
the distance between the upper surface of the p + type shielding layer (42) and the upper surface of the p type channel layer (41) is 0.3-1 mu m.
4. Silicon carbide trench MOSFETs according to claim 1, wherein the gate electrode contact (54) is closely disposed on the surface of the gate oxide layer (53), the lower portion is closely disposed on the upper surface of the bottom insulating layer (52), the top end is higher than the upper surface of the P-type channel layer (41), the material is highly doped polysilicon, and when the top end of the gate electrode contact (54) is not higher than the upper surface of the n-type current transport layer (40), the gate electrode contact (54) is disposed on the surface of the gate oxide layer (53) at both side walls in the main trench (51).
5. Silicon carbide trench MOSFETs according to claim 1, wherein the gate electrode contact (54) is disposed on the surface of the gate oxide layer (53) at both sidewalls inside the main trench (51) and on the surface of the gate oxide layer (53) on the upper surface of the n-type current transport layer (40) outside the main trench (51) when the gate electrode contact (54) extends out of the main trench (51).
6. A method of manufacturing silicon carbide trench MOSFETs according to any one of claims 1 to 5, comprising:
step A: manufacturing a silicon carbide epitaxial wafer substrate; an n + -type buffer layer (20), an n-drift layer (30) and an n-type current transmission layer (40) are epitaxially grown on an n + + type silicon carbide substrate (10) from bottom to top in sequence;
and B: making active region doping in the n-type current transport layer (40);
and C: forming a contact via (56) in the main trench region (50) in the n-type current transport layer (40) and above the n-type current transport layer;
step D: manufacturing a source electrode metal contact (57) and a drain electrode metal contact (60); and
step E: manufacturing a source region metal pad (58); the source region metal pad (58) completely covers the contact through hole (56) and is insulated from the gate electrode contact (54);
wherein the step B comprises:
a p-type channel layer (41) and a p + -type shielding layer (42) are formed in an n-type current transmission layer (40) from top to bottom, an n + + type source region conducting layer (43) is formed in the p-type channel layer (41) and the p + -type shielding layer (42), the n + + -type source region conducting layer (43) is integrally located in the p-type channel layer (41) and the p + -type shielding layer (42), the upper surface of the n + + -type source region conducting layer (43) is lower than the upper surface of the p-type channel layer (41), the lower surface of the n + + -type source region conducting layer (43) is higher than the lower surface of the p + -type shielding layer (42), a p + + -type base region conducting layer (44) is formed in the p-type channel layer (41) and the n + + -type source region conducting layer (43), the lower surface of the p + + -type base region conducting layer (44) is arranged with the lower surface of the n + + -type source region conducting layer (.
7. The production method according to claim 6, wherein the step C includes:
activating the ion implantation doping in the step B, manufacturing a main groove (51), wherein the bottom surface of the main groove (51) is positioned above the upper surface of the P < + > -type shielding layer (42), the lower surface of the n < + > -type source region conducting layer (43) is filled with the main groove (51), the filling material is silicon dioxide or silicon nitride, dry etching is carried out on the filling material, finally, a bottom insulating layer (57) is manufactured at the bottom of the main groove (51), the thickness of the bottom insulating layer (57) is 300 nm-800 nm, a silicon carbide substrate is cleaned, a gate oxide layer (53) is manufactured, a gate electrode contact (54) is manufactured on the surface of the gate oxide layer (53), the lower part of the gate electrode contact is tightly attached to the upper surface of the bottom insulating layer (52), the top end of the gate electrode contact is higher than the upper surface of the P-type channel layer (41), and when the gate electrode contact (54) is completely arranged in the main groove, making gate electrode contacts (54) on the surfaces of the gate oxide layer (53) at both sidewalls in the main trench (51); and filling an internal insulating substance (55) in the main trench (51) where the gate electrode contact (54) is formed and the upper part of the n-type current transmission layer (40), and dry-etching the internal insulating substance (55) to form a contact through hole (56).
8. A manufacturing method according to claim 6, wherein in the step C, when the gate electrode contact (54) is extended out of the main trench (51) arrangement, the gate electrode contact (54) is made on the surfaces of the gate oxide layer (53) at both sidewalls inside the main trench (51) and on the surface of the gate oxide layer (53) on the upper surface of the n-type current transporting layer (40) outside the main trench (51).
9. The method of claim 6, wherein the active region doping is formed in step B and is formed directly under the upper surface of the n-type current transport layer (40).
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