CN209947846U

CN209947846U - Field effect transistor

Info

Publication number: CN209947846U
Application number: CN201921037535.0U
Authority: CN
Inventors: 姚金才; 杨良; 陈宇
Original assignee: Shenzhen Hester Technology Co Ltd
Current assignee: Shenzhen Hester Technology Co Ltd
Priority date: 2019-07-04
Filing date: 2019-07-04
Publication date: 2020-01-14
Anticipated expiration: 2029-07-04

Abstract

The utility model discloses a field effect transistor, separate through the well region with in the field effect transistor, and the region between two adjacent well regions does not carry out ion implantation and selects the portion above that makes the schottky contact through growing metal, make peripheral well region and epitaxial PN junction and the schottky contact constitute a junction barrier schottky diode jointly, and through making this junction barrier schottky diode substitute the parasitic PIN diode of device self or outside fast recovery diode that anti-parallel was used outside in the use, make the device have lower conduction pressure drop, lower power loss and faster work efficiency, the industrial cost has also been reduced.

Description

Field effect transistor

Technical Field

The utility model relates to a semiconductor device technical field especially relates to a field effect transistor.

Background

The silicon carbide (SiC) is a third-generation semiconductor material developed after a first-generation semiconductor material, namely silicon and germanium, and a second-band semiconductor material, namely gallium arsenide and indium phosphide, and the wide forbidden band of the silicon carbide material is 2-3 times that of the silicon and the gallium arsenide, so that the semiconductor device can work at a higher temperature and has the capability of emitting blue light; the breakdown electric field of the semiconductor device is higher than that of silicon and gallium arsenide by one order of magnitude, which determines the high-voltage and high-power performance of the semiconductor device; the high saturated electron drift velocity and the low dielectric constant of the high-frequency high-speed high-frequency high-dielectric constant high-frequency high-voltage; the heat conductivity of the silicon carbide is 3.3 times that of silicon and 10 times that of gallium arsenide, so that the silicon carbide material has good heat conducting performance, the integration level of a circuit can be greatly improved in the integrated circuit process, and meanwhile, a cooling and heat dissipation system can be reduced, so that the size of a device is reduced. In summary, the silicon carbide semiconductor material has the advantages of large forbidden band width, high critical breakdown field strength, high saturated electron drift rate, high thermal conductivity, stable chemical properties and the like, so that the silicon carbide-based power device has great application prospects in the aspects of high voltage, high temperature, high frequency, high power, strong radiation and the like. In the field of semiconductor technology, the method is an ideal choice for preparing high-voltage-resistant and large-current power devices. In addition, due to the excellent physical and electrical properties of the silicon carbide and the combination of the design characteristics of a specific process, a common SiC MOSFET device has the advantages of high switching speed, small on-resistance and the like, can realize a high breakdown voltage level under a small epitaxial layer thickness, simultaneously reduces the size of a power switch module, reduces energy consumption, and has obvious advantages in the application fields of power switches, converters and the like. Therefore, with the continuous improvement of silicon carbide materials and device processes, silicon carbide is partially substituted for silicon carbide in the field, which means daily use.

Silicon carbide VDMOS devices generally need to function together with an anti-parallel diode in circuit applications such as traditional inverter circuits, chopper circuits and the like, and generally have two modes: one is to directly use the P well region of the device, N^-Drift region and N⁺A parasitic PIN diode formed in the substrate. However, in this way, since the conduction voltage drop of the silicon carbide PN junction is about 3V, the obtained parasitic silicon carbide diode has a large conduction voltage drop, which greatly increases the power consumption in the circuit in practical application; and due to drift region conductance modulation on forward conductionA large number of excess carriers are injected, so that the reverse recovery characteristic of the parasitic silicon carbide diode is poor, and high power loss is caused, which is contrary to the application concept that green environmental protection is emphasized at present; in addition, because the dislocation of the base vector in the SiC material can induce the stacking fault due to the work of the PN junction, the reliability of the device can be influenced by adopting the parasitic silicon carbide diode in the SiC material as the anti-parallel diode, for example, bipolar degradation is easily caused by long-time work, so that the electrical performance of the device is also degraded along with the degradation, the on-resistance is increased, the blocking leakage current is increased, and the like; meanwhile, the low working efficiency caused by the low working speed is very unfavorable for the application of the silicon carbide VDMOS device in an inverter circuit, a chopper circuit and the like. Secondly, the device and an external Fast Recovery Diode (FRD) are connected in an anti-parallel mode for use, the number of the used devices is increased, the mode can cause the increase of system cost, the increase of volume and the reduction of reliability caused by the increase of metal connecting lines, and finally the popularization of the silicon carbide VDMOS device in the application of circuits such as a traditional inverter circuit, a chopper circuit and the like is hindered to a certain extent.

SUMMERY OF THE UTILITY MODEL

The utility model discloses to not enough among the prior art, provide a field effect transistor to and the preparation method of preparing this kind of field effect transistor, reduced the power loss of device to a certain extent, improved work efficiency, also reduced system cost simultaneously.

In order to solve the technical problem, the utility model discloses a following technical scheme can solve:

the utility model discloses a field effect transistor, N type epitaxy on including N type substrate and locating N type substrate, its characterized in that: the Schottky barrier Schottky diode is characterized in that a P-well region formed by P-type ion injection is arranged on the N-type epitaxy, a PN junction is formed at the interface of the P-well region and the N-type epitaxy, a Schottky contact is arranged on the N-type epitaxy between two adjacent P-well regions, and the Schottky and the PN junction form a junction barrier Schottky diode together.

Preferably, the P-well region is provided with an N-type ion implanted source contact N⁺Region and P-type ion implanted source contact P⁺The area of the image to be displayed is,the source contact p⁺A region is arranged on the source contact n⁺Between the region and the edge of the P-well region.

Preferably, the P-well region is provided with a gate trench, and the depth of the gate trench is greater than that of the P-well region; a gate electrode layer is arranged in the gate groove, and an insulated gate dielectric layer is arranged between the inner wall of the gate groove and the gate electrode layer; the gate trench is arranged on the source contact n⁺And (4) a region.

Preferably, the source contact n⁺Upper part of the region and the source contact p⁺The upper part of the region is provided with source ohmic contact metal; and the back of the N-type substrate is provided with drain ohmic contact metal.

Preferably, a connection metal is provided on the source ohmic contact metal upper portion, the gate electrode layer upper portion, and the schottky contact upper portion.

Preferably, an isolation dielectric layer is further disposed at the gate trench opening to isolate the source ohmic contact metal and/or a connection metal on the source ohmic contact metal from a connection metal on the gate electrode layer.

The utility model separates the well regions in the field effect transistor, and selects the region between two adjacent well regions to prepare Schottky contact by growing metal on the upper part without ion injection, and the peripheral well regions and the PN junction formed by epitaxy and Schottky contact form a junction barrier Schottky diode; because the current of the traditional parasitic PIN diode is formed by the diffusion of minority carriers when the forward conduction is carried out, and the forward current of the junction formed by Schottky contact is formed by the fact that the majority carriers in a semiconductor enter metal, when the diode is applied in a conduction mode, the junction barrier Schottky diode has lower forward conduction voltage drop, so that the forward conduction of the device is easier to realize in the application of electric energy conversion such as an inverter circuit, a chopper circuit and the like, and the device has lower power loss and higher working efficiency; meanwhile, when the conducting mode of the field effect transistor adopting the junction barrier Schottky diode structure is applied to the diode, the bipolar conduction of the traditional parasitic PIN diode is changed into multi-sub conduction, so that the device has the advantages of short reverse recovery time, less reverse recovery charge, higher switching speed and the like in the application of electric energy conversion such as an inverter circuit, a chopper circuit and the like; the junction barrier Schottky diode is subjected to structural change in the device, so that the problems of high cost, large size and the like caused by the fact that the device and an external fast recovery diode are connected in an anti-parallel mode are solved, and the problem that the reliability of the device is reduced due to the fact that metal connecting wires are increased is solved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without undue limitation to the invention. In the drawings:

fig. 1 is a flow chart of a manufacturing method according to a second embodiment of the present disclosure;

fig. 2 is a schematic cross-sectional structure diagram of step one according to the second embodiment of the present disclosure;

fig. 3 is a schematic cross-sectional structure diagram of step two according to the second embodiment of the present disclosure;

fig. 4 is a schematic cross-sectional structure diagram of step three of the second embodiment of the present disclosure;

fig. 5 is a schematic cross-sectional structure diagram of step four of the second embodiment of the present disclosure;

fig. 6 is a schematic cross-sectional structure diagram of step six of the second embodiment of the present disclosure;

fig. 7 is a schematic cross-sectional structure diagram of step seven of the second embodiment of the present disclosure;

fig. 8 is a schematic cross-sectional structure diagram of step eight of the second embodiment of the present disclosure;

fig. 9 is a schematic cross-sectional structure diagram of step ten of the second embodiment of the present disclosure;

fig. 10 is a schematic cross-sectional structure diagram of step twelve of the second embodiment of the present disclosure;

fig. 11 is a schematic cross-sectional structure diagram of a fourteenth step of the second embodiment of the disclosure;

fig. 12 is a schematic cross-sectional view of a conventional trench MOS in the prior art.

A 101-SiC substrate; 102-N type epitaxy; 103-P-well region; 104-source contact n⁺An area; 105-source contact p⁺An area; 106-gate trenches; 107-insulated gate dielectric layer; 108-gate electrode layer; 109-an isolation dielectric layer; 110-source ohmic contact metal; 111-drain ohmic contact metal; 112-Schottky contact; 113-connecting metal.

Detailed Description

In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the drawings of the embodiments of the present invention are combined below to clearly and completely describe the technical solution of the embodiments of the present invention. It is to be understood that the embodiments described are only some of the embodiments of the present invention, and not all of them. All other embodiments, which can be obtained by a person skilled in the art without any inventive work based on the described embodiments of the present invention, belong to the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

In addition, in the description of the present invention, "a plurality of times" means two or more times unless specifically limited otherwise. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.

Reference in the specification to "one embodiment" or "an example" means that a particular feature, structure or characteristic described in connection with the embodiment itself may be included in at least one embodiment of the patent disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

The first embodiment is as follows:

the utility model discloses a preparation method of field effect transistor, this embodiment adopts N type substrate right the utility model discloses a method carries out the detailed description. In the embodiment, the schottky contact 112 is prepared, a junction barrier schottky diode (JBS) is formed by the PN junction formed by the P-well region 103 and the N-type epitaxy 102 and the schottky contact 112, and the junction barrier schottky diode replaces a parasitic PIN diode in a traditional circuit or replaces a Fast Recovery Diode (FRD) externally connected in anti-parallel with a device, so that the problems of high power loss, low working efficiency, high system cost and the like in the existing application can be solved.

Fig. 1 is a flow chart of the manufacturing method of this embodiment, and fig. 2 to 11 are schematic cross-sectional structures of the field effect transistors in respective links in the manufacturing flow of the manufacturing method of this embodiment.

The method comprises the following steps: the substrate adopted in this embodiment is a SiC substrate, that is, an N-type SiC substrate 101 is first provided, then an N-type SiC layer, that is, an N-type epitaxy 102 in fig. 2, is epitaxially formed on this N-type SiC substrate 101, and this semiconductor device sample wafer is cleaned by a conventional RCA cleaning process (in this embodiment, a field effect device in the form of a semi-finished product is added on the substrate). In this embodiment, a doping concentration of 1 × 10 is used¹⁸cm^-3N-type SiC substrate 101 and doping concentration of 5 × 10¹⁵cm^-3Of the N type inIn other embodiments, the doping concentration of the N-type SiC substrate 101 may be 1 × 10¹⁸cm^-3～1×10¹⁹cm^-3The doping concentration of the N-type epitaxy 102 may be in the range of 1 × 10¹⁴cm^-3～1×10¹⁶cm^-3The range can be determined according to the process requirements of the SiC device to be designed; in addition, the cleaning process in this step is not limited to the RCA cleaning process, and in other embodiments, a cleaning process may be selected that can remove surface contaminants of the semiconductor device sample wafer (in this embodiment, a field effect device in which an epitaxial form is a semi-finished product is added on the substrate) and provide the N-type SiC substrate 101 and the N-type epitaxial layer 102 meeting the process standard for the subsequent processing process. The RCA cleaning process is a standard semiconductor cleaning process in the prior art. After completing the RCA cleaning process, the semiconductor device sample wafer (in this embodiment, a field effect transistor device in which an epitaxial layer is added on the substrate and the form of a semi-finished product is used) after cleaning is immersed in a hydrofluoric acid solution with a concentration of 2% for 3 minutes at a normal temperature, i.e., at a temperature in a normal manufacturing shop, which is about 17 to 19 ℃ in winter and about 22 to 25 ℃ in summer, where SiO is dissolved by hydrofluoric acid₂Removes the oxide layer on the surface of the N-type SiC substrate 101 and the N-type epitaxy 102. Finally, N with a purity of 99.99% was used₂And blowing residual liquid on the surfaces of the N-type SiC substrate 101 and the N-type epitaxy 102 by air flow to dry the surfaces of the N-type SiC substrate 101 and the N-type epitaxy 102.

Step two: p-type ion implantation is performed on the surface of the N-type epitaxy 102 to form a separated two-part P-well region 103 in fig. 3. Depositing a layer of Al with the thickness of 1.5 mu m on the front surface of the N-type epitaxy 102 by a low-pressure hot-wall chemical vapor deposition (LPCVD) method to be used as a barrier layer for ion implantation of the P-well region 103, and photoetching the layer of Al on the front surface of the N-type epitaxy 102 to etch away the Al on the upper surface of the P-well region 103, namely exposing the surface of the semiconductor epitaxy for ion implantation, thereby forming a P-well implantation region; multiple Al ions are implanted into the P-well implantation region on the N-type epitaxy layer 102 at 650 deg.C to form a depth of0.6 μm and a doping concentration of 3X 10¹⁸cm^-3P-well region 103; finally, phosphoric acid is used to remove Al on the front surface of the N-type epitaxy 102, the semiconductor device sample wafer (the field effect transistor device in the form of a semi-finished product from the second step in the embodiment) is cleaned by the existing standard cleaning process, and finally N with the purity of 99.99 percent is used₂And blowing the residual liquid on the surface of the semiconductor device sample wafer by air flow so as to keep the surface of the semiconductor device sample wafer dry.

In the present embodiment, Al ions are selected for implantation, and in other embodiments, other P-type ions, such as ions corresponding to boron (B), gallium (Ga), etc., may be selected according to process requirements and equipment conditions. In other embodiments, the function of the barrier layer can be realized by directly selecting a photoresist capable of blocking ion implantation, and the photoresist only needs to protect the N-type epitaxy except for the P-well implantation region when the ion implantation process is performed, so that the ion beam cannot penetrate through the photoresist.

Step three: a source region n is arranged on the upper surface of the P-well region 103⁺Contact ion implantation (N-type ion) to form the source contact N in fig. 4⁺ Region 104, which is specifically operated by depositing a layer of Al as source contact N of 1 μm thickness on the front surface of N-type epitaxy 102 by low pressure hot wall chemical vapor deposition (LPCVD)⁺Blocking layer of ion implantation in region 104, and photoetching Al on the front surface of the N-type epitaxy layer 102 to etch away the source contact N⁺Al of the upper surface of the region 104, i.e., the semiconductor epitaxial surface exposed for ion implantation, thereby forming a source contact n⁺An implantation region; the source contact N on this N-type epitaxy 102 is contacted at a temperature of 500 DEG C⁺Multiple nitrogen ion implantation is performed in the implantation region to make the source contact n⁺The depth of the implantation region is 0.3 μm, and the doping concentration is 1 × 10¹⁹cm^-3Source contact n of⁺ A region 104; finally, phosphoric acid is used to remove Al on the front surface of the N-type epitaxy 102, and the semiconductor device sample wafer is cleaned by the existing standard cleaning process (the shape from the third step in the embodiment is a semi-finished product)Field effect transistor device) and finally N of 99.99% purity is used₂And blowing the residual liquid on the surface of the semiconductor device sample wafer by air flow so as to keep the surface of the semiconductor device sample wafer dry.

In the present embodiment, nitrogen ions are selected for implantation, and in other embodiments, other N-type ions, such As ions corresponding to elements such As phosphorus (P) and arsenic (As), may be selected according to process requirements and equipment conditions. In other embodiments, the barrier layer can be implemented by directly selecting a photoresist capable of blocking ion implantation, and the photoresist can satisfy the requirement of removing the source contact n during the ion implantation process⁺The N-type epitaxy outside the implanted region is protected from the ion beam penetrating the photoresist.

Step four: a source region P is arranged on the upper surface of the P-well region 103⁺Contact ion implantation (P-type ion) to form the source contact P in FIG. 5⁺ Region 105, the source contact p⁺Region 105 is disposed at the edge of P-well 103 and contacts the source n⁺Between the regions 104, i.e. the source contact p⁺One side of the region 105 coincides with the P-well region 103 and the other side with the source contact n⁺The regions 104 are partially overlapped, the width of the overlapped region is 0.2 μm, and the specific operation process of this step is as follows, firstly, a layer of Al with the thickness of 1.5 μm is deposited on the front surface of the N-type epitaxy 102 as the source contact p by low pressure hot wall chemical vapor deposition (LPCVD)⁺The barrier layer is ion-implanted in the region 105, and Al on the front surface of the N-type epitaxy layer 102 is etched to remove the source contact P⁺Al of the upper surface of the region 105, i.e., the semiconductor epitaxial surface exposed for ion implantation, thereby forming a source contact p⁺An implantation region; the source contact p on this N-type epitaxy 102 is contacted at a temperature of 650 DEG C⁺Multiple Al ion implantations are performed in the implantation region to make the source contact p⁺The depth of the implantation region is 0.3 μm, and the doping concentration is 1 × 10¹⁹cm^-3Source contact p of⁺ A region 105; finally, phosphoric acid is adopted to remove Al on the front surface of the N-type epitaxy 102, and the existing standard cleaning process is adopted to clean the semiconductor device sample wafer(the field effect transistor device was a semi-finished device in the form up to the fourth step in this example), and finally N was used with a purity of 99.99%₂And blowing the residual liquid on the surface of the semiconductor device sample wafer by air flow so as to keep the surface of the semiconductor device sample wafer dry.

Step five: and carrying out high-temperature activation on the impurity ions implanted in the previous steps. Specifically, the surface of a semiconductor device sample wafer (the field effect transistor device in the form of a semi-finished product which has been cleaned and dried up to the fourth step in this embodiment) is cleaned by a standard RCA cleaning process, a carbon film is formed after baking to protect the device, and then annealing is performed at 1700 ℃ for 10 minutes in an argon atmosphere to perform ion activation. After the annealing operation is completed, the carbon film is removed by using the prior art, that is, the carbon film is removed by using oxygen plasma, and the surface of the semiconductor device sample wafer (the field effect transistor device in the form of the semi-finished product up to the fifth step in the embodiment) is cleaned and dried by using the RCA cleaning standard again. In this embodiment, the drying is performed by using N with a purity of 99.99%₂The residual liquid on the surface of the semiconductor device sample wafer is blown dry by the air flow to keep the surface of the semiconductor device sample wafer dry, in other embodiments, other existing technologies can be adopted to achieve the purpose of drying the surface of the semiconductor device sample wafer, and the invention is not limited to the existing technologies adopted in the embodiment.

Step six: at the source contact n⁺The central portion of the region 104 is etched toward the portion of the N-type epitaxy 102 to form a gate trench 106 deeper than the P-well 103. Is specifically operated by first depositing on the top surface of the N-type epitaxy 102A layer of photoresist is selectively etched at the photoresist to form a gate trench window, such that the source contact n + region 104 at the gate trench window is partially exposed and the gate trench opening is located at the center of the source contact n + region 104. The gate trench 106 in fig. 6 is formed by etching the N-type epitaxy 102 by using an inductively coupled plasma etching (ICP), wherein the etching pressure is 0.3Pa to 0.5Pa, the temperature is normal temperature, the source power is 700W to 800W and the bias (RF) power is 100W to 200W during the application of the ICP, wherein the etching gas comprises SF₆(Sulfur hexafluoride), O₂(oxygen) and Ar (argon), SF₆Gas flow ratio of Ar to Ar of 2:1, O₂The content variation range of (A) is 45-50%, and the etching depth is 0.8 μm. In other embodiments, the deposition thickness of the photoresist is determined according to the underlying material of different products and the thickness to be etched, and is not limited to the deposition thickness of this embodiment.

Step seven: performing surface treatment on the SiC substrate 101, the N-type epitaxy 102 and the gate trench 106, and performing deposition, photoetching and etching on the surfaces of the N-type epitaxy 102 and the gate trench 106 to form an insulated gate dielectric layer and a gate electrode layer, namely firstly preparing the insulated gate dielectric layer on the inner surface of the gate trench 106 and then preparing the gate electrode layer 108 in the gate trench, wherein the insulated gate dielectric layer 107 is arranged between the inner wall of the gate trench 106 and the gate electrode layer 108, and the specific operation process is that firstly performing dry oxygen oxidation treatment on the upper surface of the N-type epitaxy 102 and the surface of the gate trench 106 to form a material with the thickness of 50nm on the surface of the gate trench 106, namely SiO₂And a gate electrode layer 108 is deposited on the insulated gate dielectric layer 107. The deposited gate electrode layer 108 is made of polysilicon, and the gate electrode layer 108 is deposited by LPCVD, i.e. a polysilicon gate with a thickness of 800nm is deposited by LPCVD at a temperature of 600 ℃ and a deposition pressure of 60Pa, using silane and phosphine as reaction gases and helium as a carrier gas. In this step, the dry oxygen oxidation process and the LPCVD technique are both conventional semiconductor processing processes and techniques. After completing the insulated gate dielectric layer 107 andafter the gate electrode layer 108 is prepared, the material of the surface of the N-type epitaxy layer 102 is SiO₂The redundant insulated gate dielectric layer 107 and the gate electrode layer 108 are etched and etched, and only SiO in the gate trench 106 shown in FIG. 7 is remained₂An insulated gate dielectric layer 107 and a polysilicon gate electrode layer 108. In other embodiments, the thickness of the insulating gate dielectric layer 107 and the gate electrode layer 108 is not limited to or precise with the data in this embodiment, and may be determined according to the specific process requirements and the conditions of the plant equipment of the semiconductor device to be designed.

Step eight: depositing an isolation dielectric layer 109 shown in fig. 8 on the upper surface of the N-type epitaxy 102, and performing photolithography and etching to leave only the isolation dielectric layer 109 at the position of the insulated gate dielectric layer 107 at the opening of the gate trench 106, i.e., the isolation dielectric layer 109 at the exposed opening of the insulated gate dielectric layer 107, and finally isolating the source ohmic contact metal 110 from the connection metal 113 on the upper portion of the gate electrode layer 108 through the isolation dielectric layer 109, and isolating the connection metal 113 on the upper portion of the source ohmic contact metal 110 from the connection metal 113 on the upper portion of the gate electrode layer 108 through the isolation dielectric layer 109. Here, the connection metal 113 is respectively disposed on the upper surface of the source ohmic contact metal 110, the upper surface of the gate electrode layer 108, and the upper surface of the schottky contact metal 112, and the preparation method thereof is given in the fourteenth step. The isolation dielectric layer 109 of this embodiment is a silicon oxide oxidized by wet oxygen and has a thickness of 800 nm. In other embodiments, the thickness of the isolation dielectric layer 109 may be determined according to the process requirements of the semiconductor device to be designed, and is not limited to the data in the embodiment.

Step nine: a layer of 500 nm-600 nm metal Ni is deposited by sputtering through a lift-off process, and the metal Ni is selectively etched, i.e., the metal Ni except for the position for preparing the source ohmic contact metal 110 is etched, and finally the source ohmic contact metal 110 in the figure 9 is prepared. The thickness of the metal Ni grown here is not limited to the specific thickness of this embodiment in other embodiments, and the process can be adjusted according to different process requirements of different products and different functions of whether the metal Ni is used as a test or a source/drain contact in the products. The lift-off process is prior art, so that the growth of the metal Ni here can also use other prior art processes in other embodiments, such as PVD (physical vapor deposition) process, and the like, and is not limited to the process used in this embodiment.

Step ten: and a layer of metal Ni with the thickness of 500 nm-600 nm is sputtered and deposited on the back of the SiC substrate 101 by adopting a lift-off process to serve as back drain ohmic contact metal 111. As in step nine, the selection of the existing processes and techniques is not limited to the technique employed in the present embodiment.

Step eleven: the source ohmic contact metal 110 and the drain ohmic contact metal 111 are alloyed at a high temperature. In this step, the operation was specifically as follows, N at a concentration of 99.99%₂Under protection, a Rapid Thermal Annealing (RTA) mode is adopted, so that the source ohmic contact metal 110 and the drain ohmic contact metal 111 are subjected to rapid thermal treatment for 5 minutes at 980 ℃, and the purpose of good ohmic contact is finally achieved.

Step twelve: a schottky contact 112 is formed on the upper portion of the central portion region between the adjacent two P-well regions 103. In this step, a layer of metal nickel (Ni) of 200nm to 600nm is sputter deposited as the Schottky contact metal 112 by lift-off process, i.e., at N₂Under protection, forming Schottky contact by rapid heat treatment at 850 deg.C, wherein N is₂The treatment time under protection was 5 minutes.

Step thirteen: and performing deposition, photoetching and etching on the passivation layer on the surface of the device by adopting a BPSG (binary phase shift keying) process, and performing high-temperature reflux.

Fourteen steps: and preparing the connecting metal. In this step, a layer of metal Al with a thickness of 2 μm to 64 μm is deposited on the upper surface of the semiconductor device sample wafer (the field effect device in the form of a semi-finished product up to the thirteenth step in this embodiment) as the connection metal 113, and the photolithography and etching operations are performed to leave only the connection metal 113 on the upper surface of the source ohmic contact metal 110, the upper surface of the gate electrode layer 108, and the upper surface of the schottky contact metal 112, wherein the connection metal 113 on the upper surface of the gate electrode layer 108 occupies the entire upper surface of the gate electrode layer 108 and the upper surface of the isolation dielectric layer 109, so that the connection metal 113 on the upper surface of the source ohmic contact metal 110 does not contact the connection metal 113 on the upper surface of the gate electrode layer 108, and the connection metal 113 on the upper surface of the schottky contact metal 112 does not contact the connection metal 113 on. The connecting metal 113 is made of Al, Pt, Au, TiN, TiNiAg, etc. In the fourteenth embodiment, the process for depositing the connecting metal 113 is a lift-off sputtering deposition process, which is a conventional process, and other conventional processes, such as evaporation deposition and PVD (physical vapor deposition) processes, may also be used in other embodiments; the deposition thickness of the connecting metal 113 can be determined according to the workshop of semiconductor device design, cost conditions and specific process requirements, for example, the connecting metal 113 with different thickness is required to be selected for low current products and high current products due to the difference of wire bonding thickness.

In the present embodiment, on the upper surface of the N-type epitaxy layer 102 and at the source contact p⁺Away from the source contact n on the upper surface of region 105⁺At one end of the region, the same metal used to make the schottky contact 112 is also grown together with the schottky contact 112 to better enhance the ohmic contact characteristics of the source. In other embodiments, the metal in this portion may not be grown separately, but only the source ohmic contact metal is grown in the process of preparing the source ohmic contact metal 110.

Example two:

the utility model discloses still disclose a device embodiment of field effect transistor, prepare by the preparation method in embodiment one. In the present embodiment, the disclosed field effect transistor includes a SiC substrate 101, and an N-type epitaxy 102 provided on the upper portion of the SiC substrate 101. The P-well 103 formed by P-type ion implantation is disposed on the N-type epitaxy 102, the conventional fet has only one P-well, and in this embodiment, the P-well 103 is divided into two parts, a schottky contact 112 is disposed on the upper part of the central part between two adjacent P-well 103, wherein the schottky contact 112 is formed by growing a layer of 200 nm-600 nm metal nickel (Ni) to contact with the N-type epitaxy 102 of the semiconductor material SiC, and the P-well 103 and the N-type epitaxy 102 around the schottky contact 112 form a PN junctionThis PN junction and schottky contact 112 together form a junction barrier schottky diode. In addition to the schottky contact 112, the P-well 103 of the fet disclosed in this embodiment is further provided with a source contact N formed by N-type ion implantation⁺Region 104 and source contact P formed by P-type ion implantation⁺And a region 105. Source contact n here⁺The region 104 is disposed in the center of the P-well 103 and does not contact the edges of the P-well 103 except the upper surface, and the source contact P⁺The region 105 is provided in the source contact n⁺Between the region 104 and the edge of the P-well region 103, i.e. the source contact P⁺One side of the region 105 coincides with the P-well region 103 and the other side with the source contact n⁺The regions 104 partially overlap, the width of the overlapping region being 0.2 μm. A gate trench 106 is further formed in the P-well region, the gate trench 106 being formed in the source contact n⁺The central portion of the region 104 extends toward the N-epi 102 until the bottom of the gate trench 106 exposes the top surface of the N-epi 102. An insulating dielectric layer 107 and a gate electrode layer 108 are sequentially arranged on the surface of the gate trench 106 from the surface close to the gate trench 106 to the surface far away from the gate trench 106, and an isolation dielectric layer 109 is further arranged outside the gate trench 106, wherein the isolation dielectric layer 109 enables the source ohmic contact metal 110 and/or the connection metal 113 on the upper portion of the source ohmic contact metal 110 to be isolated from the connection metal 113 on the upper portion of the gate electrode layer 108 through the isolation dielectric layer 109. In addition, at the source contact n⁺Region 104 and source contact p⁺A source ohmic contact metal 110 for ohmic contact is provided on an upper portion of the region 105, and a drain ohmic contact metal 111 is provided on a back portion of the SiC substrate 101, i.e., on the other side opposite to the source ohmic contact 110. A connection metal is provided on the upper portion of the source ohmic contact metal 110, the upper portion of the gate electrode layer 108, and the upper portion of the schottky contact 112 for conductive connection in a subsequent process.

Compare traditional slot MOS pipe in figure 12, because SiC's PN junction switches on the pressure drop and is about 3V, the inside traditional parasitic PIN diode of device has great conduction pressure drop, and the schottky contact has one-way conductivity with the PN junction the same, and the junction capacitance is less, make the reverse saturation current of junction barrier schottky diode compare in the reverse saturation current of PN junction big many, the event adopts this junction barrier schottky diode to replace traditional parasitic PIN diode, can effectively reduce forward conduction pressure drop, make the device change in the application and realize forward and switch on more easily in inverter circuit, chopper circuit etc. In addition, when the traditional parasitic PIN diode is conducted in the forward direction, current is formed by diffusion of minority carriers, and the forward current of a junction formed by Schottky contact is formed by the fact that the majority carriers in a semiconductor enter a metal, so that for a field effect transistor, when the diode is applied in a conduction mode, bipolar conduction (conductance modulation) of the traditional parasitic PIN diode is converted into multi-sub conduction of a junction barrier Schottky diode, and the device has the characteristics of short reverse recovery time and less reverse recovery charge and has higher switching speed in circuit conversion application such as an inverter circuit and a chopper circuit; and carriers in the schottky contact do not accumulate when crossing the interface, but directly flow as a drift current, and therefore, the schottky contact also has better high-frequency characteristics. Compared with an application mode that a Fast Recovery Diode (FRD) is connected in anti-parallel outside a field effect transistor device, the application mode that a diode is directly integrated inside reduces the number of devices and the number of connecting wires among the devices, and has the advantages of low production cost, high device reliability, small system size and the like.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

In short, the above description is only a preferred embodiment of the present invention, and all the equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the scope of the present invention.

Claims

1. A field effect transistor comprises an N-type substrate and an N-type epitaxy arranged on the N-type substrate, and is characterized in that: the Schottky barrier Schottky diode is characterized in that a P-well region formed by P-type ion injection is arranged on the N-type epitaxy, a PN junction is formed at the interface of the P-well region and the N-type epitaxy, a Schottky contact is arranged on the N-type epitaxy between two adjacent P-well regions, and the Schottky and the PN junction form a junction barrier Schottky diode together.

2. The fet of claim 1, wherein:

the P-well region is provided with an N-type ion implanted source electrode contact N⁺Region and P-type ion implanted source contact P⁺Region of the source contact p⁺A region is arranged on the source contact n⁺Between the region and the edge of the P-well region.

3. The fet of claim 2, wherein:

the P-well region is provided with a grid groove, and the depth of the grid groove is greater than that of the P-well region;

a gate electrode layer is arranged in the gate groove, and an insulated gate dielectric layer is arranged between the inner wall of the gate groove and the gate electrode layer;

the gate trench is arranged on the source contact n⁺And (4) a region.

4. The fet of claim 3, wherein:

the source contact n⁺Upper part of the region and the source contact p⁺The upper part of the region is provided with source ohmic contact metal; and the back of the N-type substrate is provided with drain ohmic contact metal.

5. The FET of claim 4, wherein:

and connecting metals are arranged on the upper part of the source ohmic contact metal, the upper part of the gate electrode layer and the upper part of the Schottky contact.

6. The fet of claim 5, wherein:

and an isolation dielectric layer is further arranged at the opening of the grid groove and used for isolating the source ohmic contact metal and/or the connecting metal on the upper part of the source ohmic contact metal from the connecting metal on the upper part of the grid electrode layer.