CN117690971A

CN117690971A - Silicon carbide power device and manufacturing method thereof

Info

Publication number: CN117690971A
Application number: CN202410153477.7A
Authority: CN
Inventors: 乔凯
Original assignee: Shenzhen Sirius Semiconductor Co ltd
Current assignee: Shenzhen Sirius Semiconductor Co ltd
Priority date: 2024-02-04
Filing date: 2024-02-04
Publication date: 2024-03-12

Abstract

The application discloses a silicon carbide power device and a manufacturing method thereof. The device includes: an N-type substrate; the epitaxial layer is arranged on the N-type substrate, a P-type channel region is formed in the epitaxial layer, an N+ type source region is formed in the P-type channel region, a grid groove penetrates through the P-type channel region and the N+ type source region, a P+ type suspension region is arranged below the grid groove, and a P region is arranged between the P+ type suspension region and the P-type channel region; a gate filled in the gate trench; the source electrode is arranged on the epitaxial layer and covers the P-type channel region, the N+ type source region and the grid electrode; the P-type polycrystalline silicon is arranged on the groove wall of the grid groove, is arranged in a semi-surrounding mode around the grid, is contacted with the epitaxial layer at the bottom of the grid groove and is contacted with the source electrode; and the drain electrode is arranged on one side of the N-type substrate, which is away from the epitaxial layer. The device structure realizes reverse follow current with low cost and low space occupation of the corresponding device, improves the conducting speed and switching frequency of the device, and reduces the follow current starting voltage and loss.

Description

Silicon carbide power device and manufacturing method thereof

Technical Field

The application relates to the technical field of semiconductor devices, in particular to a silicon carbide power device and a manufacturing method thereof.

Background

Under the background that the performance of the traditional silicon (Si) base power device is difficult to obtain great optimization, the silicon carbide (SiC) material lays the advantages of the silicon carbide power device manufactured by using the SiC material as a bulk material in the application fields of high temperature, high voltage, high speed, strong radiation and the like due to the excellent electrical properties such as wide forbidden bandwidth, high critical breakdown voltage, high thermal conductivity, high saturated electron drift speed and the like.

Among them, silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices have become research hot spots in the current silicon carbide power device field by virtue of their characteristics of fast switching speed, low switching loss, small on-resistance, wide operating temperature range, etc. Among the numerous silicon carbide MOSFET device structures, the grounded junction MOSFET device has been one of the mainstream structures of silicon carbide MOSFET designs by introducing a grounded junction into the device, exhibiting advantages of high current density, low on-resistance, and high reliability, as compared to conventional vertical MOSFET devices.

However, the actual application circuit of the silicon carbide MOSFET device often has an inductance element, which can form a larger reverse current impact, and the freewheel turn-on voltage of the silicon carbide MOSFET device is far higher than that of the silicon-based MOSFET device, and the occurrence of these situations increases the requirement of the device on the freewheel turn-on voltage. The existing methods have the following functions through anti-parallel diodes or body diodes and solve the problems through reverse follow currents through split gate structures, however, the methods can cause the problems of increased chip area, increased process complexity, reduced current density and the like, the process cost is increased, and the reliability and the stability of the device are reduced.

Disclosure of Invention

The application mainly provides a silicon carbide power device and a manufacturing method thereof, and aims to solve the technical problems that the follow current starting voltage of the silicon carbide power device is too high and is difficult to start.

In order to solve the technical problems, the technical scheme adopted by the application is as follows: a silicon carbide power device is provided. The silicon carbide power device includes: an N-type substrate; the epitaxial layer is arranged on the N-type substrate, a P-type channel region is formed in the epitaxial layer, an N+ type source region is formed in the P-type channel region, a grid groove penetrates through the P-type channel region and the N+ type source region, a P+ type suspension region is arranged below the grid groove, and a P region is arranged between the P+ type suspension region and the P-type channel region; a gate filled in the gate trench; the source electrode is arranged on the epitaxial layer and covers the P-type channel region, the N+ type source region and the grid electrode; the P-type polycrystalline silicon is arranged on the groove wall of the grid groove and is arranged in a semi-surrounding mode around the grid, is contacted with the epitaxial layer at the bottom of the grid groove and is contacted with the source electrode; and the drain electrode is arranged on one side of the N-type substrate, which is away from the epitaxial layer.

In some embodiments, the P-type polysilicon has a width of 0.1 to 0.4 μm.

In some embodiments, the P-type polysilicon has a doping concentration of 1×10 ¹⁹ cm ^-3 The above.

In some embodiments, the epitaxial layer includes an N-type drift region, the P-type polysilicon is in stacked contact with the N-type drift region, and the doping concentration of the N-type drift region is not more than 1×10 ¹⁷ cm ^-3 。

In some embodiments, the epitaxial layer comprises an N-type drift region and a charge storage layer which are sequentially stacked on the N-type substrate, the P-type polysilicon is in stacked contact with the charge storage layer, and the P-type channel region, the n+ type source region, the gate trench and the P region are all located in the charge storage layer.

In some embodiments, the charge storage layer has a doping concentration of no more than 1×10 ¹⁷ cm ^-3 。

In some embodiments, the p+ -type floating region extends to a side close to the gate trench to a position directly below a side of the P-type polysilicon away from the floating region.

In order to solve the technical problems, another technical scheme adopted by the application is as follows: a method for manufacturing a silicon carbide power device. The manufacturing method of the silicon carbide power device comprises the following steps: providing an N-type substrate; forming an epitaxial layer on the N-type substrate, and performing ion implantation on the epitaxial layer to form a P-type channel region in the epitaxial layer, forming an N+ type source region in the P-type channel region, forming a p+ type suspended region below the gate trench, and forming a P region arranged between the p+ type suspended region and the P-type channel region; etching the epitaxial layer to form a gate trench passing through the P-type channel region and the n+ type source region; depositing a thick oxide layer in the grid electrode groove and etching to form a window; forming P-type polycrystalline silicon on the window, and etching to remove the thick oxide layer on the side wall of the grid electrode groove; performing thermal oxidation on the epitaxial layer and the thick oxide layer to form a thermal oxide layer which wraps the P-type polycrystalline silicon and covers the epitaxial layer, and depositing grid polycrystalline silicon on the thermal oxide layer; etching the grid polysilicon and performing field oxide deposition to form the grid and a grid oxide layer wrapping the grid; and depositing a source electrode to cover the N+ type source region and the gate oxide layer, and depositing a drain electrode on one side of the N type substrate, which is away from the epitaxial layer.

The beneficial effects of this application are: unlike the prior art, the application discloses a silicon carbide power device and a manufacturing method thereof. Through setting up with the grid adjacent setting and with epitaxial layer range upon range of P type polycrystalline silicon that contacts in carborundum power device to can obtain the freewheel passageway, so that the device can open under lower reverse voltage, and have better breakdown voltage and on resistance compromise effect, realize reverse freewheel, simultaneously, the cost and the technology degree of difficulty of this mode are relatively lower, under the circumstances that do not exert an influence to chip area and forward conduction characteristic, can effectively promote the conduction speed and the switching frequency of device, reduce switching loss, promote switching performance.

Drawings

For a clearer description of embodiments of the present application or of the solutions of the prior art, the drawings that are required to be used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the present application, and that other drawings may be obtained, without inventive effort, by a person skilled in the art from these drawings, in which:

FIG. 1 is a schematic diagram of an embodiment of a silicon carbide power device provided herein;

FIG. 2 is a heterojunction energy band diagram of N-type polysilicon (N-POLY) in contact with N-type silicon carbide (N-SiC) material;

FIG. 3 is a heterojunction energy band diagram of P-type polysilicon (P-POLY) in contact with N-type silicon carbide material (N-SiC);

FIG. 4 is a schematic diagram of breakdown voltage characteristics of a conventional planar gate (CONV) MOSFET, a P-type polysilicon (P-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET, and a TCAD simulation of an N-type polysilicon (N-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET;

FIG. 5 is a schematic diagram of on-resistance characteristics of a conventional planar gate (CONV) MOSFET, a P-type polysilicon (P-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET, and a TCAD simulation of an N-type polysilicon (N-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET;

FIG. 6 is a schematic diagram of the freewheel turn-on voltage characteristics of a conventional planar gate (CONV) MOSFET, a P-type polysilicon (P-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET, and a TCAD simulation of an N-type polysilicon (N-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET;

FIG. 7 is a schematic diagram of the current density distribution of a conventional planar gate (CONV) MOSFET, a P-type polysilicon (P-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET, and an N-type polysilicon (N-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET breakdown;

FIG. 8 is a schematic diagram of potential distribution of a conventional planar gate (CONV) MOSFET, a P-type polysilicon (P-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET, and an N-type polysilicon (N-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET breakdown;

FIG. 9 is a schematic diagram of another embodiment of a silicon carbide power device provided in FIG. 1;

FIG. 10 is a heterojunction energy band diagram of P-type polysilicon (P-POLY) in contact with N-type charge storage layer silicon carbide material (N-SiC);

FIG. 11 is a schematic flow chart of a method for fabricating a silicon carbide power device according to the present disclosure;

fig. 12 is a schematic flow chart showing the steps of a method for manufacturing the silicon carbide power device shown in fig. 11.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The terms "first," "second," "third," and the like in the embodiments of the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic flow chart of an embodiment of a silicon carbide power device provided in the present application. The silicon carbide power device 100 includes: an N-type substrate 10; an epitaxial layer 20 disposed on the N-type substrate 10, a P-type channel region 21 formed in the epitaxial layer 20, an n+ type source region 22 formed in the P-type channel region 21, a gate trench 30 passing through the P-type channel region 21 and the n+ type source region 22, a p+ type floating region 41 located under the gate trench 30, and a P region disposed between the p+ type floating region 41 and the P-type channel region 21; a gate electrode 31 filled in the gate trench 30; a source 50 disposed on the epitaxial layer 20 and covering the P-type channel region 21, the n+ type source region 22 and the gate 31; the P-type polysilicon 32 is arranged on the wall of the gate trench 30 and is arranged around the gate 31 in a semi-circular manner, is in contact with the epitaxial layer 20 at the bottom of the gate trench 30 and is in contact with the source 50; and a drain electrode 60 disposed on a side of the N-type substrate 10 facing away from the epitaxial layer 20.

The silicon carbide power device is a vertical conductive U-shaped trench-gate MOSFET (UMOS) device, and a grounding junction is introduced into a source region of the silicon carbide power device to form a grounding junction MOSFET device structure. The source 50 is grounded or low-level, the drain 60 is connected with high-level, forward conduction is realized when the voltage of the gate 31 is higher than a certain threshold voltage, the P-type channel region 21 is opened, the P-type polysilicon 32 and the epitaxial layer 20 are depleted and cut off, and electrons in the device sequentially pass through the N+ type source region 22, the P-type channel region 21, the epitaxial layer 20 and the N-type substrate 10 from the source 50 to enter the drain 60; and when the device is conducted reversely, the grid electrode 31 and the drain electrode 60 are grounded or low-level, the source electrode 50 is connected with high-level, the P-type channel is closed, the conduction and continuous flow of the P-type polysilicon 32 and the epitaxial layer 20 are realized reversely, and electrons in the device sequentially pass through the N-type substrate 10, the epitaxial layer 20 and the P-type polysilicon 32 from the drain electrode 60 to enter the source electrode 50.

Among them, polysilicon (Poly) is a form of silicon crystal composed of many small crystals or grains, and when doped with acceptor impurities such as boron, aluminum, gallium and the like, it is mainly hole-conductive to form the P-type polysilicon (P-Poly), and when doped with donor impurities such as phosphorus, nitrogen, arsenic and the like, it is mainly electron-conductive to form the N-type polysilicon (N-Poly). The P-type polysilicon or the N-type polysilicon can be contacted with the N-type doped silicon carbide material through the structure to form a heterojunction structure.

In the silicon carbide power device 100 provided by the present invention, referring to fig. 2 and 3, fig. 2 is a heterojunction energy band diagram of N-type polysilicon (N-POLY) in contact with N-type silicon carbide (N-SiC) material, and fig. 3 is a heterojunction energy band diagram of P-type polysilicon (P-POLY) in contact with N-type silicon carbide material (N-SiC). In order to play a role of freewheel, the energy Δe-reverse required for reverse conduction of the heterojunction should be ensured to be small enough to ensure that the heterojunction can be turned on under a lower reverse voltage, while as can be seen from fig. 2 and 3 of the energy band, the energy required for reverse conduction of the heterojunction structure formed by the N-type polysilicon and the silicon carbide material is lower than the energy required for reverse conduction of the heterojunction structure formed by the P-type polysilicon and the silicon carbide material, so that the heterojunction structure formed by the N-type polysilicon and the silicon carbide material has better freewheel capability, but in practice, when the device is turned on, the breakdown voltage characteristics simulated by TCAD (Technology Computer Aided Design) of the conventional planar gate (CONV) MOSFET, the P-type polysilicon (P-POLY) and the N-type silicon carbide (N-SiC) heterojunction MOSFET and the N-type polysilicon (N-SiC) are almost bad in practical breakdown voltage, compared with the conventional planar gate MOSFET and the P-type MOSFET, so that the breakdown voltage is hardly bad in practice.

Meanwhile, according to the on-resistance characteristic diagram of the conventional planar gate (CONV) MOSFET, the P-type polycrystalline silicon (P-POLY) and the N-type silicon carbide (N-SiC) heterojunction MOSFET and the on-voltage characteristic diagram of the N-type polycrystalline silicon (N-POLY) and the N-type silicon carbide (N-SiC) heterojunction MOSFET shown in fig. 5, and the counter-current effect of the conventional planar gate (CONV) MOSFET, the P-type polycrystalline silicon (P-POLY) and the N-type silicon carbide (N-SiC) heterojunction MOSFET and the N-type polycrystalline silicon (N-POLY) and the N-type silicon carbide (N-SiC) heterojunction MOSFET shown in fig. 6, it is known that the effect of using the P-type polycrystalline silicon on the breakdown voltage is small and the on-voltage of the freewheel channel is about 1.5-1.8V, the on-voltage is about 30% lower than that of the conventional planar gate MOSFET body diode 2.4-2.8V, the counter-current effect can be achieved, and the on-current and the on-voltage and the switching speed and the on-voltage loss can be effectively increased by laminating the P-type polycrystalline silicon and the epitaxial layer 20. As can be seen from the current density distribution diagrams of these three structures at breakdown shown in fig. 7 and the potential distribution diagrams of these three structures at breakdown shown in fig. 8, the MOSFET structure using P-type polysilicon is as typical as a conventional planar gate structure in Junction breakdown, that is, breakdown occurs at the PN Junction formed by the n+ type source region 22 and the P-type channel region 21, while N-type polysilicon breaks down at the heterojunction in the JFET (Junction Field-Effect Transistor) region, that is, the middle region of the two-sided P-type channel region 21, and the current density inside the breakdown is three orders of magnitude higher than that of the other two structures, and at the same time, the potential distribution of the three cases also shows that the MOSFET structure using N-type polysilicon is denser in potential line, that is, its peak electric Field is higher and its withstand voltage capability is weaker. Thus, as can be seen from the comparison of fig. 2 to 8, the MOSFET device using the P-type polysilicon structure has better performance advantages compared to the MOSFET device using the N-type polysilicon structure and the conventional planar gate structure, and the corresponding silicon carbide power device has better reliability and stability.

In addition, the cost and space resources occupied by the structure are also less. When the P-type polysilicon 32 is not used, the gate 31 is a whole, the current is mainly controlled to be conducted through the gate 31 when the P-type polysilicon 32 is conducted in the forward direction or the reverse direction, and under the trench gate structure, the partial areas under the P-type channel region 21 and the N+ type source region 22 are not practically conducted or only conducted a small amount of current, so that the part is made into a freewheeling channel, reverse freewheeling can be realized under the condition of no influence or little influence on a device, and the introduction of the P-type polysilicon 32 structure is more universal in technology and materials, occupies less resources on chip space and is convenient to be integrated into corresponding devices, thereby being beneficial to saving cost and reducing loss.

Alternatively, the P-type polysilicon 32 has a width of 0.1 to 0.4 μm.

Specifically, the P-type polysilicon 32 may have a width of 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, or the like. Under the condition that the width of the P-type polysilicon 32 is smaller than 0.1 μm, the P-type polysilicon 32 cannot well load reverse current, the capability of reverse freewheeling is weak, if the width of the P-type polysilicon 32 exceeds 0.4 μm, the area of the gate 31 is excessively occupied, the gate 31 cannot well control the P-type channel region 21, the capability of controlling current is lost, and when the drain-source voltage is large, the current may directly enter the epitaxial layer 20 through the P-type polysilicon 32, thereby greatly affecting the performance of a device, and the excessively wide P-type polysilicon 32 also causes the increase of the chip area and the increase of the cost. Therefore, as a preferred embodiment, the width of the P-type polysilicon 32 may be set to be between 0.1 and 0.4 μm, so as to prevent or reduce interference to the control effect of the gate electrode 31 while ensuring the reverse freewheeling function, thereby ensuring the reliability and stability of the device. The width of the P-type polysilicon 32 may be adaptively adjusted according to the process or the overall ratio, as long as the reverse freewheeling is effectively performed without affecting the control of the gate electrode 31.

Optionally, the doping concentration of the P-type polysilicon 32 is 1×10 ¹⁹ cm ^-3 The above.

In the dopant concentration setting of the P-type polysilicon 32, as a preferred embodiment, the dopant concentration of the P-type polysilicon 32 may be set at 1×10 ¹⁹ cm ^-3 Above, i.e. greater than the N-type doping concentration of epitaxial layer 20, so that the depletion region diffuses towards the drift region to deplete the current, but too high a doping concentration may not be desirable, which may lead to degradation of material properties, such as reduced carrier mobility and reduced thermal stability, while if too low a doping concentration, the depletion region narrows, the blocking effect of the depletion region on the current becomes worse, and electrons may be turned on by means of a built-in electric field or drift effect at very low voltagesP-type polysilicon 32 is passed into source 50. Thus, in practice, the doping concentration also needs to be reasonably selected and adjusted according to the specific application requirements and process conditions.

Optionally, the epitaxial layer 20 includes an N-type drift region 23, and the P-type polysilicon 32 is in stacked contact with the N-type drift region 23, the N-type drift region 23 having a doping concentration of not more than 1×10 ¹⁷ cm ^-3 。

Under the above structure, a heterojunction diode can be formed for reverse freewheeling by contacting the P-type polysilicon 32 with the N-type drift region 23, and when the concentration of the N-type drift region 23 is too high, the band bending at the heterojunction junction is increased, so that the built-in electric field is enhanced, the tunnel length is shortened, and the electron tunneling from the P-type polysilicon 32 to the N-type drift region 23 is more likely to occur, so that the source leakage current is increased and the reverse breakdown voltage is degraded. At the same time, the contact between the p+ type floating region 41 and the N type drift region 23 expands the depletion region to increase the doping concentration in the epitaxial layer 20, if the original doping concentration of the N type drift region 23 is too high, the N type drift region is more likely to cause the narrowing of the potential barrier at the heterojunction with the P type polysilicon 50, the electron tunneling is more likely to occur, and the stability of the device is reduced, therefore, preferably, the doping concentration of the N type drift region 23 may be set to be not more than 1×10 ¹⁷ cm ^-3 To ensure the reliability and stability of the device.

Optionally, the epitaxial layer 20 includes an N-type drift region 23 and a charge storage layer 24 sequentially stacked on the N-type substrate 10, and P-type polysilicon 32 is stacked in contact with the charge storage layer 24, where the P-type channel region 21, the n+ type source region 22, the gate trench 30 and the P-region 42 are located in the charge storage layer 24.

The charge storage layer (Charge Storage Layer, CSL) is a material layer for controlling carrier injection in the semiconductor device, and when the charge storage layer 24 is introduced, the doping concentration of the charge storage layer 24 is higher than that of the drift region and lower than that of the P-type polysilicon 32, so that the injection and diffusion of carriers can be effectively limited, the low resistance and high transparency can be maintained, the leakage current of the silicon carbide power device 100 can be reduced, the working efficiency and the reliability of the device can be effectively improved, and meanwhile, referring to the heterojunction energy pattern of the P-type polysilicon (P-POLY) and the N-type charge storage layer silicon carbide material (N-SiC) shown in fig. 10, the introduction of the CSL layer can further reduce the energy Δe-reverse required for reverse conduction and ensure the charge energy required for forward conduction, so that electrons can pass through the n+ type source region 22, the P-type channel region 21, the charge storage layer 24, the N-type substrate 23 and the N-type substrate 10 in sequence in the forward conduction, and the N-type polysilicon layer 24 and the N-type substrate 60 in the reverse conduction, and the N-type polysilicon layer 60 in sequence in the forward conduction, and the N-type polysilicon layer 60 in the sequence can pass through the n+ type source region 22, the P-type channel region 21 and the N-type substrate 10 in the N-type substrate 60 in the forward conduction.

Optionally, the charge storage layer 24 has a doping concentration of no more than 1×10 ¹⁷ cm ^-3 。

Similar to the drift region, the charge storage layer 24 is in contact with the P-type polysilicon 32 after the addition of the layer, and therefore has the same definition of doping concentration, which is not described in detail herein. In addition, the concentration of the carrier should be set to be slightly higher than that of the N-type drift region 23, so that the injection and diffusion of carriers can be effectively limited, and the reliability and stability of the device can be effectively improved.

Optionally, the p+ type floating region 41 extends to a side close to the gate trench 30 to a position directly below a side of the P type polysilicon 32 away from the floating region.

The p+ type floating region 41 is a region heavily doped with P-type ions, and is connected to the P-type region 42 to form a floating junction, while the other end of the P-type region 42 is connected to the P-type channel region 21, and when the P-type channel region 21 is opened, i.e., the forward conducting source 50 is grounded, the P-type channel region 21 is opened, which corresponds to the floating junction structure being grounded, so the structure is called a ground junction. By extending the p+ type floating region 41 to one side of the P type polysilicon 32, the structure of the semi-packet UMOS structure and the epitaxial region form a depletion region structure, which can effectively smooth the electric field distribution in the N type drift region 23, reduce the peak electric field, and thus improve the voltage withstanding capability of the device. The length of the p+ type floating region 41 is controlled, if too long, the electron conduction channel is affected, if too short, the electric field cannot be well smoothed, so that the p+ type floating region is preferably extended and half-wrapped with the gate groove, a better compromise effect can be achieved, and the reliability and stability of the silicon carbide power device are further improved.

In addition, in the conventional floating region structure, the heavily doped p+ floating region is deeply implanted into the epitaxial layer, so that a built-in electric field is generated, a minority carrier storage effect (Minority Carrier Storage Effect) occurs, and when the on state is switched to the off state, the stored carriers need a certain time to be completely eliminated, so that the switching frequency is reduced, the current in the device is unstable and delayed, and the device and the performance thereof are negatively affected. However, the effect of minority carrier storage is greatly reduced, and as can be seen from the heterojunction energy band diagram shown in fig. 3, there is no barrier difference between the P-type polysilicon 32 and the heterojunction formed between the N-type silicon carbide material of the epitaxial layer 20 for minority carrier holes, and minority carrier holes can directly pass through the P-type polysilicon 32 from the epitaxial layer 20 to the source 50, so that the switching performance of the silicon carbide power device 100 is effectively ensured, and the reliability and stability of the silicon carbide power device are further improved.

Based on the above structure, referring to fig. 11 and fig. 12 in combination, fig. 11 is a schematic flow structure diagram of a method for manufacturing a silicon carbide power device 100 provided in the present application, and fig. 12 is a schematic flow step diagram of the flow structure in the present application, where the manufacturing method includes:

step 110: an N-type substrate 10 is provided.

The substrate (substrate) refers to a wafer made of a semiconductor material, and can directly enter a wafer manufacturing production link to produce a semiconductor device, or can be subjected to epitaxial processing to produce an epitaxial wafer, and the N-type substrate 10, i.e., a substrate with a conductivity type of N-type and conducting electricity through electrons, can be obtained by doping pentavalent elements such as phosphorus, arsenic and the like. The N-type substrate 10 used in the present embodiment is preferably a silicon carbide substrate, which may be provided by a wafer manufacturing factory, or may be manufactured by performing single crystal growth and wafer dicing, polishing, and the like on silicon carbide powder by itself, which is not particularly limited in this application. Optionally, wafer cleaning (Wafer cleaning) may be performed after the N-type substrate 10 is obtained, such as chemical cleaning, mechanical cleaning, and thermal treatment, to ensure cleanliness of the Wafer surface, so as to reduce defects and reject rate in subsequent processes, and also to make proper cleaning methods and parameter settings very important, which may damage the substrate surface or introduce new contaminants.

Step 120: an epitaxial layer 20 is formed on the N-type substrate 10 and ion implantation is performed on the epitaxial layer 20 to form a P-type channel region 21 in the epitaxial layer 20, an n+ -type source region 22 is formed in the P-type channel region 21, a p+ -type floating region 41 is formed below the gate trench 30, and a P-region 42 is formed between the p+ -type floating region 41 and the P-type channel region 21.

An Epitaxial Layer (epi Layer), a thin single crystal Layer deposited on a single crystal substrate, forms the epi Layer 20 by Epitaxial growth or deposition on the N-type substrate 10. The epitaxial growth method or deposition method may be physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), molecular beam epitaxy (Molecular Beam Epitaxy, MBE) or liquid phase epitaxy (Liquid Phase Epitaxy, LPE), which is not particularly limited in this application. Preferably, the epitaxial layer 20 and the N-type substrate 10 are of a homogenous silicon carbide material, which allows for a good lattice match between the epitaxial layer 20 and the substrate, thereby reducing defects and stresses, facilitating improved yield in the fabrication of the device, and better performance of the device.

Alternatively, the epitaxial layer 20 includes an N-type drift region 23 or includes an N-type drift region 23 and a charge storage layer 24 sequentially stacked on the N-type substrate 10, in which case a P-type polysilicon 32 is stacked with the N-type drift region 23, and in which case the charge storage layer 24 is included. The N-type drift region 23 or the charge storage layer 24 is a part of the epitaxial layer 20 in the manufacturing method, and may be obtained by performing ion implantation by an epitaxial growth method such as solid phase epitaxy or vapor phase epitaxy, and will not be described herein.

Ion Implantation (Ion Implantation) is a doping process in which atoms of impurity elements are ionized to form charged impurity ions, the charged impurity ions are accelerated under a strong electric field, high energy is obtained and then bombarded into corresponding regions of a semiconductor device, and then the impurities are activated through annealing, so that certain impurity distribution is formed in a semiconductor wafer. The P-type channel region 21, the p+ -type suspended region 41 and the P-type region 42 formed in this step are obtained by ion implantation doping of trivalent elements such as aluminum, boron and gallium, wherein the p+ -type suspended region 41 is obtained by ion heavily doping of trivalent elements with a better concentration, and the n+ -type source region 22 is obtained by ion heavily doping implantation of pentavalent elements such as phosphorus, arsenic and nitrogen. Optionally, when the p+ type floating region 41 needs to be extended, the implantation direction, the implantation speed and the implantation amount are adaptively adjusted due to the difference between the region and the region area, so as to form the region structures.

Step 130: the epitaxial layer 20 is etched to form a gate trench 30 through the P-type channel region 21 and the n+ type source region 22.

Etching (Etch) is a process of selectively removing unwanted material from the wafer surface, either chemically or physically, and is a generic term for stripping and removing material by solution, reactive ions, or other mechanical means. Etching techniques are largely divided into Dry Etching (Dry Etching) and Wet Etching (Wet Etching). The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching. The present embodiment preferably adopts a dry etching method, and etches the n+ type source region 22 and the P type channel region 21 by reactive ion etching, plasma etching or sputter etching to form the gate trench 30. The gate trench 30 penetrates the n+ type source region 22 and the P type channel region 21 to serve as a region for subsequently depositing the gate electrode 31 polysilicon material, the P type polysilicon 32 material and the corresponding oxide layer thereof, and in addition, the arrangement of the region is beneficial to saving the device area, reducing the on-resistance and improving the reliability and stability of the device.

Step 140: a thick oxide layer is deposited and etched into the gate trench 30 to form a window.

Oxidation is a step of forming a silicon dioxide film on a surface to prevent impurities from penetrating and diffusing, and mainly comprises a thermal oxidation method and a field oxygen deposition method, wherein the thermal oxidation method is to react a silicon-containing material with an oxygen-containing material at a high temperature to form the silicon dioxide film, and the field oxygen deposition is to activate one or more gases on the surface in a certain way by using a chemical vapor deposition technology, so that the silicon dioxide film is formed at a deposition position. In this step, a field oxygen deposition mode is adopted, and a window is formed through an etching step, so that P-type polysilicon 32 is formed in the window to be in contact with an epitaxial layer 20 at the lower side of the trench, and reverse freewheeling is performed, and the oxide layer can be used for protecting the P-type polysilicon 32 from being in contact with other regions, so that a better reverse freewheeling effect is achieved.

Step 150: p-type polysilicon 32 is formed in the window and the thick oxide layer on the sidewalls of gate trench 30 is etched away.

The P-type polysilicon 32 can be formed in the window by the conventional deposition method such as chemical vapor deposition or physical vapor deposition, and the process is simple and can generate great benefit, thereby being beneficial to improving the reliability and stability of the device. After the deposition is completed, the oxide layer on the sidewall can complete the function of preventing the P-type polysilicon 32 material from entering the active region, so that the thick oxide layer on the sidewall of the gate trench 30 can be removed, and the situation that the excessively thick oxide layer cannot cause insufficient space of the gate 31 and cannot control the conduction of current is avoided, thereby laying a foundation for the subsequent steps.

Step 160: thermal oxidation is performed on the epitaxial layer 20 and the thick oxide layer to form a thermal oxide layer surrounding the P-type polysilicon 32 and covering the epitaxial layer 20, and the gate 31 polysilicon is deposited on the thermal oxide layer.

The device is also protected by oxidation during the polysilicon process of the gate electrode 31, and the optional oxidation and deposition steps are similar to those described above and are not repeated here.

Step 170: the gate 31 polysilicon is etched and field oxide deposition is performed to form the gate 31 and a gate oxide layer 33 surrounding the gate 31.

The arrangement of the grid electrode 31 is generally provided with a preset shape, size and position, and the stability of the grid electrode 31 morphology is favorable for realizing a better control effect, so that the normal operation of a device is ensured, therefore, after the grid electrode 31 polysilicon is deposited, the grid electrode 31 morphology can be formed by etching, after the morphology is etched, the grid electrode 31 morphology is further formed by wrapping the grid electrode oxide layer 33, and the external invasion is prevented, so that the reliability and the stability of the device are further ensured, and the corresponding conduction control function of the device is better realized. The etching and oxidizing steps can be referred to as the foregoing steps, and are not described herein.

Step 180: source 50 is deposited to cover N + type source region 22 and gate oxide 33 and drain 60 is deposited on the side of N-type substrate 10 facing away from epitaxial layer 20.

In the process of manufacturing the silicon carbide power device 100, a metal layer needs to be deposited to achieve the conductive connection and other functions, wherein common metal deposition materials include metal materials such as nickel, chromium, titanium, zirconium and cobalt, or other materials with better electrical conductivity and thermal conductivity obtained by combining the metal materials. Both chemical vapor deposition and physical vapor deposition can be used as a means of depositing metal electrodes. In the embodiment of the invention, the metal electrode is preferably deposited by adopting a chemical vapor deposition method, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like. TiC or TiN is usually deposited by introducing TiCl4, H2, CH4 and other gases into a reaction chamber at 850-1100 ℃ and forming a coating on the surface of the device through chemical reaction, wherein the coating can form good ohmic contact with silicon carbide materials, and finally the deposited source electrode 50 and drain electrode 60 metals have good electrical conductivity and thermal conductivity, so that the reliability and stability of the silicon carbide power device 100 are improved.

Based on the above-described manufacturing methods as illustrated in the steps of fig. 11 to 12, it should be noted that concentration limitation of each layer region is required during the doping process in the preparation of the silicon carbide power device 100, and limitation of width, thickness, depth, etc. of each layer region is required during the steps of deposition, etching, etc., and specific reference may be made to specific limitations in the silicon carbide power device 100 described in fig. 1 to 10, which are not repeated herein. For example, in the doping process, the high-purity doping source can be selected, the doping process and parameter setting can be optimized, the energy and the dosage of doping injection can be controlled, the doping concentration can be monitored and measured in real time, the process parameters can be adjusted in time to ensure the stability of the doping concentration, advanced reaction cavities and control technology can be adopted in the steps of deposition, etching and the like, parameters such as temperature, pressure, gas flow and the like of each layer region can be controlled, and an accurate thickness measuring and monitoring system can be adopted to ensure the accuracy of the width, thickness, depth and the like of each layer region. Meanwhile, the stability of environmental conditions and process parameters needs to be strictly controlled in the whole preparation process, and the influence of various external factors on the performance of the device is avoided, so that the reliability and stability of the silicon carbide power device are improved.

Unlike the prior art, the application discloses a silicon carbide power device and a manufacturing method thereof. Through setting up with the grid adjacent setting and with epitaxial layer range upon range of P type polycrystalline silicon that contacts in carborundum power device to can obtain the freewheel passageway, so that the device can open under lower reverse voltage, and have better breakdown voltage and on resistance compromise effect, realize reverse freewheel, simultaneously, the cost and the technology degree of difficulty of this mode are relatively lower, under the circumstances that do not exert an influence to chip area and forward conduction characteristic, can effectively promote the conduction speed and the switching frequency of device, reduce switching loss, promote switching performance.

The foregoing description is only exemplary embodiments of the present application and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the present application.

Claims

1. A silicon carbide power device, comprising:

an N-type substrate;

the epitaxial layer is arranged on the N-type substrate, a P-type channel region is formed in the epitaxial layer, an N+ type source region is formed in the P-type channel region, a grid groove penetrates through the P-type channel region and the N+ type source region, a P+ type suspension region is arranged below the grid groove, and a P region is arranged between the P+ type suspension region and the P-type channel region;

a gate filled in the gate trench;

the source electrode is arranged on the epitaxial layer and covers the P-type channel region, the N+ type source region and the grid electrode;

the P-type polycrystalline silicon is arranged on the groove wall of the grid groove and is arranged in a semi-surrounding mode around the grid, is contacted with the epitaxial layer at the bottom of the grid groove and is contacted with the source electrode;

and the drain electrode is arranged on one side of the N-type substrate, which is away from the epitaxial layer.

2. The silicon carbide power device of claim 1, wherein the P-type polysilicon has a width of 0.1 to 0.4 μm.

3. The silicon carbide power device of claim 1 or 2, wherein the P-type polysilicon has a doping concentration of 1 x 10 ¹⁹ cm ^-3 The above.

4. The silicon carbide power device of claim 1, wherein the epitaxial layer includes an N-type drift region, the P-type polysilicon being in stacked contact with the N-type drift region, the N-type drift region having a doping concentration of no more than 1 x 10 ¹⁷ cm ^-3 。

5. The silicon carbide power device of claim 1, wherein the epitaxial layer comprises an N-type drift region and a charge storage layer stacked in sequence on the N-type substrate, the P-type polysilicon is in stacked contact with the charge storage layer, and the P-type channel region, the n+ type source region, the gate trench, and the P-region are all located in the charge storage layer.

6. The silicon carbide power device of claim 5, wherein the charge storage layer has a doping concentration of no more than 1 x 10 ¹⁷ cm ^-3 。

7. The silicon carbide power device of claim 1, wherein the p+ type floating region extends to a side proximate to the gate trench to a side directly below the side of the P type polysilicon remote from the floating region.

8. A method for manufacturing a silicon carbide power device is characterized in that,

providing an N-type substrate;

forming an epitaxial layer on the N-type substrate, and performing ion implantation on the epitaxial layer to form a P-type channel region in the epitaxial layer, forming an N+ type source region in the P-type channel region, forming a p+ type suspended region below the gate trench, and forming a P region arranged between the p+ type suspended region and the P-type channel region;

etching the epitaxial layer to form a gate trench passing through the P-type channel region and the n+ type source region;

depositing a thick oxide layer in the grid electrode groove and etching to form a window;

forming P-type polycrystalline silicon on the window, and etching to remove the thick oxide layer on the side wall of the grid electrode groove;

performing thermal oxidation on the epitaxial layer and the thick oxide layer to form a thermal oxide layer which wraps the P-type polycrystalline silicon and covers the epitaxial layer, and depositing grid polycrystalline silicon on the thermal oxide layer;

etching the grid polysilicon and performing field oxide deposition to form the grid and a grid oxide layer wrapping the grid;

and depositing a source electrode to cover the N+ type source region and the gate oxide layer, and depositing a drain electrode on one side of the N type substrate, which is away from the epitaxial layer.

9. The method of claim 8, wherein the epitaxial layer comprises an N-type drift region and a charge storage layer sequentially stacked on the N-type substrate, the P-type polysilicon is in stacked contact with the charge storage layer, and the P-type channel region, the n+ type source region, the gate trench, and the P region are all located in the charge storage layer.

10. The method of claim 8, wherein the p+ type floating region extends to a side close to the gate trench to a position directly below a side of the P type polysilicon away from the floating region.