CN117690972A

CN117690972A - Silicon carbide power device and manufacturing method thereof

Info

Publication number: CN117690972A
Application number: CN202410153478.1A
Authority: CN
Inventors: 乔凯
Original assignee: Shenzhen Sirius Semiconductor Co ltd
Current assignee: Shenzhen Sirius Semiconductor Co ltd
Priority date: 2024-02-04
Filing date: 2024-02-04
Publication date: 2024-03-12

Abstract

The application discloses a silicon carbide power device and a manufacturing method thereof. The silicon carbide power device includes: an N-type substrate; the epitaxial layer is arranged on the N-type substrate, a P-type channel region is formed in the epitaxial layer, an N+ type source region is formed in the P-type channel region, and a source groove is arranged on the epitaxial layer, penetrates through the N+ type source region and the P-type channel region, and a P+ body region is formed on the side wall of the source groove; the grid electrode is arranged on one side of the epitaxial layer, which is away from the N-type substrate, and spans the region of the P-type channel region, which is exposed on the surface of the epitaxial layer; p-type polysilicon, which is arranged adjacent to the grid electrode and is in laminated contact with the epitaxial layer; the source electrode is filled in the source electrode groove and covers the P+ body region, the N+ type source region, the grid electrode and the P type polysilicon; and the drain electrode is arranged on one side of the N-type substrate, which is away from the epitaxial layer. By the device, the silicon carbide power device can be reversely freewheeled with low cost and low occupation, the switching-on efficiency of the device is improved, and the freewheeling starting voltage and loss thereof are reduced.

Description

Silicon carbide power device and manufacturing method thereof

Technical Field

The application relates to the technical field of semiconductor devices, in particular to a silicon carbide power device and a manufacturing method thereof.

Background

Under the background that the performance of the traditional silicon (Si) base power device is difficult to obtain great optimization, the silicon carbide (SiC) material lays the advantages of the silicon carbide power device manufactured by using the SiC material as a bulk material in the application fields of high temperature, high voltage, high speed, strong radiation and the like due to the excellent electrical properties such as wide forbidden bandwidth, high critical breakdown voltage, high thermal conductivity, high saturated electron drift speed and the like.

Among them, silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices have become research hot spots in the current silicon carbide power device field by virtue of their characteristics of fast switching speed, low switching loss, small on-resistance, wide operating temperature range, etc. Among the numerous silicon carbide MOSFET device structures, a Double-Trench MOSFET (DT-MOS) device has been one of the mainstream structures of silicon carbide MOSFET designs by introducing two types of trenches into the device, which exhibits advantages of high withstand voltage, low on-resistance, high reliability, and the like, as compared with conventional vertical MOSFET devices.

However, the actual application circuit of the silicon carbide MOSFET device often has an inductance element, which can form a larger reverse current impact, and the freewheel turn-on voltage of the silicon carbide MOSFET device is far higher than that of the silicon-based MOSFET device, and the occurrence of these situations increases the requirement of the device on the freewheel turn-on voltage. The existing methods have the following functions through anti-parallel diodes or body diodes and solve the problems through reverse follow currents through split gate structures, however, the methods can cause the problems of increased chip area, increased process complexity, reduced current density and the like, the process cost is increased, and the reliability and the stability of the device are reduced.

Disclosure of Invention

The application mainly provides a silicon carbide power device and a manufacturing method thereof, and aims to solve the technical problems that the follow current starting voltage of the silicon carbide power device is too high and is difficult to start.

In order to solve the technical problems, one technical scheme adopted by the application is as follows: a silicon carbide power device is provided. The silicon carbide power device includes: an N-type substrate; the epitaxial layer is arranged on the N-type substrate, a P-type channel region is formed in the epitaxial layer, an N+ type source region is formed in the P-type channel region, and a source groove is arranged on the epitaxial layer, penetrates through the N+ type source region and the P-type channel region, and a P+ body region is formed on the side wall of the source groove; the grid electrode is arranged on one side, away from the N-type substrate, of the epitaxial layer and spans the region, exposed on the surface of the epitaxial layer, of the P-type channel region; p-type polysilicon, which is arranged adjacent to the grid electrode and is in laminated contact with the epitaxial layer; the source electrode is filled in the source electrode groove and covers the P+ body region, the N+ type source region, the grid electrode and the P type polycrystalline silicon; and the drain electrode is arranged on one side of the N-type substrate, which is away from the epitaxial layer.

In some embodiments, the P-type polysilicon has a width of 0.1 to 0.4 μm.

In some embodiments, the P-type polysilicon has a doping concentration of 1×10 ¹⁹ cm ^-3 The above.

In some embodiments, the source trench includes a first level trench and a second level trench arranged in a step, the second level trench is arranged at the bottom of the first level trench, and the first level trench passes through the n+ type source region and the P type channel region.

In some embodiments, the first level trenches and the second level trenches have a total depth of 1.5 to 4.0 μm.

In some embodiments, the epitaxial layer includes an N-type drift region, the P-type polysilicon being in stacked contact with the N-type drift region; or the epitaxial layer comprises an N-type drift region and a charge storage layer which are sequentially stacked on the N-type substrate, the P-type polysilicon is in stacked contact with the charge storage layer, the P-type channel region and the N+ type source region are both positioned on the charge storage layer, and the source trench penetrates through the charge storage layer and extends to the N-type drift region.

In some embodiments, the P-type polysilicon is in stacked contact with the N-type drift region having a doping concentration of no more than 1×10 ¹⁷ cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the Or the P-type polysilicon is in laminated contact with the charge storage layer, the doping concentration of the charge storage layer is not more than 1×10 ¹⁷ cm ^-3 。

In order to solve the technical problems, another technical scheme adopted by the application is as follows: a method for manufacturing a silicon carbide power device. The manufacturing method of the silicon carbide power device comprises the following steps: providing an N-type substrate; forming an epitaxial layer on the N-type substrate; ion implantation is carried out on the epitaxial layer so as to form a P-type channel region in the epitaxial layer and an N+ type source region in the P-type channel region; etching the epitaxial layer to form a source trench penetrating through the N+ type source region and the P type channel region; p+ implantation is conducted on the side wall of the source electrode groove so as to form a P+ body region; setting a grid electrode in a region, exposed on the surface of the epitaxial layer, of the P-type channel region and an oxide layer wrapping the grid electrode; a P-type polysilicon layer is arranged on the epitaxial layer in a stacked mode, and the P-type polysilicon layer is adjacent to the grid electrode; and depositing a source electrode to fill the source electrode groove and cover the P+ body region, the N+ type source region, the grid electrode and the P type polycrystalline silicon, and depositing a drain electrode on one side of the N type substrate, which is far away from the epitaxial layer.

In some embodiments, the source trench includes a first level trench and a second level trench arranged in a step, and the etching the epitaxial layer includes: forming the first-stage groove passing through the N+ type source region and the P type channel region by dry etching; and depositing oxide on the first-stage groove to be used as a hard mask, and etching to form the second-stage groove.

The beneficial effects of this application are: unlike the prior art, the application discloses a silicon carbide power device and a manufacturing method thereof. Through setting up with the grid adjacent setting and with epitaxial layer range upon range of P type polycrystalline silicon that contacts in carborundum power device to can obtain the freewheel passageway, so that the device can open under lower reverse voltage, and have better breakdown voltage and on resistance compromise effect, realize reverse freewheel, simultaneously, the cost and the technology degree of difficulty of this mode are relatively lower, under the circumstances that do not exert an influence to chip area and forward conduction characteristic, can effectively promote the conduction speed and the switching frequency of device, reduce switching loss, promote switching performance. In addition, the on-resistance can be reduced by epitaxially growing the charge storage layer, and the expansion of the depletion region can be realized by etching the first-stage groove and the second-stage groove which are arranged in a step manner, so that the switching performance of the device is further enhanced, the loss is reduced, and the reliability and the stability of the silicon carbide power device are further improved.

Drawings

For a clearer description of embodiments of the present application or of the solutions of the prior art, the drawings that are required to be used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the present application, and that other drawings may be obtained, without inventive effort, by a person skilled in the art from these drawings, in which:

FIG. 1 is a schematic diagram of an embodiment of a silicon carbide power device provided herein;

FIG. 2 is a heterojunction energy band diagram of N-type polysilicon (N-POLY) in contact with N-type silicon carbide (N-SiC) material;

FIG. 3 is a heterojunction energy band diagram of P-type polysilicon (P-POLY) in contact with N-type silicon carbide material (N-SiC);

FIG. 4 is a schematic diagram of breakdown voltage characteristics of a conventional planar gate (CONV) MOSFET, a P-type polysilicon (P-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET, and a TCAD simulation of an N-type polysilicon (N-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET;

FIG. 5 is a schematic diagram of on-resistance characteristics of a conventional planar gate (CONV) MOSFET, a P-type polysilicon (P-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET, and a TCAD simulation of an N-type polysilicon (N-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET;

FIG. 6 is a schematic diagram of the freewheel turn-on voltage characteristics of a conventional planar gate (CONV) MOSFET, a P-type polysilicon (P-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET, and a TCAD simulation of an N-type polysilicon (N-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET;

FIG. 7 is a schematic diagram of the current density distribution of a conventional planar gate (CONV) MOSFET, a P-type polysilicon (P-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET, and an N-type polysilicon (N-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET breakdown;

FIG. 8 is a schematic diagram of potential distribution of a conventional planar gate (CONV) MOSFET, a P-type polysilicon (P-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET, and an N-type polysilicon (N-POLY) and N-type silicon carbide (N-SiC) heterojunction MOSFET breakdown;

FIG. 9 is a schematic diagram of another embodiment of a silicon carbide power device provided in FIG. 1;

FIG. 10 is a heterojunction energy band diagram of P-type polysilicon (P-POLY) in contact with N-type charge storage layer silicon carbide material (N-SiC);

FIG. 11 is a schematic flow chart of a method for fabricating a silicon carbide power device according to the present disclosure;

FIG. 12 is a schematic flow chart of a method of fabricating the silicon carbide power device of FIG. 11;

fig. 13 is a schematic diagram illustrating steps in a process for fabricating a silicon carbide power device according to an embodiment of step 140 in the method of fig. 12.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The terms "first," "second," "third," and the like in the embodiments of the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic flow chart of an embodiment of a silicon carbide power device provided in the present application. The silicon carbide power device 100 includes: an N-type substrate 10; the epitaxial layer 20 is arranged on the N-type substrate 10, a P-type channel region 30 is formed in the epitaxial layer 20, an N+ type source region 40 is formed in the P-type channel region 30, and a source trench 50 is arranged on the epitaxial layer 20, the source trench 50 penetrates through the N+ type source region 40 and the P-type channel region 30, and a P+ body region 60 is formed on the side wall of the source trench 50; the grid electrode 70 is arranged on one side of the epitaxial layer 20, which is away from the N-type substrate 10, and spans the region of the P-type channel region 30 exposed on the surface of the epitaxial layer 20; a P-type polysilicon 80 disposed adjacent to the gate 70 and in stacked contact with the epitaxial layer 20; a source 91 filled in the source trench 50 and covering the p+ body region 60, the n+ source region 40, the gate 70 and the P-type polysilicon 80; and a drain 92 disposed on a side of the N-type substrate 10 facing away from the epitaxial layer 20.

The silicon carbide power device 100 is a vertically conductive double-trench MOSFET device, wherein the source 91 is grounded or low, the drain 92 is high, and when the voltage of the gate 70 is greater than a certain threshold voltage, the P-type channel region 30 is opened, the P-type polysilicon 80 and the epitaxial layer 20 are depleted and turned off, electrons in the device sequentially pass through the n+ type source region 40, the P-type channel region 30, the epitaxial layer 20 and the N-type substrate 10 from the source 91 into the drain 92; and when the device is conducted reversely, the grid electrode 70 and the drain electrode 92 are grounded or low-level, the source electrode 91 is connected with high-level, the P-type channel is closed, the conduction and continuous flow of the P-type polysilicon 80 and the epitaxial layer 20 are realized reversely, and electrons in the device sequentially pass through the N-type substrate 10, the epitaxial layer 20 and the P-type polysilicon 80 from the drain electrode 92 to enter the source electrode 91.

Among them, polysilicon (Poly) is a form of silicon crystal composed of many small crystals or grains, and when doped with acceptor impurities such as boron, aluminum, gallium and the like, it is mainly hole-conductive to form the P-type polysilicon (P-Poly), and when doped with donor impurities such as phosphorus, nitrogen, arsenic and the like, it is mainly electron-conductive to form the N-type polysilicon (N-Poly). The P-type polysilicon or the N-type polysilicon can be contacted with the N-type doped silicon carbide material through the structure to form a heterojunction structure.

In the silicon carbide power device 100 provided by the present invention, referring to fig. 2 and 3, fig. 2 is a heterojunction energy band diagram of N-type polysilicon (N-POLY) in contact with N-type silicon carbide (N-SiC) material, and fig. 3 is a heterojunction energy band diagram of P-type polysilicon (P-POLY) in contact with N-type silicon carbide material (N-SiC). In order to play a role of freewheel, the energy Δe-reverse required for reverse conduction of the heterojunction should be ensured to be small enough to ensure that the heterojunction can be turned on under a lower reverse voltage, while as can be seen from fig. 2 and 3 of the energy band, the energy required for reverse conduction of the heterojunction structure formed by the N-type polysilicon and the silicon carbide material is lower than the energy required for reverse conduction of the heterojunction structure formed by the P-type polysilicon and the silicon carbide material, so that the heterojunction structure formed by the N-type polysilicon and the silicon carbide material has better freewheel capability, but in practice, when the device is turned on, the breakdown voltage characteristics simulated by TCAD (Technology Computer Aided Design) of the conventional planar gate (CONV) MOSFET, the P-type polysilicon (P-POLY) and the N-type silicon carbide (N-SiC) heterojunction MOSFET and the N-type polysilicon (N-SiC) are almost bad in practical breakdown voltage, compared with the conventional planar gate MOSFET and the P-type MOSFET, so that the breakdown voltage is hardly bad in practice.

Meanwhile, according to the schematic view of the on-resistance characteristics of the conventional planar gate (CONV) MOSFET, the P-type polysilicon (P-POLY) and the N-type silicon carbide (N-SiC) heterojunction MOSFET and the TCAD simulation of the N-type polysilicon (N-POLY) and the N-type silicon carbide (N-SiC) heterojunction MOSFET shown in fig. 5, and the schematic view of the freewheel on-voltage characteristics of the conventional planar gate (CONV) MOSFET, the P-type polysilicon (P-POLY) and the N-type silicon carbide (N-SiC) heterojunction MOSFET and the TCAD simulation of the N-type polysilicon (N-POLY) and the N-type silicon carbide (N-SiC) shown in fig. 6, it is known that the influence of the P-type polysilicon on the breakdown voltage is small and the freewheel channel on-voltage is about 1.5 to 1.8V, the freewheel on-voltage is about 30% lower than that of the conventional planar gate MOSFET body diode 2.4 to 2.8V, and the current density is equivalent, the freewheel effect is better, and the freewheel effect can be achieved by effectively raising the contact between the P-type polysilicon and the epitaxial layer and the freewheel device on-frequency and the freewheel device on-frequency can be reduced. As can be seen from the current density distribution diagrams of the three structures shown in fig. 7 and the potential distribution diagrams of the three structures shown in fig. 8 at the time of breakdown, the MOSFET structure using P-type polysilicon is typically Junction breakdown like a conventional planar gate structure, that is, breakdown occurs at the PN Junction formed by the n+ type source region and the P-type channel, while N-type polysilicon breaks down at the heterojunction in the JFET (Junction Field-Effect Transistor) region, that is, the middle region of the P-type channel region on both sides, and the internal current density is three orders of magnitude higher than that of the other two structures at the time of breakdown, and meanwhile, the MOSFET structure using N-type polysilicon is denser in potential line, that is, higher in peak electric Field and weaker in withstand voltage capability, as can be seen from the potential distribution of the three cases. Thus, as can be seen from the comparison of fig. 2 to 8, the MOSFET device using the P-type polysilicon structure has better performance advantages compared to the MOSFET device using the N-type polysilicon structure and the conventional planar gate structure, and the corresponding silicon carbide power device has better reliability and stability.

In addition, the cost and space resources occupied by the structure are also less. When the P-type polysilicon 80 is not used, the gate 70 is a whole, the current of the P-type polysilicon is mainly controlled to be conducted through the gate 70 when the P-type polysilicon is conducted in the forward direction or the reverse direction, and a part of the middle of the gate 70 is not practically conducted or only a small amount of current is conducted, so that the middle part is made into a freewheeling channel, the reverse freewheeling can be realized under the condition of having no or little influence on a device, the introduction of the P-type polysilicon structure is more universal in process and materials, the occupied resources of the chip space are less, the P-type polysilicon is convenient to be integrated into corresponding devices, and the cost and the loss are saved.

Alternatively, the P-type polysilicon 80 has a width of 0.1 to 0.4 μm.

Specifically, the P-type polysilicon 80 may have a width of 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, or the like. In the case that the width of the P-type polysilicon 80 is less than 0.1 μm, the P-type polysilicon 80 cannot well load the reverse current, the reverse freewheeling ability is weak, if the width of the P-type polysilicon 80 exceeds 0.4 μm, the area of the gate 70 is excessively occupied, so that the gate 70 cannot control the P-type channel region 30, the current control capability is lost, and when the drain-source voltage is large, the current may directly enter the epitaxial layer 20 through the P-type polysilicon 80, thereby greatly affecting the performance of the device, and the excessively wide P-type polysilicon 80 also causes the increase of the chip area and the increase of the cost. Therefore, as a preferred embodiment, the width of the P-type polysilicon 80 may be set to be between 0.1 and 0.4 μm, so as to prevent or reduce interference to the control effect of the gate 70 while ensuring the reverse freewheeling function, thereby ensuring the reliability and stability of the device. In addition, the width of the P-type polysilicon 80 may be adaptively adjusted according to the process or overall ratio, so long as the reverse freewheeling is effectively performed without affecting the control of the gate 70.

Optionally, the P-type polysilicon 80 has a doping concentration of 1×10 ¹⁹ cm ^-3 The above.

In the dopant concentration setting of the P-type polysilicon 80, as a preferred embodiment, the dopant concentration of the P-type polysilicon 80 may be set at 1×10 ¹⁹ cm ^-3 Above, i.e. greater than the N-type doping concentration of the epitaxial layer 20, so that the depletion region diffuses towards the drift region to deplete the current, but too high a doping concentration is not preferred, which may lead to degradation of material properties such as reduced carrier mobility and reduced thermal stability, while if too low a doping concentration, the depletion region narrows, the blocking effect of the depletion region against the current becomes worse, and electrons may be able to enter the source 91 through the P-type polysilicon 80 by means of a built-in electric field or drift effect at very low voltages. Thus, in practice, the doping concentration also needs to be reasonably selected and adjusted according to the specific application requirements and process conditions.

Optionally, the source trench 50 includes a first level trench 51 and a second level trench 52 disposed in a step manner, the second level trench 52 is disposed at the bottom of the first level trench 51, and the first level trench 51 passes through the n+ type source region 40 and the P type channel region 30.

In this embodiment, the source trench 50 is a two-level step trench structure, because it penetrates the n+ type source region 40 and the P type channel region 30 into the epitaxial layer 20, and forms a p+ body region 60 on the sidewall thereof, so that the present silicon carbide power device 100 can be regarded as a Semi-super junction (Semi-super junction) device, i.e., a PN junction structure established perpendicular to a portion of the space of the epitaxial layer 20. The semi-superjunction structure forms a depletion region in the epitaxial layer 20, smoothes the internal electric field thereof, reduces the peak value of the electric field, and is beneficial to improving the voltage-withstanding capability of the device and reducing the on-resistance.

Meanwhile, the first-stage groove 51 in the arrangement of the two-stage step groove structure penetrates through the N+ type source region 40 and the P-type channel, so that corresponding electrons can be conducted through the source region and the P-type channel, and normal on-off of a device switch is realized. The p+ body region 60 in the trench structure can be used as a body diode to maintain reverse freewheeling when in reverse conduction, and when the P-type polysilicon 80 is arranged, since the freewheeling starting voltage is far higher than that of the reverse freewheeling diode formed by the P-type polysilicon 80 and the epitaxial layer 20, current can preferentially pass through the reverse freewheeling diode, so that the structure can effectively ensure the consistency of electrons and current conduction paths when in normal forward and reverse conduction, is beneficial to controlling devices, and reduces the freewheeling starting voltage and loss. The second-stage trench 52 is narrower than the first-stage trench 51, which reduces material loss and process cost, and can effectively maintain the smoothing and depletion effects of the semi-superjunction structure, thereby improving the reliability and stability of the silicon carbide power device 100.

In addition, in the conventional semi-superjunction structure, a heavily doped P-type body region is deeply injected into an epitaxial layer, a built-in electric field is generated, a minority carrier storage effect (Minority Carrier Storage Effect) occurs, and when an on state is switched to an off state, the stored carriers can be completely eliminated in a certain time, so that the switching frequency is reduced, the current in the device is unstable and delayed, and the device and the performance thereof are negatively affected. However, the effect of minority carrier storage is greatly reduced, and as can be seen from the heterojunction energy band diagram shown in fig. 3, there is no barrier difference between the P-type polysilicon 80 and the heterojunction formed between the N-type silicon carbide material of the epitaxial layer 20 for minority carrier holes, and minority carrier holes can directly pass through the P-type polysilicon 80 from the epitaxial layer 20 to the source 91, so that the switching performance of the silicon carbide power device 100 is effectively ensured, and the reliability and stability of the silicon carbide power device are further improved.

Alternatively, the total depth of the first level trenches 51 and the second level trenches 52 is 1.5 to 4.0 μm.

Specifically, the total depth of the first level trenches 51 and the second level trenches 52 may be 1.5 μm, 2.2 μm, 2.5 μm, 3.0 μm, 3.5 μm, 4.0 μm, or the like.

Because the hardness of silicon carbide is higher, the diffusion coefficient of impurities is lower, the difficulty in realizing the existing technical method such as deep groove etching backfill and multi-step epitaxial technology on the silicon carbide material is higher, the problems of alignment error and the like easily occur when deep grooves are etched, the super junction structure is difficult to realize, and the manufacturing process for realizing the semi-super junction structure is relatively simple. In this solution, considering the effectiveness of the device structure, that is, the semi-superjunction structure needs to pass through the n+ type source region 40 and the P type channel region 30 and smooth the electric field in the epitaxial layer 20, preferably, the total depth of the semi-superjunction structure needs to be set above 1.5 μm, and considering the etching cost and stability of the etching technology, the single-stage trench etching with a thickness of 1.5 to 2 μm is limited to the bench device, and the deeper etching may cause the shape of the trench to be poor, for example, the U shape in the embodiment may be changed into the V shape, so that the effect of the semi-superjunction is weakened. For deeper etching, it is also possible to consider that the opening width of the trench is widened to achieve more level etching or relatively deeper etching, but the positions of the P-type channel region and the n+ type source region need to be adjusted accordingly, the area of the chip needs to be increased to maintain the stability of the device, and the increase in the process complexity and the increase in the area of the chip also result in an increase in cost, so that, considering the relationship between the beneficial effect of the half superjunction structure and the area and cost of the chip, it is more preferable to etch the trench structure into a two-level structure, and the two-level step trench structure can be etched to about 3.0 μm-4.0 μm without affecting the area of the chip, thereby achieving a better compromise between performance and cost. Optionally, on the basis of not influencing the chip area and the trench morphology, along with continuous optimization of the process, the depth of the total depth can reach more than 4.0 mu m so as to realize a better half super junction effect, and on the basis of overall device proportion and material improvement, the setting of the range can be adaptively adjusted.

Optionally, the epitaxial layer 20 includes an N-type drift region 21, and the p-type polysilicon 80 is in stacked contact with the N-type drift region 21; or the epitaxial layer 20 comprises an N-type drift region 21 and a charge storage layer 22 which are sequentially stacked on the N-type substrate 10, the P-type polysilicon 80 is in stacked contact with the charge storage layer 21, the P-type channel region 30 and the n+ type source region 40 are both positioned on the charge storage layer 22, and the source trench 50 extends to the N-type drift region 21 through the charge storage layer 22.

The epitaxial layer 20 includes an N-Drift region (N-Drift) and may or may not include a charge storage layer (Charge Storage Layer, CSL), in which case the device structure is shown in fig. 1, and the epitaxial layer 20 may include N-Drift regions, in which case the device structure is shown in fig. 9, and the epitaxial layer 20 includes an N-Drift region 21 and a charge storage layer 22. The main body doping concentration of the N-type drift region 21 is low, so that most of the voltage in the device falls on the N-type drift region 21, thereby bearing high voltage and providing a current path, the structure and the characteristics of the N-type drift region 21 also directly influence the current control capability of the silicon carbide power semiconductor, and the control of current can be realized by adjusting the shape, the size and the doping concentration of the N-drift layer, so as to meet the requirements of different applications. In addition, the electric field concentration effect of the N-type drift region under high voltage can be relieved through the semi-superjunction structure, so that the electric field in the epitaxial layer 20 can be relatively evenly distributed, and the voltage-withstanding capability of the device can be improved.

When the epitaxial layer includes the charge storage layer 22, the doping concentration of the charge storage layer 22 is higher than the doping concentration of the drift region 21 and lower than the doping concentration of the P-type polysilicon 80, so that the injection and diffusion of carriers can be effectively limited, meanwhile, the low resistance and high transparency can be maintained, the leakage current of the silicon carbide power device 100 can be reduced, the working efficiency and reliability of the device can be effectively improved, meanwhile, referring to the heterojunction energy band diagram of the P-type polysilicon (P-POLY) in contact with the N-type charge storage layer silicon carbide material (N-SiC) shown in fig. 10, the introduction of the CSL layer can further reduce the energy Δe-reverse required for reverse conduction and ensure the charge energy required for forward conduction, so that electrons can pass through the n+ type source region 40, the P-type channel region 30, the charge storage layer 22, the N-type substrate 21 and the N-type substrate 10 in sequence during forward conduction, and can pass through the n+ type source region 91, the P-type channel region 30, the N-type charge storage layer 21 and the N-type substrate 10 into the drain 92 in sequence, and the forward conduction can pass through the N-type polysilicon layer 21 and the N-type substrate 10 in sequence.

Optionally, the P-type polysilicon 80 is in stacked contact with an N-type drift region 21 having a doping concentration of no more than 1 x 10 ¹⁷ cm ^-3 Or the P-type polysilicon 80 is in laminated contact with the charge storage layer 22, the charge storage layer having a doping concentration of not more than 1×10 ¹⁷ cm ^-3 。

In both cases, the P-type polysilicon 80 contacts the N-type drift region 21 or the charge storage layer 22 to form a heterojunction diode for reverse freewheeling, and when the concentration of the N-type drift region 21 or the charge storage layer 22 is too high, the band bending at the heterojunction junction is increased, so that the built-in electric field is enhanced, the tunnel length is shortened, and electron tunneling from the P-type polysilicon 80 to the epitaxial layer 20 is easier to occur, so that the source leakage current is increased, and the reverse breakdown voltage is deteriorated. Meanwhile, the above-mentioned semi-superjunction structure formed by the P-type body region 60 and the epitaxial layer 20 in the source trench 50 expands the depletion region, so that the doping concentration in the epitaxial layer 20 is increased, if the original doping concentration of the epitaxial layer 20 is too high, the barrier at the heterojunction with the P-type polysilicon 50 is more easily narrowed, and electron tunneling is more easily generated, resulting in the reduction of the stability of the device. Therefore, it is preferable that the doping concentration of the N-type drift region 21 or the charge storage layer 22 is set to not more than 1×10 ¹⁷ cm ^-3 To ensure the reliability and stability of the device.

Based on this, referring to fig. 11 and 12, fig. 11 is a schematic flow structure diagram of a method for manufacturing a silicon carbide power device 100 provided in the present application, and fig. 12 is a schematic flow step diagram of a method for manufacturing a silicon carbide power device 100 provided in the present application, where the manufacturing method includes:

Step 110: an N-type substrate 10 is provided.

The substrate (substrate) refers to a wafer made of a semiconductor material, and can directly enter a wafer manufacturing production link to produce a semiconductor device, or can be subjected to epitaxial processing to produce an epitaxial wafer, and the N-type substrate 10, i.e., a substrate with a conductivity type of N-type and conducting electricity through electrons, can be obtained by doping pentavalent elements such as phosphorus, arsenic and the like. The N-type substrate 10 used in the present embodiment is preferably a silicon carbide substrate, which may be provided by a wafer manufacturing factory, or may be manufactured by performing single crystal growth and wafer dicing, polishing, and the like on silicon carbide powder by itself, which is not particularly limited in this application. Optionally, wafer cleaning (Wafer cleaning) may be performed after the N-type substrate 10 is obtained, such as chemical cleaning, mechanical cleaning, and thermal treatment, to ensure cleanliness of the Wafer surface, so as to reduce defects and reject rate in subsequent processes, and also to make proper cleaning methods and parameter settings very important, which may damage the substrate surface or introduce new contaminants.

Step 120: an epitaxial layer 20 is formed on the N-type substrate 10.

An Epitaxial Layer (epi Layer), a thin single crystal Layer deposited on a single crystal substrate, forms the epi Layer 20 by Epitaxial growth or deposition on the N-type substrate 10. The epitaxial growth method or deposition method may be physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), molecular beam epitaxy (Molecular Beam Epitaxy, MBE) or liquid phase epitaxy (Liquid Phase Epitaxy, LPE), which is not particularly limited in this application. Preferably, the epitaxial layer 20 and the N-type substrate 10 are of a homogenous silicon carbide material, which allows for a good lattice match between the epitaxial layer 20 and the substrate, thereby reducing defects and stresses, facilitating improved yield in the fabrication of the device, and better performance of the device.

Optionally, the epitaxial layer 20 includes an N-type drift region 21, a P-type polysilicon 80 is in stacked contact with the N-type drift region 21, or the epitaxial layer 20 includes an N-type drift region 21 and a charge storage layer 22 sequentially stacked on an N-type substrate 10, a P-type polysilicon 80 is in stacked contact with the charge storage layer 22, a P-type channel region 30 and an n+ type source region 40 are both located in the charge storage layer 22, and a source trench 50 extends through the charge storage layer 22 to the N-type drift region 21.

The N-type drift region 21 or the charge storage layer 22 is a part of the epitaxial layer 20, and can be obtained by an epitaxial growth method such as solid phase epitaxy or vapor phase epitaxy, and the description thereof is omitted herein.

Step 130: the epitaxial layer 20 is ion implanted to form a P-type channel region 30 in the epitaxial layer 20 and an n+ -type source region 40 in the P-type channel region 30.

Ion Implantation (Ion Implantation) is a doping process in which atoms of impurity elements are ionized to form charged impurity ions, the charged impurity ions are accelerated under a strong electric field, high energy is obtained and then bombarded into corresponding regions of a semiconductor device, and then the impurities are activated through annealing, so that certain impurity distribution is formed in a semiconductor wafer. The P-type channel region 30 formed in this step is obtained by ion implantation doping of trivalent elements such as aluminum, boron and gallium, and the n+ type source region 40 is obtained by ion heavily doping implantation of pentavalent elements such as phosphorus, arsenic and nitrogen.

Step 140: epitaxial layer 20 is etched to form source trenches 50 through N + type source regions 40 and P-type channel regions 30.

Etching (Etch) is a process of selectively removing unwanted material from the wafer surface, either chemically or physically, and is a generic term for stripping and removing material by solution, reactive ions, or other mechanical means. Etching techniques are largely divided into Dry Etching (Dry Etching) and Wet Etching (Wet Etching). The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching. The source trench 50 is preferably formed by etching the n+ type source region 40 and the P type channel region 30 by reactive ion etching, plasma etching or sputter etching using a dry etching method. The source trench 50 extends through the N + type source region 40 and the P-type channel region 30 for subsequent source 91 metallization formation and connection.

Optionally, the source trench 50 includes a first level trench 51 and a second level trench 52 that are arranged in steps, and on the basis of this, optionally, referring to fig. 13, the epitaxial layer 20 is etched, which may be performed as follows:

Step 141: a first level trench 51 is formed through the N + type source region 40 and the P-type channel region 30 by dry etching.

The dry etching is to remove the material by physical or chemical reaction to achieve the purpose of manufacturing the micro-nano structure. In forming the first level trenches 51 through the N + type source regions 40 and the P-type channel regions 30, special care needs to be taken to avoid damaging the crystal structure of the source region channel regions so as not to affect device performance. The dry etching technology can precisely control the etching depth and width by selecting proper reaction gas and process parameters, thereby achieving the fine processing of the P-type channel region 30, and can ensure that the shape, size and depth of the groove meet the design requirements by precisely controlling the etching conditions and parameters. Meanwhile, the dry etching can effectively remove residues generated by etching, and reduce the influence on the subsequent process so as to ensure the smooth progress of the whole manufacturing process.

Step 142: oxide is deposited in the first level trenches 51 to act as a hard mask and etched to form second level trenches 52.

An oxide such as silicon dioxide or the like is deposited in the first level trenches 51 as a hard mask. Then, the second-stage trench 52 is formed by an etching technique under the protection of the oxide mask. In this way, a more complex structure can be manufactured on the surface of the device, namely, the second-stage trench 52 with higher process requirements can be etched, then, the second-stage trench 52 is formed on the oxide mask through an etching technology, in the step, a hard mask and a trench structure with excellent performance can be obtained through precisely controlling the deposition and etching processes, in the etching process of the deep trench of the second stage, attention is paid to the etching depth, the side wall smoothness and the bottom flatness, attention is paid to the etching selectivity and the etching uniformity, the requirements on the process are higher, the current process method can only generally achieve about 3 mu m, but the formed semi-superjunction structure can effectively smooth the electric field inside the device through the subsequent injection of the P+ body region 60, so that the voltage-resistant capability and the conduction efficiency of the device are enhanced, and the reliability and the stability of the device are improved.

Step 150: p+ implantation is performed on the sidewalls of the source trench 50 to form a p+ body region 60.

The p+ implant is also an ion implantation method, and the p+ body 60 is formed by heavily doping the sidewalls of the source trench 50 with an ion implantation of trivalent elements such as aluminum, boron, and gallium. The p+ body region 60 is a P-type region with high doping concentration, and can smooth the electric field distribution in the epitaxial layer 20 during reverse conduction, thereby reducing peak electric field, improving reverse withstand voltage capability of the device, and when forward conduction, the p+ field region is in metal contact with the source 91, so that contact resistance can be reduced, forward conduction performance can be improved, and reliability and stability of the silicon carbide power device 100 can be further improved.

Step 160: a gate 70 and an oxide layer surrounding the gate 70 are disposed in a region of the P-type channel region 30 exposed on the surface of the epitaxial layer 20.

The step of forming the gate oxide layer and the gate 70 material required for the gate 70 on the basis of the foregoing steps, preferably, the step may be specifically to form a field oxide layer under the gate 70 on the basis of the foregoing structure, then perform polysilicon deposition on the gate 70, and finally etch to form the gate 70 morphology and deposit an upper field oxide layer. The morphology of the gate 70, that is, the specific structure and shape of the gate 70 in the fabricated device, after these steps, the lower field oxide layer and the upper field oxide layer form an integral oxide layer made of silicon dioxide, which is used to isolate the gate 70 from the channel and the subsequent metal layers or other material layers, so as to avoid leakage of the current of the gate 70, reduce parasitic capacitance between the gate 70 and other metal layers, and facilitate improvement of the control energy efficiency of the gate 70 and reliability and stability of the device.

The steps of etching and depositing can be referred to as the foregoing steps, and will not be described in detail herein. The oxidation is a step of forming a silicon dioxide film on the surface to prevent impurities from penetrating and diffusing, and the oxidation method mainly comprises a thermal oxidation method and a field oxygen deposition method, wherein the thermal oxidation method is to react a silicon-containing material with an oxygen-containing material at high temperature to form the silicon dioxide film, and the field oxygen deposition is to activate one or more substances of gases on the surface in a certain way by utilizing a chemical vapor deposition technology, so that the silicon dioxide film is formed at a deposition position.

Step 170: a P-type polysilicon 80 is stacked on the epitaxial layer 20, and the P-type polysilicon 80 is adjacent to the gate electrode 70.

This step is to stack P-type polysilicon 80 over epitaxial layer 20 to form the heterojunction diode described previously. The conductivity type of the polysilicon is P-type, and the polysilicon conducts electricity through holes. Preferably, the fabrication process includes CONTACT hole etching followed by deposition and doping of free-wheeling polysilicon. First, contact holes are formed by reactive ion etching or plasma etching for providing contact points with the epitaxial layer 20 or the corresponding P-type channel region 30 or n+ type source region 40 therein for each subsequent electrode and polysilicon layer, thereby achieving connection between the bottom device and the external metal. And then, forming a polysilicon layer through polysilicon deposition, wherein the step is carried out through conventional deposition methods such as chemical vapor deposition or physical vapor deposition, and the like, so that the method has simple process and can generate great benefit, and is beneficial to improving the reliability and stability of the device. After the deposition is completed, the P-type polysilicon 80 is doped to improve the conductivity, and the doping of the P-type polysilicon 80 may be performed by diffusion or ion implantation. If diffusion is used, dopants may be placed on the surface of epitaxial layer 20 after deposition and allowed to diffuse into the polysilicon at high temperatures. If an ion implantation mode is adopted, ions of the dopant can be implanted into the polysilicon, and then the dopant is activated by annealing.

Since the P-type polysilicon 80 is disposed in the middle of the gate 70, the P-type polysilicon 80 has a small effect on the overall area and volume of the device, and the heterojunction diode of the reverse freewheeling formed by the P-type polysilicon 80 and the epitaxial layer 20 can be turned off when the device is turned on in the forward direction, so that electrons reach the drain 92 from the preset channel, and current is passed when the device is turned on in the reverse direction, so that current enters the source 91, thereby realizing the reverse freewheeling effect, reducing loss and improving switching efficiency, and further improving the performance of the silicon carbide power device 100.

Step 180: a source 91 is deposited to fill the source trench 50 and cover the P + body 60, the N + source 40, the gate 70 and the P-type polysilicon 80, and a drain 92 is deposited on the side of the N-type substrate 10 facing away from the epitaxial layer 20.

In the process of manufacturing the silicon carbide power device 100, a metal layer needs to be deposited to achieve the conductive connection and other functions, wherein common metal deposition materials include metal materials such as nickel, chromium, titanium, zirconium and cobalt, or other materials with better electrical conductivity and thermal conductivity obtained by combining the metal materials. Both chemical vapor deposition and physical vapor deposition can be used as a means of depositing metal electrodes. In the embodiment of the invention, the metal electrode is preferably deposited by adopting a chemical vapor deposition method, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like. TiC or TiN is usually deposited by introducing TiCl4, H2, CH4 and other gases into a reaction chamber at 850-1100 ℃ and forming a coating on the surface of the device through chemical reaction, wherein the coating can form good ohmic contact with silicon carbide materials, and finally the deposited source electrode 91 and drain electrode 92 metals have good electrical conductivity and thermal conductivity, so that the reliability and stability of the silicon carbide power device 100 are improved.

Based on the above-described manufacturing methods as illustrated in the steps of fig. 11 to 13, it should be noted that concentration limitation of each layer region is required during the doping process in the preparation of the silicon carbide power device 100, and limitation of width, thickness, depth, etc. of each layer region is required during the steps of deposition, etching, etc., and specific reference may be made to specific limitations in the silicon carbide power device 100 described in fig. 1 to 10, which are not repeated herein. For example, in the doping process, the high-purity doping source can be selected, the doping process and parameter setting can be optimized, the energy and the dosage of doping injection can be controlled, the doping concentration can be monitored and measured in real time, the process parameters can be adjusted in time to ensure the stability of the doping concentration, advanced reaction cavities and control technology can be adopted in the steps of deposition, etching and the like, parameters such as temperature, pressure, gas flow and the like of each layer region can be controlled, and an accurate thickness measuring and monitoring system can be adopted to ensure the accuracy of the width, thickness, depth and the like of each layer region. Meanwhile, the stability of environmental conditions and process parameters needs to be strictly controlled in the whole preparation process, and the influence of various external factors on the device performance is avoided, so that the reliability and stability of the silicon carbide power device 100 are improved.

Unlike the prior art, the application discloses a silicon carbide power device and a manufacturing method thereof. Through set up with the grid adjacent setting and with epitaxial layer range upon range of P type polycrystalline silicon that contacts in carborundum power device to can obtain the freewheel passageway, so that the device can open under lower reverse voltage, and have better breakdown voltage and on resistance compromise effect, realize reverse freewheel, simultaneously, the cost and the technology degree of difficulty of this mode are relatively lower, do not exert an influence under the condition to chip area and forward conduction characteristic, can effectively promote the conduction speed and the switching frequency of device, reduce switching loss, promote switching performance. In addition, the on-resistance can be reduced by epitaxially growing the charge storage layer, and the expansion of the depletion region can be realized by etching the first-stage groove and the second-stage groove which are arranged in a step manner, so that the switching performance of the device is further enhanced, the loss is reduced, and the reliability and the stability of the silicon carbide power device are further improved.

The foregoing description is only exemplary embodiments of the present application and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the present application.

Claims

1. A silicon carbide power device, comprising:

an N-type substrate;

the epitaxial layer is arranged on the N-type substrate, a P-type channel region is formed in the epitaxial layer, an N+ type source region is formed in the P-type channel region, and a source groove is arranged on the epitaxial layer, penetrates through the N+ type source region and the P-type channel region, and a P+ body region is formed on the side wall of the source groove;

the grid electrode is arranged on one side, away from the N-type substrate, of the epitaxial layer and spans the region, exposed on the surface of the epitaxial layer, of the P-type channel region;

p-type polysilicon, which is arranged adjacent to the grid electrode and is in laminated contact with the epitaxial layer;

the source electrode is filled in the source electrode groove and covers the P+ body region, the N+ type source region, the grid electrode and the P type polycrystalline silicon;

and the drain electrode is arranged on one side of the N-type substrate, which is away from the epitaxial layer.

2. The silicon carbide power device of claim 1, wherein the P-type polysilicon has a width of 0.1 to 0.4 μm.

3. The silicon carbide power device of claim 1 or 2, wherein the P-type polysilicon has a doping concentration of 1 x 10 ¹⁹ cm ^-3 The above.

4. The silicon carbide power device of claim 1, wherein the source trench comprises a first level trench and a second level trench arranged in a step configuration, the second level trench being disposed at a bottom of the first level trench, the first level trench passing through the n+ type source region and the P type channel region.

5. The silicon carbide power device of claim 4, wherein the first and second level trenches have a total depth of 1.5 to 4.0 μm.

6. The silicon carbide power device of claim 1, wherein the epitaxial layer includes an N-type drift region, the P-type polysilicon being in stacked contact with the N-type drift region; or (b)

The epitaxial layer comprises an N-type drift region and a charge storage layer which are sequentially stacked on the N-type substrate, the P-type polysilicon is in stacked contact with the charge storage layer, the P-type channel region and the N+ type source region are both located on the charge storage layer, and the source trench penetrates through the charge storage layer and extends to the N-type drift region.

7. The silicon carbide power device of claim 6, whereinThe P-type polysilicon is in laminated contact with the N-type drift region, and the doping concentration of the N-type drift region is not more than 1×10 ¹⁷ cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the Or (b)

The P-type polysilicon is in laminated contact with the charge storage layer, and the doping concentration of the charge storage layer is not more than 1×10 ¹⁷ cm ^-3 。

8. A method of fabricating a silicon carbide power device, comprising:

providing an N-type substrate;

forming an epitaxial layer on the N-type substrate;

ion implantation is carried out on the epitaxial layer so as to form a P-type channel region in the epitaxial layer and an N+ type source region in the P-type channel region;

etching the epitaxial layer to form a source trench penetrating through the N+ type source region and the P type channel region;

p+ implantation is conducted on the side wall of the source electrode groove so as to form a P+ body region;

setting a grid electrode in a region, exposed on the surface of the epitaxial layer, of the P-type channel region and an oxide layer wrapping the grid electrode;

a P-type polysilicon layer is arranged on the epitaxial layer in a stacked mode, and the P-type polysilicon layer is adjacent to the grid electrode;

and depositing a source electrode to fill the source electrode groove and cover the P+ body region, the N+ type source region, the grid electrode and the P type polycrystalline silicon, and depositing a drain electrode on one side of the N type substrate, which is far away from the epitaxial layer.

9. The method of fabricating a silicon carbide power device according to claim 8, wherein the epitaxial layer comprises an N-type drift region, the P-type polysilicon being in stacked contact with the N-type drift region; or (b)

10. The method for manufacturing a silicon carbide power device according to claim 8, wherein the source trench includes a first level trench and a second level trench arranged in a step, and the etching the epitaxial layer includes:

forming the first-stage groove passing through the N+ type source region and the P type channel region by dry etching;

and depositing oxide on the first-stage groove to be used as a hard mask, and etching to form the second-stage groove.