CN114744037A - Shielding gate groove type field effect transistor with variable doping concentration structure and preparation method thereof - Google Patents
Shielding gate groove type field effect transistor with variable doping concentration structure and preparation method thereof Download PDFInfo
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- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The application relates to a shielded gate trench field effect transistor with a variable doping concentration structure, which comprises: the transistor comprises a substrate region, a drift region, a base region, a source region, a groove region, a drain electrode and a source electrode; the groove region comprises a shielding grid, a control grid, an insulating layer and a metal grid; the shielding grid and the drift region are of variable doping concentration structures, the doping concentration of the drift region is gradually reduced from top to bottom, and the doping concentration of the shielding grid is gradually reduced from top to bottom. When the transistor is forward blocking, the electric field between the third level drift region and the corner of the trench region is weakened. Therefore, the shielded gate trench type field effect transistor with the variable doping concentration structure shown in the embodiment of the application can balance the peak electric field of the voltage-withstanding layer at the interface of the base region and the drift region, so that the peak value of the electric field is improved, the breakdown voltage is improved, and the specific on-resistance is reduced.
Description
Technical Field
The application relates to the technical field of power semiconductor devices, in particular to a shielded gate trench type field effect transistor with a variable doping concentration structure and a preparation method thereof.
Background
Shielded Gate Trench field effect transistors (SGTs) have been widely used in important low voltage fields such as power management. SGT has high channel density and simultaneously has better charge compensation effect. In addition, the shielding gate structure effectively isolates the coupling between the control gate and the drain, thereby remarkably reducing the transmission capacitance.
Therefore, the SGT has lower specific on resistance, smaller on loss and switching loss and higher operating frequency.
In the SGT device, due to the electric field concentration effect and the high polysilicon doping concentration of the shielding gate, when the SGT device is blocked in the forward direction, the electric charge flux emitted by the ionized donors in the voltage-withstanding region is concentrated at the corner of the shielding gate in the trench region, so that the peak voltage borne at the corner of the shielding gate in the trench region is higher, and the shielding gate in the trench region is also easily broken down at the corner.
Therefore, in the SGT device, in order to improve the voltage endurance capability at the corner of the trench-shielded gate, it is necessary to design a new type of shielded gate trench field effect transistor.
Disclosure of Invention
To overcome the problems in the related art, the present application provides a shielded gate trench field effect transistor with a variable doping concentration structure, comprising:
the transistor comprises a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a drain electrode 6 and a source electrode 7;
the drift region is connected with the substrate region, the direction of the substrate region pointing to the drift region is taken as the upper direction, and the base region and the source region are sequentially arranged above the drift region; the drift region is a variable doping concentration structure with the doping concentration gradually reduced from top to bottom; the drift region includes: the first-stage drift region, the second-stage drift region and the third-stage drift region; the doping concentration of the first-stage drift region is high doping concentration, the doping concentration of the second-stage drift region is medium doping concentration, and the doping concentration of the third-stage drift region is low doping concentration;
the groove region is arranged on the side of the substrate region and is respectively connected with the drift region, the substrate region and the source region;
the groove region comprises a shielding grid, a control grid, an insulating layer and a metal grid; the control grid and the shielding grid are sequentially arranged in the groove region from top to bottom and are separated by the insulating layer; the control grid is respectively connected with the base region and the source region through the insulating layer, and the shielding grid is connected with the drift region through the insulating layer;
the shielding grid is a variable doping concentration structure with the doping concentration gradually reduced from top to bottom;
the source region consists of an N-type source region and a P-type source region; the P-type source region, the N-type source region and the trench region are sequentially arranged along the top surface of the substrate region, and the N-type source region is connected with the control gate through the insulating layer;
the source electrode is arranged above the source region.
In one embodiment, the shielding grids comprise a first-stage shielding grid, a second-stage shielding grid and a third-stage shielding grid;
the doping concentration of the first-stage shielding grid is high; the doping concentration of the second-stage shielding grid is medium doping concentration; and the doping concentration of the third-stage shielding grid is low.
In one embodiment, the trench region further comprises: a Schottky metal layer; the Schottky metal layer is arranged below the shielding grid.
In one embodiment, the direction in which the substrate region points to the drift region is taken as a height direction; the top surface and the bottom surface of the first-level drift region are respectively positioned on the same height plane with the top surface and the bottom surface of the first-level shielding grid;
the top surface and the bottom surface of the second-level drift region are respectively positioned on the same height plane with the top surface and the bottom surface of the second-level shielding grid; and the top surface and the bottom surface of the third-stage drift region are respectively positioned on the same height plane with the top surface and the bottom surface of the third-stage shielding grid.
In one embodiment, the doping concentrations of the P-type source region and the N-type source region are both heavy doping concentrations.
In one embodiment, the doping type of the substrate region is N-type doping, and the doping concentration of the substrate region is heavily doped concentration; the doping type of the drift region is N-type doping; the doping type of the substrate region is P-type doping, and the doping concentration of the substrate region is medium doping concentration; the doping concentration of the source region is heavy doping concentration; the doping concentration of the control gate is heavy doping concentration.
A second aspect of the present application provides a method for manufacturing a shielded gate trench field effect transistor with a variable doping concentration structure, for manufacturing the shielded gate trench field effect transistor with the variable doping concentration structure according to the first aspect of the present application, including:
preparing a substrate region with a semiconductor material;
forming a first-level drift region, a second-level drift region and a third-level drift region on the substrate region in sequence through epitaxy; the doping concentration of the first-stage drift region is low doping concentration, the doping concentration of the second-stage drift region is medium doping concentration, and the doping concentration of the third-stage drift region is high doping concentration;
forming a base region on the drift region in an ion implantation or diffusion mode;
etching a groove on the side face of the drift region;
depositing an oxide, polysilicon, an oxide, polysilicon and an oxide in the trench in sequence to form an insulating layer, a shielding gate and a control gate; the shielding grid is of a variable doping concentration structure; the doping concentration of the shielding grid is gradually decreased from top to bottom;
forming a source region on the base region;
depositing metal on the source region to form a source electrode;
a drain is formed under the substrate region.
In one embodiment, the sequentially depositing oxide, polysilicon, oxide, polysilicon and oxide in the trench to form the insulating layer, the shielding gate and the control gate includes:
depositing an oxide, polysilicon, an oxide and polysilicon in the trench in sequence to form an insulating layer, a first-stage shielding gate, a second-stage shielding gate, a third-stage shielding gate and a control gate respectively; the doping concentration of the first-stage shielding grid is high doping concentration, the doping concentration of the second-stage shielding grid is medium doping concentration, and the doping concentration of the third-stage shielding grid is low doping concentration.
In one embodiment, before sequentially depositing an oxide, a polysilicon, an oxide, a polysilicon and an oxide in the trench and forming the insulating layer, the shield gate and the control gate, the method includes:
and depositing metal in the groove to form a Schottky metal layer.
The technical scheme provided by the application can comprise the following beneficial effects:
in the embodiment of the application, the shielding grid and the drift region are of variable doping concentration structures, the doping concentration of the drift region is gradually reduced from top to bottom, and the doping concentration of the shielding grid is gradually reduced from top to bottom. The drift region is composed of a first-stage drift region, a second-stage drift region and a third-stage drift region, wherein the doping concentration of the first-stage drift region, the second-stage drift region and the third-stage drift region is gradually reduced from top to bottom. Therefore, the third-level drift region with low doping concentration corresponds to the position of the shielding grid on the same height. When the transistor is forward blocking, the electric field between the third level drift region and the corner of the trench region is weakened. Therefore, the shielded gate trench type field effect transistor with the variable doping concentration structure shown in the embodiment of the application can balance the peak electric field of the voltage-withstanding layer at the interface of the base region and the drift region, so that the peak value of the electric field is improved, the breakdown voltage is improved, and the specific on-resistance is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the application.
Fig. 1 is a schematic structural diagram of a shielded gate trench field effect transistor with a variable doping concentration structure according to an embodiment of the present application;
fig. 2 is a schematic flowchart of a method for manufacturing a shielded gate trench field effect transistor with a variable doping concentration structure according to an embodiment of the present application;
fig. 3 is another schematic flow chart of a manufacturing method of a shielded gate trench field effect transistor with a variable doping concentration structure according to an embodiment of the present application.
Detailed Description
Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Example one
In the SGT device, because the doping concentration of the shield gate drift region is high, when the SGT device is subjected to forward blocking, a depletion region is formed between the interface of the drift region and the base region, and the depletion region has a spike electric field. The peak electric field may cause breakdown at the corner between the trench region and the drift region due to electric field concentration effects.
Therefore, in order to balance the peak electric field of the depletion region, the electric field peak is improved, the breakdown voltage is increased, and the specific on-resistance is reduced. The embodiment of the application provides a shielded gate trench type field effect transistor with a variable doping concentration structure.
Fig. 1 is a schematic structural diagram of a shielded gate trench field effect transistor with a variable doping concentration structure according to an embodiment of the present application.
Referring to fig. 1, a shielded gate trench field effect transistor with a variable doping concentration structure according to an embodiment of the present application includes:
the transistor comprises a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a drain electrode 6 and a source electrode 7;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction, and the base region 3 and the source region 4 are sequentially arranged above the drift region 2; the drift region 2 is a variable doping concentration structure with the doping concentration gradually reduced from top to bottom; the drift region 2 includes: a first-level drift region 21, a second-level drift region 22, and a third-level drift region 23; the doping concentration of the first-stage drift region 21 is high doping concentration, the doping concentration of the second-stage drift region 22 is medium doping concentration, and the doping concentration of the third-stage drift region 23 is low doping concentration;
the groove region 5 is arranged on the side of the substrate region 3 and is respectively connected with the drift region 2, the substrate region 3 and the source region 4;
the trench region 5 comprises a shielding grid 51, a control grid 52, an insulating layer 53 and a metal grid; the control gate 52 and the shielding gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the body region 3 and the source region 4 through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;
the shielding gate 51 is a variable doping concentration structure with the doping concentration gradually reduced from top to bottom;
the source region 4 consists of an N-type source region 41 and a P-type source region 42; the P-type source region 42, the N-type source region 41 and the trench region 5 are sequentially arranged along the top surface of the body region 3, and the N-type source region 41 is connected to the control gate through the insulating layer 53;
the source 7 is disposed above the source region 4.
In the embodiment of the present application, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavy doping concentration; the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is light doping concentration; the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration; the doping concentration of the source region 4 is heavy doping concentration; the doping concentration of the control gate 52 is heavy doping concentration, and the doping type of the control gate 52 is P-type or N-type doping.
In the embodiment of the present application, the value range of the light doping concentration is 1 × 1015cm-3To 5X 1016cm-3(ii) a The value range of the medium doping concentration is 1 multiplied by 1017cm-3To 5X 1018cm-3(ii) a The value range of the heavy doping concentration is 1 multiplied by 1019cm-3To 5X 1020cm-3。
In the embodiment of the present application, the doping type of the shielding gate is P-type doping or N-type doping.
Further, the doping concentration of the doping type of the shielding gate may be a heavily doped concentration or a medium doped concentration.
To reduce the peak electric field between the trench regions and the corners between the drift regions.
In the embodiment of the application, the shielding gate and the drift region are of variable doping concentration structures, the doping concentration of the drift region is gradually reduced from top to bottom, and the doping concentration of the shielding gate is gradually reduced from top to bottom. The drift region is composed of a first-stage drift region, a second-stage drift region and a third-stage drift region, wherein the doping concentration of the first-stage drift region, the second-stage drift region and the third-stage drift region is gradually reduced from top to bottom. Therefore, the third-level drift region with low doping concentration corresponds to the position of the shielding grid on the same height. When the transistor is forward blocking, the electric field between the third level drift region and the corner of the trench region is weakened.
Therefore, the shielded gate trench type field effect transistor with the variable doping concentration structure shown in the embodiment of the application can balance the peak electric field of the voltage-withstanding layer at the interface of the base region and the drift region, so that the peak value of the electric field is improved, the breakdown voltage is improved, and the specific on-resistance is reduced.
Example two
In the SGT device, due to the electric field concentration effect and the fact that the polycrystalline silicon doping concentration of the shielding gate is high, when the SGT device is blocked in the forward direction, parasitic capacitance formed between the shielding gate and a substrate region is large, and the switching speed of a transistor is reduced.
Therefore, in order to improve the voltage endurance of the SGT device, the electric field strength at the corners of the trench shielding gate needs to be weakened. The embodiment of the application provides a shielded gate trench type field effect transistor with a variable doping concentration structure.
Fig. 1 is a schematic structural diagram of a shielded gate trench field effect transistor with a variable doping concentration structure according to an embodiment of the present application.
Referring to fig. 1, a shielded gate trench field effect transistor of a variable doping concentration structure according to an embodiment of the present application includes:
the transistor comprises a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a drain electrode 6 and a source electrode 7;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction, and the base region 3 and the source region 4 are sequentially arranged above the drift region 2; the drift region 2 is a variable doping concentration structure with the doping concentration gradually reduced from top to bottom; the drift region 2 includes: a first-level drift region 21, a second-level drift region 22 and a third-level drift region 23; the doping concentration of the first-stage drift region 21 is high doping concentration, the doping concentration of the second-stage drift region 22 is medium doping concentration, and the doping concentration of the third-stage drift region 23 is low doping concentration;
the groove region 5 is arranged on the side of the substrate region 3 and is respectively connected with the drift region 2, the substrate region 3 and the source region 4;
the trench region 5 comprises a shielding grid 51, a control grid 52, an insulating layer 53 and a metal grid; the control gate 52 and the shielding gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the body region 3 and the source region 4 through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;
the shielding gate 51 is a variable doping concentration structure with the doping concentration gradually reduced from top to bottom;
the source region 4 consists of an N-type source region 41 and a P-type source region 42; the P-type source region 42, the N-type source region 41 and the trench region 5 are sequentially arranged along the top surface of the body region 3, and the N-type source region 41 is connected to the control gate through the insulating layer 53;
the source 7 is disposed above the source region 4.
In the embodiment of the present application, the shielding gate 51 includes: a first-stage shield grid 510, a second-stage shield grid 511 and a third-stage shield grid 512;
the doping concentration of the first-stage shielding gate 510 is low; the doping concentration of the second-stage shielding grid 511 is a medium doping concentration; the doping concentration of the third-stage shielding gate 512 is high.
In the embodiment of the present application, the third-stage shielding gate is disposed at the bottom of the shielding gate, near the substrate region, and the doping concentration of the third-stage shielding gate is a high doping concentration.
Further, the trench region 5 further includes: a Schottky metal layer 54; the schottky metal layer 54 is disposed below the shield gate.
In the embodiment of the present application, the top surface and the bottom surface of the first-level drift region 21 are located on the same height plane as the top surface and the bottom surface of the first-level shielding gate 510, respectively;
the top surface and the bottom surface of the second-stage drift region 22 are respectively positioned on the same height plane with the top surface and the bottom surface of the second-stage shielding gate 511; the top surface and the bottom surface of the third-stage drift region 23 are located on the same height plane as the top surface and the bottom surface of the third-stage shielding grid 512, respectively.
Therefore, when the transistor is in forward blocking, the third stage shielding grid is easier to be depleted under the same applied voltage, and the width of a depletion layer is thicker. Therefore, the parasitic capacitance formed between the third-stage shielding gate and the substrate region is smaller, the parasitic capacitance formed between the shielding gate and the substrate region is weakened, and the switching speed of the device is further improved.
EXAMPLE III
Corresponding to the shielded gate trench field effect transistor with the variable doping concentration structure in the first embodiment, the application also provides a manufacturing method of the shielded gate trench field effect transistor with the variable doping concentration structure and a corresponding embodiment.
Fig. 2 is a schematic flowchart of a manufacturing method of a shielded gate trench field effect transistor with a variable doping concentration structure according to an embodiment of the present application.
As shown in fig. 2, a method for manufacturing a shielded gate trench field effect transistor according to an embodiment of the present application includes the following steps:
201. preparing a substrate region with a semiconductor material;
in the embodiment of the present application, the substrate region is made of an N-type heavily doped semiconductor material, that is, the doping type of the substrate region is N-type doping, and the doping concentration of the substrate region is a heavily doped concentration.
202. Forming a first-level drift region, a second-level drift region and a third-level drift region on the substrate region in sequence through epitaxy;
in this embodiment, the doping concentration of the first-stage drift region is a low doping concentration, the doping concentration of the second-stage drift region is a medium doping concentration, and the doping concentration of the third-stage drift region is a high doping concentration.
In the embodiment of the present application, different epitaxy processes may be adopted according to actual requirements, including but not limited to: vapor Phase Epitaxy (VPE) or Chemical Vapor Deposition (CVD).
203. Forming a base region on the drift region in an ion implantation or diffusion mode;
the ion implantation process is a process of doping silicon materials, in the practical application process, a power device product is placed at one end of an ion implanter, and a doping ion source is arranged at the other end of the ion implanter. At one end of the doping ion source, doping body atoms are ionized to carry certain charges, the charges are added to the super high speed by an electric field, penetrate through the surface layer of a product, and are injected into a power device by utilizing momentum of the atoms to form a doping area.
The diffusion process is a process of doping pure impurity atoms on the surface of the silicon material, and in the practical application process, diborane or phosphine is usually used as an ion source, and the pure impurity atoms are doped on the surface of the silicon material by adopting an intermittent diffusion or displacement diffusion mode.
It should be noted that, in the embodiments of the present application, the preparation method adopted for the substrate region is not strictly limited, and in an actual process, the preparation of the substrate region may be completed by selecting the above different processes according to actual requirements.
204. Etching a groove on the side face of the drift region;
in the embodiment of the application, a trench is etched on one side of the drift region through a photoetching process, and the residual photoresist is removed through wet etching or dry etching.
205. Depositing oxide, polysilicon, oxide, polysilicon and oxide in the trench in sequence to form an insulating layer, a shielding gate and a control gate;
preferably, in this embodiment of the present application, an oxide, a heavily doped polysilicon, an oxide, and a heavily doped polysilicon are sequentially deposited in the trench to form the shield gate, the insulating layer, and the control gate.
In the embodiment of the present application, the doping concentration of the shielding gate decreases gradually from top to bottom, that is, the doping concentration of the portion of the shielding gate close to the control gate is the lowest, and the doping concentration of the portion of the shielding gate close to the substrate region is the highest.
206. Forming a source region on the base region;
207. depositing metal on the source region to form a source electrode;
208. a drain is formed under the substrate region.
To reduce the peak electric field between the corners between the trench region and the drift region.
In the embodiment of the application, the shielding gate and the drift region are of variable doping concentration structures, the doping concentration of the drift region is gradually reduced from top to bottom, and the doping concentration of the shielding gate is gradually reduced from top to bottom. The drift region is composed of a first-stage drift region, a second-stage drift region and a third-stage drift region, wherein the doping concentration of the first-stage drift region, the second-stage drift region and the third-stage drift region is gradually reduced from top to bottom. Therefore, the third-level drift region with low doping concentration corresponds to the position of the shielding grid on the same height. When the transistor is forward blocking, the electric field between the third level drift region and the corner of the trench region is weakened.
Therefore, the shielded gate trench type field effect transistor with the variable doping concentration structure shown in the embodiment of the application can balance the peak electric field of the voltage-withstanding layer at the interface of the base region and the drift region, so that the peak value of the electric field is improved, the breakdown voltage is improved, and the specific on-resistance is reduced.
Example four
Corresponding to the shielded gate trench field effect transistor with the variable doping concentration structure shown in the second embodiment, the application also provides a preparation method of the shielded gate trench field effect transistor with the variable doping concentration structure and a corresponding embodiment.
Fig. 3 is a schematic flowchart of a method for manufacturing a shielded gate trench field effect transistor with a variable doping concentration structure according to an embodiment of the present application.
As shown in fig. 3, the method comprises the following steps:
301. preparing a substrate region with a semiconductor material;
302. a first-stage drift region, a second-stage drift region and a third-stage drift region are formed on the substrate region in an epitaxial mode in sequence;
303. forming a base region on the drift region in an ion implantation or diffusion mode;
304. etching a groove on the side face of the drift region;
305. depositing metal in the groove to form a Schottky metal layer;
306. depositing an oxide, polysilicon, an oxide and polysilicon in the trench in sequence to form an insulating layer, a first-stage shielding gate, a second-stage shielding gate, a third-stage shielding gate and a control gate respectively;
in this embodiment, the doping concentration of the first-stage shielding gate is a high doping concentration, the doping concentration of the second-stage shielding gate is a medium doping concentration, and the doping concentration of the third-stage shielding gate is a low doping concentration.
307. Forming a source region on the substrate region;
308. depositing metal on the source region to form a source electrode;
309. a drain is formed under the substrate region.
In the embodiment of the present application, the top surface and the bottom surface of the first-level drift region are respectively located on the same height plane as the top surface and the bottom surface of the first-level shielding gate;
the top surface and the bottom surface of the second-level drift region are respectively positioned on the same height plane with the top surface and the bottom surface of the second-level shielding grid; and the top surface and the bottom surface of the third-stage drift region are respectively positioned on the same height plane with the top surface and the bottom surface of the third-stage shielding grid.
Therefore, when the transistor is in forward blocking, the third stage shielding grid is easier to be depleted under the same applied voltage, and the width of a depletion layer is thicker. Therefore, the parasitic capacitance formed between the third-stage shielding gate and the substrate region is smaller, the parasitic capacitance formed between the shielding gate and the substrate region is weakened, and the switching speed of the device is further improved.
Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (9)
1. A shielded gate trench field effect transistor of variable doping concentration structure comprising:
the transistor comprises a substrate region (1), a drift region (2), a base region (3), a source region (4), a trench region (5), a drain electrode (6) and a source electrode (7);
the drift region (2) is connected with the substrate region (1), the direction of the substrate region (1) pointing to the drift region (2) is taken as the upper direction, and the base region (3) and the source region (4) are sequentially arranged above the drift region (2); the drift region (2) is a variable doping concentration structure with the doping concentration gradually reduced from top to bottom; the drift region (2) comprises: a first-level drift region (21), a second-level drift region (22) and a third-level drift region (23); the doping concentration of the first-stage drift region (21) is high doping concentration, the doping concentration of the second-stage drift region (22) is medium doping concentration, and the doping concentration of the third-stage drift region (23) is low doping concentration;
the groove region (5) is arranged on the side of the substrate region (3) and is respectively connected with the drift region (2), the substrate region (3) and the source region (4);
the trench region (5) comprises a shielding gate (51), a control gate (52), an insulating layer (53) and a metal gate; the control grid (52) and the shielding grid (51) are sequentially arranged in the trench region (5) from top to bottom and are separated by the insulating layer (53); the control grid (52) is respectively connected with the base region (3) and the source region (4) through the insulating layer (53), and the shielding grid (51) is connected with the drift region (2) through the insulating layer (53);
the shielding grid (51) is a variable doping concentration structure with the doping concentration gradually reduced from top to bottom;
the source region (4) consists of an N-type source region (41) and a P-type source region (42); the P-type source region (42), the N-type source region (41) and the trench region (5) are sequentially arranged along the top surface of the base region (3), and the N-type source region (41) is connected with the control gate through the insulating layer (53);
the source electrode (7) is arranged above the source region (4).
2. The shielded gate trench field effect transistor of variable doping concentration structure of claim 1,
the shielding grids (51) comprise a first-stage shielding grid (510), a second-stage shielding grid (511) and a third-stage shielding grid (512);
the doping concentration of the first-stage shielding grid (510) is low; the doping concentration of the second-stage shielding grid (511) is medium doping concentration; the doping concentration of the third-stage shielding grid (512) is high.
3. The shielded gate trench field effect transistor of variable dopant concentration configuration as claimed in claim 1, wherein said trench region (5) further comprises: a Schottky metal layer (54);
the Schottky metal layer (54) is arranged below the shielding grid.
4. The variable dopant concentration structure shielded gate trench field effect transistor of claim 3,
taking the direction of the substrate region (1) pointing to the drift region (2) as the height direction;
the top surface and the bottom surface of the first-level drift region (21) are respectively positioned on the same height plane with the top surface and the bottom surface of the first-level shielding grid (510);
the top surface and the bottom surface of the second-stage drift region (22) are respectively positioned on the same height plane with the top surface and the bottom surface of the second-stage shielding grid (511); the top surface and the bottom surface of the third-stage drift region (23) are respectively positioned on the same height plane with the top surface and the bottom surface of the third-stage shielding grid (512).
5. The shielded gate trench field effect transistor with the variable doping concentration structure of claim 1, wherein the doping concentrations of the P-type source region (42) and the N-type source region (41) are both heavy doping concentrations.
6. The shielded gate trench field effect transistor of variable doping concentration structure as claimed in claim 1, wherein the doping type of the substrate region (1) is N-type doping, and the doping concentration of the substrate region (1) is heavily doped concentration;
the doping type of the drift region (2) is N-type doping;
the doping type of the substrate region (3) is P-type doping, and the doping concentration of the substrate region (3) is medium doping concentration;
the doping concentration of the source region (4) is heavy doping concentration; the doping concentration of the control gate (52) is a heavy doping concentration.
7. A method for manufacturing a variable doping concentration structure shielded gate trench type field effect transistor, which is used for manufacturing the variable doping concentration structure shielded gate trench type field effect transistor as claimed in any one of claims 1 to 6, comprises the following steps:
preparing a substrate region with a semiconductor material;
a first-stage drift region, a second-stage drift region and a third-stage drift region are formed on the substrate region in an epitaxial mode in sequence; the doping concentration of the first-stage drift region is low doping concentration, the doping concentration of the second-stage drift region is medium doping concentration, and the doping concentration of the third-stage drift region is high doping concentration;
forming a base region on the drift region in an ion implantation or diffusion mode;
etching a groove on the side face of the drift region;
depositing oxide, polysilicon, oxide, polysilicon and oxide in the trench in sequence to form an insulating layer, a shielding gate and a control gate; the shielding grid is of a variable doping concentration structure; the doping concentration of the shielding grid is gradually decreased from top to bottom;
forming a source region on the base region;
depositing metal on the source region to form a source electrode;
a drain is formed under the substrate region.
8. The shielded gate trench field effect transistor with variable doping concentration structure of claim 7 wherein depositing oxide, polysilicon, oxide, polysilicon and oxide in sequence in the trench to form the insulating layer, the shielded gate and the control gate comprises:
depositing an oxide, polysilicon, an oxide and polysilicon in the trench in sequence to form an insulating layer, a first-stage shielding gate, a second-stage shielding gate, a third-stage shielding gate and a control gate respectively; the doping concentration of the first-stage shielding grid is high doping concentration, the doping concentration of the second-stage shielding grid is medium doping concentration, and the doping concentration of the third-stage shielding grid is low doping concentration.
9. The method for manufacturing a shielded gate trench field effect transistor with a variable doping concentration structure according to claim 8, wherein before depositing an oxide, a polysilicon, an oxide, a polysilicon and an oxide in the trench in sequence to form an insulating layer, a shielded gate and a control gate, the method comprises:
and depositing metal in the groove to form a Schottky metal layer.
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| CN202210192925.5A CN114744037A (en) | 2022-02-28 | 2022-02-28 | Shielding gate groove type field effect transistor with variable doping concentration structure and preparation method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117038708A (en) * | 2023-09-28 | 2023-11-10 | 绍兴中芯集成电路制造股份有限公司 | Trench type field effect transistor and preparation method thereof |
| CN117423749A (en) * | 2023-12-19 | 2024-01-19 | 山东大学 | SiC MOSFET device capable of improving short circuit capability |
| WO2024021336A1 (en) * | 2022-07-26 | 2024-02-01 | 苏州大学 | Non-uniformly doped field effect transistor device |
| CN117525157A (en) * | 2024-01-08 | 2024-02-06 | 通威微电子有限公司 | Double-channel groove device and manufacturing method thereof |
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2022
- 2022-02-28 CN CN202210192925.5A patent/CN114744037A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024021336A1 (en) * | 2022-07-26 | 2024-02-01 | 苏州大学 | Non-uniformly doped field effect transistor device |
| CN117038708A (en) * | 2023-09-28 | 2023-11-10 | 绍兴中芯集成电路制造股份有限公司 | Trench type field effect transistor and preparation method thereof |
| CN117038708B (en) * | 2023-09-28 | 2024-01-23 | 绍兴中芯集成电路制造股份有限公司 | Trench type field effect transistor and preparation method thereof |
| CN117423749A (en) * | 2023-12-19 | 2024-01-19 | 山东大学 | SiC MOSFET device capable of improving short circuit capability |
| CN117423749B (en) * | 2023-12-19 | 2024-03-05 | 山东大学 | SiC MOSFET device capable of improving short circuit capability |
| CN117525157A (en) * | 2024-01-08 | 2024-02-06 | 通威微电子有限公司 | Double-channel groove device and manufacturing method thereof |
| CN117525157B (en) * | 2024-01-08 | 2024-03-22 | 通威微电子有限公司 | Double-channel groove device and manufacturing method thereof |
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