WO2024021336A1

WO2024021336A1 - Non-uniformly doped field effect transistor device

Info

Publication number: WO2024021336A1
Application number: PCT/CN2022/127848
Authority: WO
Inventors: 王明湘; 郭烨烨; 张冬利; 王槐生
Original assignee: 苏州大学
Priority date: 2022-07-26
Filing date: 2022-10-27
Publication date: 2024-02-01
Also published as: CN116825820A

Abstract

Disclosed in the present application is a non-uniformly doped field effect transistor device, which is used for solving the problem of the short-channel effect of a field effect transistor in the prior art. The field effect transistor device is configured in such a way that: when the device is turned on, formed in a channel region are an effective channel and an equivalent source region and/or an equivalent drain region which are/is at least away from the effective channel in the thickness direction of the channel region and, in the field effect transistor device, a source region and a drain region are communicated with each other by means of the effective channel, the equivalent source region and the equivalent drain region so as to provide a working current. In the direction in which the channel region is close to the effective channel, the doping concentration of at least part of a first region is gradually decreased, and/or the doping concentration of at least part of a second region is gradually increased, and/or the doping concentration of at least part of a third region is gradually decreased; and/or, in the direction from the source region to the drain region, the doping concentration of at least part of the third region is gradually decreased.

Description

Non-uniformly doped field effect transistor devices

This application claims priority to the Chinese patent application with the application number 2022108875947 and the invention name "Non-uniformly Doped Field Effect Transistor Device" submitted to the China Patent Office on July 26, 2022. The entire content of the application is incorporated by reference in in this article.

Technical field

The invention specifically relates to a non-uniformly doped field effect transistor device and belongs to the technical field of semiconductor devices.

Background technique

With the development of integrated circuit technology, the gate length (corresponding to the channel length) of field effect transistors is constantly shrinking. Currently, VLSI chips based on submicron or even sub-10 nanometer gate length devices have been mass-produced. For such small-size devices, how to deal with their short channel effects is an important challenge for device technology. The short channel effect causes the overall degradation of the threshold voltage and sub-threshold characteristics of small-size devices. Specifically, the threshold voltage of the device is no longer constant, but decreases with the decrease of the channel length, and increases with the increase of the drain terminal voltage of the device. Reduced; the sub-threshold swing of the device transfer characteristics is also degraded.

Current methods to improve the short channel effect of field effect transistor devices mainly include fin field effect transistors FinFET, silicon on insulator SOI, lightly doped drain (LDD) structure and metal source drain Schottky barrier transistor (SB MOSFET), etc. . ①The channel area of FinFET is a 3D fin-shaped sheet, and the gate is a three-sided gate structure. The two side gates enhance the control of the channel by the gate and effectively suppress the short channel effect. The device preparation process in this solution is relatively planar. Type devices are much more complex. Currently, chips with technology nodes below 22nm mostly use FinFET solutions. ②SOI technology introduces a buried oxide layer between the silicon channel layer and the backing substrate, which can effectively suppress the leakage current between the source and drain under the condition that the channel layer is very thin and fully depleted. The difficulty of this solution lies in the SOI silicon The cost of the chip is very high, and chips based on the 10-nanometer technology node based on the SOI solution have also been mass-produced. ③The lightly doped drain LDD is placed near the drain channel and the source and drain regions far away from the channel are still heavily doped. The drain PN junction formed by the lightly doped region reduces the influence of the drain voltage on the channel. It is the mainstream technical solution for sub-micron short-channel devices. In this solution, the on-state current and field-effect mobility of the device are reduced to a certain extent due to the influence of LDD. ④The operating current of the Schottky barrier transistor is the tunneling current of the Schottky barrier between the metal source and the semiconductor channel, which is insensitive to the short channel effect. The process of this solution is relatively difficult, and the selection of barrier materials is limited. And it is difficult to take into account the suppression of the off-state current of the device.

On the other hand, the kink effect appearing on the output characteristic curve of short-channel devices has also received a lot of attention. When the device works in a saturated operating state, the higher drain voltage depletes the drain end of the device and forms a high electric field area, where carriers are prone to collision ionization effects and are coupled and amplified with the parasitic bipolar transistor of the MOS device. , causing the drain current to increase rapidly as the drain voltage increases, forming a so-called kink current. The output characteristic curve of the device is greatly warped, seriously affecting the normal output characteristics.

Commonly used methods to improve the kink effect mainly include increasing the device channel length and lightly doped drain (LDD) structures. Increasing the channel length can reduce the impact of carriers generated by collision ionization at the drain end on the source end, weaken the parasitic transistor effect and alleviate the kink effect. However, increasing the channel length will correspondingly reduce the output current of the device. The LDD structure can reduce the peak electric field intensity in the drain depletion region and weaken the carrier collision ionization effect, thereby suppressing the kink effect. However, the LDD structure will introduce additional parasitic resistance and reduce the field effect mobility and on-state current of the device. .

Contents of the invention

The purpose of this application is to provide a field effect transistor device that is used to solve the problem of short channel effect of field effect transistors in the prior art.

In order to achieve the above object, the present application provides a non-uniformly doped field effect transistor device, including an active layer. The active layer includes a source region, a drain region, and a semiconductor device located between the source region and the drain region. channel area between;

When the device is turned on, an effective channel is formed in the channel region, and an equivalent source region and/or an equivalent drain region that is at least far away from the effective channel in the thickness direction of the channel region, said The field effect transistor device connects the source region and the drain region through the effective channel, equivalent source region and equivalent drain region to contribute operating current;

Wherein, in the direction in which the channel region is close to the effective channel:

The doping concentration of at least part of the first region gradually decreases; and/or,

The doping concentration in at least part of the second region gradually increases; and/or,

The doping concentration of at least part of the third region gradually decreases; and/or,

In the direction from the source region to the drain region:

The doping concentration of at least part of the third region gradually decreases;

The first region is a region in the channel region corresponding to the equivalent source region, the second region is a region in the channel region corresponding to the equivalent drain region, and the third region is the The area in the channel region corresponding to the effective channel.

In one embodiment, in the direction in which the channel region is close to the effective channel:

The doping concentration in the third region and the first region gradually decreases, and the doping concentration in the second region gradually increases; or,

The doping concentration in the third region and the first region gradually decreases, and the doping concentration in the second region is uniformly doped; or,

The doping concentration in the third region gradually decreases, and the first region and the second region are uniformly doped; or,

The doping concentration in the third region, the first region and the second region gradually decreases; or,

The third region is uniformly doped, the doping concentration in the first region gradually decreases, and the doping concentration in the second region gradually increases; or,

The third region and the first region are uniformly doped, and the doping concentration in the second region gradually increases; or,

The third region and the second region are uniformly doped, and the doping concentration in the first region gradually decreases.

In one embodiment, the doping concentration in the first region, the second region, and the third region changes according to one of a linear distribution, an exponential distribution, a Gaussian distribution, and a residual error distribution.

In one embodiment, a conductive region that is not connected to the source region and the drain region is formed in the channel region; wherein,

When the conductive region is connected to the source region, the conductive region constitutes the equivalent source region; and/or,

When the conductive region is connected to the drain region, the conductive region constitutes the equivalent drain region.

In one embodiment, it includes a first gate disposed on one side surface of the active layer, and the vertical projections of the first gate and the conductive region on the channel region overlap; wherein, The first gate can control the channel region and form a channel therein, and a portion of the channel that does not overlap with a vertical projection of the conductive region on the channel region constitutes the effective channel. road.

In one embodiment, when the device is turned on, the conductance of the conductive region is greater than the conductance of the rest of the channel except the effective channel, so that at least one of the conductive region and the effective channel can flow toward the other of the conductive region and the effective channel. Inject carriers.

In one embodiment, the conductance of the conductive region is at least three times greater than the conductance of the rest of the channel except the effective channel.

In one embodiment, the field effect transistor device is a planar structure device or a vertical structure device.

In one embodiment, when the device is turned on, the conductance per unit length of the effective channel in the channel is less than the conductance per unit length of the rest of the channel except the effective channel.

In one embodiment, when the field effect transistor device is an N-type device, the work function of the portion of the first gate corresponding to the effective channel is greater than the work function of the remaining portion of the first gate;

When the field effect transistor device is a P-type device, the work function of the portion of the first gate corresponding to the effective channel is smaller than the work function of the remaining portion of the first gate.

In one embodiment, the field effect transistor device includes a gate insulating layer disposed between the first gate and a channel region, wherein a thickness of a portion of the gate insulating layer corresponding to the effective channel is greater than The remaining thickness of the gate insulating layer.

In one embodiment, the field effect transistor device includes a gate insulating layer disposed between the first gate and a channel region, wherein the dielectric of a portion of the gate insulating layer corresponding to the effective channel is The constant is greater than the dielectric constant of the rest of the gate insulating layer.

In one embodiment, a second gate electrode is provided on a side surface of the active layer adjacent to the conductive region, and the second gate electrode can control the formation of the conductive region in the channel region.

In one embodiment, the conductive region is formed by carriers introduced by surface doping of the channel region on a side away from the effective channel.

In one embodiment, an insulating layer is provided on a side surface of the active layer away from the effective channel, and the conductive region is insulated adjacent to the channel region through electrostatic induction by the injected charges in the insulating layer. Carriers generated at the layer.

In one embodiment, it also includes a semiconductor material layer disposed on a side surface of the active layer away from the effective channel, the active layer and the semiconductor material layer form a heterostructure, and the conductive region is composed of distributed It is composed of a two-dimensional electron gas channel or a two-dimensional hole gas channel in the heterostructure.

In one embodiment, the conductive region is composed of a two-dimensional electron gas channel or a two-dimensional hole gas channel formed by surface treatment on a side surface of the channel region away from the effective channel.

The present application also provides a field effect transistor device, including an active layer, the active layer including a source region, a drain region, and a channel region located between the source region and the drain region;

Wherein, at least part of the channel region is non-uniformly doped, so that a built-in electric field is formed in the channel region that guides carriers to move from the equivalent source region to the effective channel, and/or , a built-in electric field that guides carriers to move from the effective channel to the equivalent drain region.

Compared with the prior art, in the embodiments of the present application, by configuring the device to be turned on, an effective channel can be formed in the channel region, and an equivalent source region that is far away from the effective channel in the thickness direction of the channel region can be formed. and the equivalent drain region, thereby connecting the source region and the drain region to contribute to the operating current; in this way, the equivalent drain region (source region) connected to the drain (source) region is structurally far away from the effective channel, which can reduce The impact of small drain terminal voltage on the effective channel; and reducing the peak built-in electric field in the drain terminal depletion region when the device is saturated, thus suppressing the short channel effect of the device and improving the output characteristics of the device.

On the other hand, through uneven doping in the channel region, a built-in electric field is formed in the channel region that guides carriers to move from the equivalent source region to the effective channel, and/or, guides carriers from The built-in electric field in which the effective channel moves toward the equivalent drain region can not only ensure good suppression of the short channel effect, but also enable the device to have a smaller saturation drain voltage V _dsat and a larger saturation leakage current. I _dsat , kink voltage and output impedance _Ro .

Description of drawings

Figure 1 is a schematic diagram of a state in which a non-uniformly doped field effect transistor device forms an equivalent source region, an equivalent drain region, and an effective channel when it is turned on according to an embodiment of the present application;

Figure 2 is a schematic structural diagram of a non-uniformly doped field effect transistor device in an on state according to an embodiment of the present application;

Figure 3 is a schematic diagram of a state in which a conductive region is formed in a non-uniformly doped field effect transistor device according to an embodiment of the present application;

4 to 13 are schematic structural diagrams of non-uniformly doped field effect transistor devices according to various embodiments of the present application;

Figures 14 to 21 are schematic diagrams of the principles of making conductive areas in various embodiments of the present application;

Figures 22 to 24 are schematic structural diagrams of SOI devices applying the solution of this application;

Figure 25 is a schematic structural diagram of a non-uniformly doped field effect transistor device with a gap between the effective channel and the vertical projection of the conductive region on the channel region according to an embodiment of the present application;

Figures 26 and 27 are comparison diagrams of the transfer characteristics and output characteristics of each device in simulation example 1;

Figures 28 and 29 are comparison diagrams of the transfer characteristics and output characteristics of each device in simulation example 2;

Figures 30 and 31 are comparison diagrams of the transfer characteristics and output characteristics of each device in simulation example 3;

Figures 32 and 33 are comparison diagrams of the transfer characteristics and output characteristics of each device in simulation example 4;

Figures 34 and 35 are comparison diagrams of the transfer characteristics and output characteristics of each device in simulation example 5;

Figures 36 and 37 are comparison diagrams of the transfer characteristics and output characteristics of each device in simulation example 6;

Figures 38 and 39 are comparison diagrams of the transfer characteristics and output characteristics of each device in Simulation Example 7.

Detailed ways

Typical embodiments embodying the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various changes in different embodiments without departing from the scope of the present invention, and the description and illustrations are for illustrative purposes in nature, rather than for limitation. this invention.

Unless otherwise defined, all technical and scientific terms used in this specification have the same meanings commonly understood by those skilled in the technical field belonging to the present invention. The terminology used in the description of the present invention is for the purpose of describing specific embodiments only and is not intended to limit the present invention.

Referring to Figure 1, a specific implementation mode of the non-uniformly doped field effect transistor device of the present application is introduced. In this embodiment, the field effect transistor device 100 includes an active layer 10 , and the active layer 10 includes a source region 101 , a drain region 102 , and a channel region 103 .

The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10 , and the channel region 103 is located between the source region 101 and the drain region 102 . In conjunction with the schematic diagram of the device turned on shown in FIG. 1 , an effective channel 1041 is formed in the channel region 103 of the field effect transistor at this time, as well as an equivalent source region 1051 and the like that are far away from the effective channel 1041 in the thickness direction of the channel region 103 . The effective drain region 1052 is used by the field effect transistor device 100 to connect the source region 101 and the drain region 102 through the effective channel 1041, the equivalent source region 1051, and the equivalent drain region 1052 to contribute operating current.

In some embodiments of the present application, the “distance” between the effective channel 1041 and the equivalent source region 1051 and the equivalent drain region 1052 may also include the length of the channel region in addition to the thickness direction of the channel region. direction away. In these embodiments, regardless of the distance in the thickness or length direction of the channel region, when the device is turned on, it does not affect the effective channel 1041, the equivalent source region 1051, and the equivalent drain region 1052 connecting the source region 101 and drain region 102.

In a typical field effect transistor device 100, the source region 101 of the active layer 10 is used to provide carriers when the device is turned on, and the drain region 102 is used to collect carriers provided by the source region 101. Correspondingly, in this application, the equivalent source region 1051 mentioned refers to a structure in which part of the carriers provided by the source region 101 are directly injected into the effective channel 1041, while the equivalent drain region 1052 refers to a structure in which some carriers provided by the source region 101 are directly injected into the effective channel 1041. The structure of the channel 1041 directly receives some carriers and injects them into the drain region 102 .

With reference to Figure 2, the "effective channel 1041" mentioned in this application refers to the part of the channel through which carriers serving as operating current will pass when the device is turned on. Taking this embodiment as an example, a first gate 20 may be disposed on one side surface of the active layer 10 , and the vertical projection of the first gate 20 on the active layer 10 is between the source region 101 and the drain region 102 . There is no gap between them. Therefore, when a gate bias is applied to the first gate 20 to turn on the device, a channel 104 can be controlled to be formed below the first gate 20 , and the channel 104 is structurally connected to the source region 101 and drain region 102. However, from a functional perspective, only the portion of the channel that does not overlap with the vertical projections of the equivalent source region 1051 and the equivalent drain region 1052 on the channel region 103 is used to transmit the entire operating current, and therefore Only this part of the channel will be called the "effective channel 1041" here.

In this embodiment, the carrier path when the device is turned on includes two main parts: one part is from the source region 101 to the equivalent source region 1051, the effective channel 1041, the equivalent drain region 1052, and the drain region 102 in sequence. , the other part is from the source region 101 directly through the channel 104 into the drain region 102 . From the perspective of the carrier path, the remaining channels in the channel 104 except the effective channel 1041 are only used to transmit part of the operating current.

It can be seen that the effective channel 1041 in this application is not limited to having a different device structure or parameter setting than the rest of the channel 104 . In fact, in some embodiments, the above-mentioned channel 104 can be formed entirely in the channel region, and only the equivalent source region 1051 and the equivalent drain region 1052 are provided, so that when the device is turned on, the source region The carriers provided by 101 will not all be directly injected into the drain region 102 through the channel 104. The adjustments to the channel that may be shown in some of the following embodiments, such as changing the work function of the first gate corresponding to the effective channel, the thickness of the gate insulating layer, etc., should not be considered necessary to form an effective channel. Prerequisites.

The arrangement of the equivalent source region 1051 and the equivalent drain region 1052 is equivalent to shortening the length of the part of the channel 104 that can conduct all operating currents, that is, there is a gap between the effective channel 1041 and the source region 101 and the drain region 102 interval. Moreover, the equivalent drain region 1052 connected to the drain region 102 is structurally far away from the effective channel 1041, which reduces the influence of the drain end potential on the effective channel 1041; while the equivalent source region 1051 connected to the source region 101 Structurally far away from the effective channel 1041, the potential of the equivalent source region 1051 is consistent with the source region (usually zero potential), which also reduces the impact of the drain potential on the effective channel 1041 to improve the short channel of the device. Tao effect.

Referring to Figure 3, in the specific preparation of the equivalent source region 1051 and the equivalent drain region 1052, a conductive region A that is not connected to the source region 101 and the drain region 102 can be formed in the channel region 103. When the conductive region A When connected to the source region 101, this part of the conductive region A constitutes an equivalent source region 1051; when connected to the drain region 102, this part of the conductive region A constitutes an equivalent drain region 1052.

When the device is turned on, the conductance of the conductive region A is set to be greater than the conductance of the remaining portion 1042 of the channel 104 except the effective channel 1041, so that carriers can be injected into each other between the conductive region A and the effective channel 1041. In this way, the carriers in the source region 101 will be attracted by the equivalent source region 1051 with greater conductivity, and will not be directly injected into the remaining portion 1042 of the channel 104 that is directly connected to the source region 101; similarly, in the effective The carriers transported in the channel 1041 will also be attracted by the equivalent drain region 1052 and will not all be transported through the remaining portion 1042 in the channel 104 .

In order to achieve the carrier injection arrangement between the equivalent source region 1051 , the equivalent drain region 1052 , and the effective channel 1041 here, the conductance of the conductive region A may be set to be at least greater than that of the channel 104 except the effective channel 1041 The electrical conductivity of the remaining part 1042 is three times that of the outside. Moreover, since carriers will flow in the thickness direction of the channel region 103 during the above-mentioned "injection" process, in this embodiment, the conductive region A and the effective channel 1041 in the thickness direction of the channel region 103 The spacing can be set to 5 nm to 10 μm, or more preferably 10 nm to 1 μm, or more preferably 10 nm to 100 nm according to the specific design of different devices to ensure normal injection of carriers and device performance.

It should be noted that the "carriers" mentioned in this application refer to charge particles that can move freely in the corresponding polarity channel/conductive region A. Generally, we refer to electrons or P in the N-type channel The holes in the N-type channel are called "carriers" here. Correspondingly, the holes in the N-type channel or the electrons in the P-type channel are not called "carriers" here. Therefore, In this application, the polarities of the effective channel 1041 and the conductive region A are set to be the same, so that the carrier interaction between the two channels can ultimately substantially contribute to the operating current of the device.

The shape and position of the conductive area can be set according to the application needs of the device, and is not limited to the form shown in Figure 3. For example, the conductive region A in the field effect transistor device 200 shown in FIG. 4 may have a larger overall thickness and an irregular region shape relative to FIG. 3 . For another example, in the field effect transistor device 300 shown in FIG. 5 , the conductive region A is not located at the same height in the thickness direction of the channel region.

Referring to FIG. 6 , in this embodiment, the region corresponding to the equivalent source region 1051 in the channel region 103 is called the first region S1 , and the region corresponding to the equivalent drain region 1052 in the channel region 103 is called the first region S1 . In the second region S2, the region corresponding to the effective channel 1041 in the channel region 103 is called the third region S3. The “correspondence” here can be understood as: in the thickness direction of the channel region 103, the channel region 103 is “divided” into three regions by the vertical projection of the equivalent source region 1051, the equivalent drain region 1052, and the effective channel 1041. , therefore, the area divided by the vertical projection of the equivalent source area 1051 is the first area S1, the area divided by the vertical projection of the equivalent drain area 1052 is the second area S2, and the area divided by the vertical projection of the effective channel 1041 is the second area S2. The area obtained by projection division is the third area S3.

It should be noted that the “first region S1”, “second region S2” and “third region S3” mentioned in each embodiment of the present application do not include the device channel region 103 for forming the above-mentioned channel. , equivalent source region 1051 and part of the equivalent drain region 1052 .

Specifically, in this embodiment, in the direction in which the channel region 103 approaches the effective channel 1041, at least part of the doping concentration in the first region S1 gradually decreases; and/or, at least part of the doping concentration in the second region S2 The concentration gradually increases; and/or at least part of the doping concentration in the third region S3 gradually decreases; and/or, in the direction from the source region 101 to the drain region 102, at least part of the doping concentration in the third region S3 The concentration gradually decreases.

It should be noted that among the doping mentioned in various implementation modes/examples of this application, for N-type devices, the doping of the channel region should be P-type; similarly, for P-type devices , the doping of the channel region should be N-type.

Continuing to refer to FIG. 6 , in various embodiments of the present application, the direction in which the channel region 103 approaches the effective channel 1041 is defined as the direction D from the bottom of the channel region 1041 to the effective channel along the thickness direction of the channel region 1041 .

Taking the gradual reduction of at least part of the doping concentration in the first region S1 as an example, the doping in the first region S1 may be a change in the "vertical doping depth" in the thickness direction of the channel region 103 . For example, the doping in the first region S1 may be doping to one-quarter, one-half, three-quarters of the thickness of the channel region 103, or full depth doping.

Referring to FIG. 7 , taking the gradual reduction of at least part of the doping concentration in the first region S1 as an example, the doping in the first region S1 may change the "lateral doping width" in the length direction of the effective channel 1041 . For example, the doping in the first region S1 may be doped at a quarter, a half, or three-quarters of the first region S1 along the length direction of the effective channel 1041 or in the first region S1 full width doping.

In various embodiments of the present application, at least part of the doping in the second region S2 and the third region S3 may be partially or fully referred to the above description of the doping in the first region. Moreover, it should be noted that the description of non-uniform doping of the first region S1, the second region S2 and the third region S3 in each implementation mode/example of the present application does not describe the doping of the remaining parts of the channel region 103. Restrictive Exclusions. For example, when only the first region S1 is defined as being non-uniformly doped, it does not mean that the rest of the channel region 103 is intrinsic.

Similarly, with reference to FIGS. 8 and 9 , in the direction from the source region 101 to the drain region 102 , the doping concentration of at least part of the third region S3 gradually decreases, which may be in the thickness direction of the channel region 103 There is a change in the "vertical doping depth", or there is a change in the "lateral doping width" in the length direction of the effective channel 1041, which will not be described again here.

Generally speaking, through at least part of the uneven doping in the channel region 103, a built-in electric field is formed in the channel region 103 that guides carriers to move from the equivalent source region 1051 to the effective channel 1041, and/or, A built-in electric field that guides carriers to move from the effective channel 1041 to the equivalent drain region 1052. Therefore, the doping concentration changes in the first region S1, the second region S2, and the third region S3 mentioned in this embodiment may be implemented in coordination with each other. Some exemplary embodiments are given below:

In one embodiment, in the direction in which the channel region 103 approaches the effective channel 1041, the doping concentration in the third region S3 and the first region S1 gradually decreases, and the doping concentration in the second region S2 gradually increases. In this embodiment, the doping through the third region S3 and the first region S1 at least provides a built-in electric field that guides carriers to move from the equivalent source region 1051 to the effective channel 1041, and through the doping of the second region S2 Doping provides a built-in electric field that guides carrier movement from the effective channel 1041 to the equivalent drain region 1052 .

In one embodiment, in the direction in which the channel region 103 approaches the effective channel 1041, the doping concentration in the third region S3 and the first region S1 gradually decreases, and the doping concentration in the second region S2 is uniformly doped. In this embodiment, the doping through the third region S3 and the first region S1 at least provides a built-in electric field that guides carriers to move from the equivalent source region 1051 to the effective channel 1041 .

In one embodiment, in the direction in which the channel region 103 approaches the effective channel 1041, the doping concentration in the third region S3 gradually decreases, and the first region S1 and the second region S2 are uniformly doped. In this embodiment, the doping through the third region S3 at least provides a built-in electric field that guides carriers to move from the equivalent source region 1051 to the effective channel 1041 .

In one embodiment, the third region S3 is uniformly doped. In the direction in which the channel region 103 approaches the effective channel 1041, the doping concentration in the first region S1 gradually decreases, and the doping concentration in the second region S2 gradually decreases. rise. In this embodiment, the doping in the first region S1 at least provides a built-in electric field that guides carriers to move from the equivalent source region 1051 to the effective channel 1041 , and the doping in the second region S2 provides guidance. The built-in electric field in which carriers move from the effective channel 1041 to the equivalent drain region 1052.

In one embodiment, the third region S3 and the first region S1 are uniformly doped, and the doping concentration in the second region S2 gradually increases in the direction in which the channel region 103 approaches the effective channel 1041 . In this embodiment, the doping through the second region S2 at least provides a built-in electric field that guides carriers to move from the effective channel 1041 to the equivalent drain region 1052 .

In one embodiment, the third region S3 and the second region S2 are uniformly doped, and the doping concentration in the first region S1 gradually decreases in the direction in which the channel region 103 approaches the effective channel 1041 . In this embodiment, the doping through the first region S1 at least provides a built-in electric field that guides carriers to move from the equivalent source region 1051 to the effective channel 1041 .

In one embodiment, in the direction in which the channel region 103 approaches the effective channel 1041, the doping concentration in the third region S3, the second region S2 and the first region S1 gradually decreases. In this embodiment, the doping through the first region S1 and the third region S3 at least provides a built-in electric field that guides carriers to move from the equivalent source region 1051 to the effective channel 1041 .

In one embodiment, in the direction in which the channel region 103 approaches the effective channel 1041, the doping concentration in the third region S3 gradually decreases. At the same time, in the direction in which the source region points to the drain region, the doping concentration in the third region S3 The doping concentration also gradually decreases. In this embodiment, the doping concentration in the third region S3 has a gradual change trend in both directions, and the third region S3 can at least provide guidance for carriers from the equivalent source region 1051 to the effective channel. 1041 movement, and the built-in electric field moving from the effective channel 1041 to the equivalent drain region 1052.

In this embodiment, the doping concentration in the first region S1, the second region S2, and the third region S3 changes according to one of a linear distribution, an exponential distribution, a Gaussian distribution, and a residual error distribution. Moreover, in some embodiments, the doping concentration in these regions can be made to have a greater rate of change, thereby forming a greater built-in electric field that guides carrier movement.

Taking the doping concentration in the first region S1, the second region S2 and the third region S3 according to the exponential distribution as an example, the exponential factor can be set to be larger (that is, a in the exponential function y=a ^x is larger), so that At least part of the performance of the device is improved.

In this embodiment, the doping concentration in the channel region 103 can be set such that it does not affect the mobility of carriers in the corresponding region of the channel 104 at the interface adjacent to the channel 104, thereby affecting the formation of the inversion layer. And degrade the turn-on characteristics of the device.

Exemplarily, for a silicon device, if the doping concentration in the channel 104 is 3.5E18cm ^-3 , the doping concentration at the interface adjacent to the channel 104 in the channel region 103 may be, for example, 3.5E12cm ^-3 , 3.5E13cm ^-3 , 5.5E14cm ^-3 , etc.

In the above embodiments, the field effect transistor device of the present application is explained based on the fact that the field effect transistor device includes both an equivalent source region and an equivalent drain region. In some embodiments, the field effect transistor device may also include only an equivalent drain region. Source area or equivalent drain area.

Referring to FIG. 10 , another embodiment of the field effect transistor device 200 of the present application is introduced.

Different from the above embodiment, in this embodiment, when the device is turned on, no equivalent drain region is formed in the channel region 103 at this time. The field effect transistor device 200 connects the source region 101 and the drain region 102 through the effective channel 1041 and the equivalent source region 1051 to contribute operating current.

In this embodiment, it is equivalent to weakening the influence of the drain end potential on the potential near the source end of the channel region 103 through the arrangement of the equivalent source region 1051, thereby improving the short channel effect of the device. Correspondingly, active channel 1041 is directly connected to drain region 102 .

When the device is turned on, during carrier transport, part of the carriers provided by the source region 101 enters the equivalent source region 1051, and is injected into the effective channel 1041 from the end of the equivalent source region 1051 away from the source region 101; the flow The carriers through the effective channel 1041 are injected back into the drain region 102 . That is, in this embodiment, only the conductive region injects carriers into the effective channel 1041 in one direction.

Correspondingly, in the channel region of this embodiment, there are only the first region S1 corresponding to the equivalent source region 1051 and the third region S3 corresponding to the effective channel 1041. Similarly, in the direction in which the channel region 103 approaches the effective channel 1041, the doping concentration of at least part of the first region S1 gradually decreases; and/or, the doping concentration of at least part of the third region S3 gradually decreases; and /Or, in the direction from the source region 101 to the drain region 102, the doping concentration of at least part of the third region S3 gradually decreases.

Referring to FIG. 11 , another implementation of the field effect transistor device 300 of the present application is introduced.

Different from the above embodiment, in this embodiment, when the device is turned on, no equivalent source region is formed in the channel region 103 at this time. The field effect transistor device 300 connects the source region 101 and the drain region 102 through the effective channel 1041 and the equivalent drain region 1052 to contribute operating current.

In this embodiment, it is equivalent to weakening the influence of the drain terminal potential on the effective channel 1041 only through the arrangement of the equivalent drain region 1052, thereby improving the short channel effect of the device. Correspondingly, the active channel 1041 is directly connected to the source region.

During carrier transfer, the carriers provided by the source region 101 enter the effective channel 1041, and some of the carriers are injected into the equivalent drain region 1052 from the end of the effective channel 1041 away from the source region 101, and then injected again. back to drain region 102 . That is, in this embodiment, only the effective channel 1041 injects carriers into the conductive region in one direction.

Correspondingly, in the channel region of this embodiment, there are only the second region S2 corresponding to the equivalent drain region 1052 and the third region S3 corresponding to the effective channel 1041 . Similarly, in the direction in which the channel region 103 approaches the effective channel 1041, the doping concentration of at least part of the second region S2 gradually increases; and/or, the doping concentration of at least part of the third region S3 gradually decreases; And/or, in the direction from the source region 101 to the drain region 102, the doping concentration of at least part of the third region S3 gradually decreases.

In the above embodiments of the field

effect transistor devices

200 and 300, regarding the specific definitions and doping methods of the first region S1, the second region S2, and the third region S3, please refer to the embodiment of the field effect transistor device 100. , which will not be described in detail here.

In the above-described embodiment, a structure has been shown in which a part of the channel formed by gate control constitutes an effective channel. In such a structure, in order to further improve the device's ability to suppress short channel effects, the unit length conductance of the effective channel in the channel can be set to be smaller than the unit length conductance of the rest of the channel except the effective channel. Some corresponding implementations are introduced below.

Referring to FIG. 12 , another embodiment of the field effect transistor device 400 of the present application is introduced.

Field effect transistor device 400 includes active layer 10 including source region 101 , drain region 102 , and channel region 103 . The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10 , and the channel region 103 is located between the source region 101 and the drain region 102 .

An insulating layer 30 and a first gate electrode 20 are arranged in sequence above the channel region, and the thickness of the gate insulating layer 302 corresponding to the effective channel 1041 is greater than the thickness of the remaining gate insulating layer 301 . That is, the gate insulating layer 301 corresponding to the equivalent source region 1051 and the equivalent drain region 1052 is relatively thinned. In this way, the corresponding gate pair of the corresponding part of the channel 1042 in the remaining part of the channel 1042 other than the effective channel 1041 can be enhanced. modulation capability, thereby increasing the conductance of the corresponding part of the channel 1042.

Optionally, in this embodiment, the dielectric constant of the gate insulating layer 302 corresponding to the effective channel 1041 can also be set to be smaller than that of the remaining gate insulating layers 301 to further increase the dielectric constant of the remaining channels 1042 other than the effective channel 1041 . Conductance.

Referring to FIG. 13 , another implementation of the field effect transistor device 500 of the present application is introduced.

Field effect transistor device 500 includes active layer 10 including source region 101 , drain region 102 , and channel region 103 . The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10 , and the channel region 103 is located between the source region 101 and the drain region 102 .

The first gate 20 is disposed above the channel region 103, and the portion 201 corresponding to the effective channel 1041 and the remaining portion 202 of the first gate 20 are made of different materials, so that the effective channel in the first gate 20 The channels formed corresponding to the portion 201 and the remaining portion 201 of 201 have different modulation capabilities, and the conductance per unit length of the effective channel 1041 is smaller than the conductance per unit length of the remaining portion 1042 of the channel 104 except the effective channel 1041.

In this embodiment, if the field effect transistor device 500 is an N-type device, the work function of the portion 201 of the first gate 20 corresponding to the effective channel 1041 is set to be greater than the work function of the remaining portion 202 of the first gate 20; Correspondingly, if the field effect transistor device 500 is a P-type device, the work function of the portion 201 of the first gate 20 corresponding to the effective channel 1041 is set to be smaller than the work function of the remaining portion 202 of the first gate 20 .

Specifically, if it is an N-type device, the portion 201 of the first gate 20 corresponding to the effective channel 1041 can use a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or adjust the compound composition The obtained ITO, RuO ₂ , WN, MoN, etc. with larger work functions are used as gate materials; the remaining part 202 can be made of metals with smaller work functions such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or adjusted Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with smaller work functions obtained from the compound components are used as gate materials. If it is a P-type device, the portion 201 of the first gate 20 corresponding to the effective channel 1041 can be made of metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or the compound composition can be adjusted The obtained Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with smaller work functions are used as gate materials; the remaining parts 202 can use metals with larger work functions such as gold, platinum, or P-type doped (P+) polysilicon , or ITO, RuO ₂ , WN, MoN, etc., which have a larger work function obtained by adjusting the compound composition, are used as gate materials.

The following uses some specific examples to introduce the formation method of the first conductive region and the second conductive region in this application:

Example 1

The first conductive region A1 and the second conductive region A2 are formed by carriers introduced by surface doping of the channel region 103A on a side away from the effective channel 1041A.

Correspondingly, referring to Figure 14, if it is an N-type silicon-based device 100A, the doping concentration of the interface can be changed by doping donor atoms, such as phosphorus, arsenic, etc., on the surface of the channel region 103A away from the effective channel 1041A; refer to Figure 15 , if it is a P-type silicon-based device 100A, the interface doping concentration can be changed by doping acceptor atoms, such as boron, on the surface of the channel region 103A away from the effective channel 1041A.

Example 2

Referring to FIGS. 16 and 17 , the field effect transistor device 100B further includes an insulating layer 40B disposed on the surface of the active layer 10B away from the effective channel 1041B. The conductive region A is electrostatically induced in the channel by the injected charges in the insulating layer 40B. One side of the area is formed on the surface.

Correspondingly, referring to Figure 16, if it is an N-type device, it can be achieved by locally injecting positive charges, such as H+ and holes, into the insulating layer 40B; Referring to Figure 17, if it is a P-type device, it can be achieved by injecting positive charges, such as H+ and holes, into the insulating layer 40B. The local injection of negative charges in 40B, such as F-, Cl-, electrons, etc., is achieved. In this way, a high density of fixed charges is formed in the insulating layer 40B, and carriers in the conductive region A are generated in the channel region 103B adjacent to the insulating layer 40B through electrostatic induction. It should be noted that “partial” here refers to the partial region of the insulating layer 40B corresponding to the channel region where the conductive region A needs to be formed.

During a specific charge injection process, charges can be injected into the insulating layer 40B closer to the channel region 103B, so that the conductive region A formed in the channel region 103B can store more carriers. Of course, in some other alternative embodiments, a "double insulating layer" structure may also be used, specifically including a charge trapping layer disposed on the surface of the channel region 103B and a conventional insulating layer covering the charge trapping layer. The charge trapping layer can be made of a material that is easier to store charges, or metal or semiconductor nanoparticles can be introduced into it to store charges more stably, thereby ensuring stable and controllable carriers in the conductive region.

Example 3

Referring to FIG. 18 , a field effect transistor device 100C includes a semiconductor material layer 40C disposed on an active layer 10C. The semiconductor material layer 40C and the active layer 10C form a heterostructure. The conductive region A is composed of two layers distributed in the heterostructure. A two-dimensional electron gas channel or a two-dimensional hole gas channel is formed.

Specifically, the semiconductor material layer 40C and the active layer 10C have different band gap widths, and the semiconductor material layer 40C can be divided into two parts connected to the source region 101C and the drain region 102C respectively, so that the formed two-dimensional electron gas The channel does not conduct the source and drain regions.

Of course, in some alternative embodiments, the channel region 103C can also be surface treated to form a two-dimensional electron gas channel or a two-dimensional hole gas channel. These two-dimensional electron gas channels or two-dimensional hole gas channels are commonly known to those skilled in the art. Alternative embodiments of electron gas channels or two-dimensional hole gas channels should fall within the scope of the present application. Moreover, the semiconductor material layer 40C mentioned here may be a barrier layer, and the barrier layer may be doped or intrinsic.

Example 4

Referring to FIG. 19, a field effect transistor device 100D is fabricated as a device including at least two gate electrodes. Specifically, the field effect transistor device 100D includes a first gate insulating layer 30D and a first gate electrode 20D sequentially disposed on one side surface of the active layer 10D, and a third gate electrode 20D sequentially disposed on one side surface of the active layer 10D adjacent to the conductive region A. The second gate insulating layer 40D and the second gate electrode 50D.

The second gate 50D is correspondingly divided into two parts, one part has a vertical projection on the active layer 10D connected to the source region 101D, and the other part has a vertical projection on the active layer 10D connected to the drain region 102D. In this way, when appropriate bias voltages are applied to these two parts of the second gate 50D, conductive regions A connecting the source region 101D and the drain region 102D can be formed at corresponding positions in the channel region 103D.

In this embodiment, the absolute value of the bias voltage applied to the second gate 50D should be greater than the absolute value of the turn-on voltage applied to the device. Correspondingly, if it is an N-type device, a forward bias greater than the first gate 20D is applied to the second gate 50D; if it is a P-type device, a forward bias voltage greater than the first gate 20D in absolute value is applied to the second gate 50D. Extremely 20D negative bias.

Example 5

Referring to FIG. 20 , the field effect transistor device 100E is fabricated similarly to Embodiment 4 and includes at least two gate electrodes. But the difference is that in this embodiment, in order to make the conductance of the conductive region A larger than the conductance of the portion 1042E of the channel 104E except the effective channel 1041E, the first gate 20E and the first gate 20E of different work function gate materials can be used. Second gate 50E. That is, the work function difference between the first gate electrode 20E and the active layer 10E is not equal to the work function difference between the second gate electrode 50E and the active layer 10E.

Correspondingly, if it is an N-type device, the first gate 20E can be made of a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO or RuO2 with a larger work function obtained by adjusting the compound composition. , WN, MoN, etc. as the gate material; the second gate 50E can use a metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or a smaller work function obtained by adjusting the compound composition. Function Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. as gate materials. If it is a P-type device, the first gate 20E can be made of metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru- with a smaller work function obtained by adjusting the compound composition. Hf, WN, HfN, TiN, TaN, TaSiN, etc. are used as gate materials; the second gate 50E can be obtained by using metals with larger work functions such as gold, platinum, or P-type doped (P+) polysilicon, or by adjusting the compound composition ITO, RuO ₂ , WN, MoN, etc. with larger work functions are used as gate materials.

In the N-type device, the work function difference between the first gate 20E and the active layer 10E can also be set to be greater than zero (Φms>0V), so that the channel 104E is an enhancement channel; at the same time, the second gate 50E is set The work function difference with the active layer 10E is less than zero (Φms<0V), so that the conductive region A can also form a certain number of carriers under the action of the bias voltage applied thereto when the device is turned off. In the P-type device, the work function difference between the first gate 20E and the active layer can be set to be less than zero (Φms<0V), so that the channel 104E is an enhancement channel; at the same time, the second gate 50E is set to have an The work function difference of the source layer 10E is greater than zero (Φms>0V), so that when the device is turned off, the conductive region A can also form a certain number of carriers under the action of the bias voltage applied thereto.

Example 6

Referring to FIG. 21 , the field effect transistor device 100F is manufactured similarly to Embodiment 4 and includes at least two

gate electrodes

20F and 50F. But the difference is that in this embodiment, in order to make the conductance of the conductive region A greater than the conductance of the portion 1042F of the channel 104F except the effective channel 1041F, the unit area capacitance of the second gate insulating layer 40F can be set to be greater than that of the first gate. The capacitance per unit area of the insulating layer 30F.

Specifically, this can be achieved by adjusting the dielectric constant of the first gate insulating layer 30F and the second gate insulating layer 40F, or the thickness of the first gate insulating layer 30F and the second gate insulating layer 40F.

For example, when the first gate insulating layer 30F and the second gate insulating layer 40F have the same thickness, only the dielectric constant of the gate insulating layer can be considered, and the second gate insulating layer 40F can be set to have a higher dielectric constant than the first gate insulating layer. The dielectric constant of layer 30F is enough. Exemplarily, the first gate insulating layer 30F may be made of silicon dioxide, and the second gate insulating layer 40F may be made of a high dielectric constant medium such as hafnium dioxide, aluminum oxide, etc.

For another example, when the first gate insulating layer 30F and the second gate insulating layer 40F are made of the same material, only the thickness of the gate insulating layer may be considered, and the thickness of the second gate insulating layer 40F may be set to be smaller than the thickness of the first gate insulating layer 30F.

In specific device applications, the second gate in the above-mentioned Embodiments 4 to 6 can also be directly floating or grounded to avoid excessive device connection terminals and increasing the complexity of the device application.

Moreover, the methods of forming the conductive areas in the above embodiments can also be applied in combination with each other to achieve better implementation effects.

The field effect transistor device introduced in each of the above embodiments/examples may be a planar structure device or a vertical structure device. The following will take an SOI device (TFT device) as an example to exemplify the specific settings of the solution of the present application when applied to the SOI device.

Example 7

Referring to FIG. 22 , a planar top-gate structure TFT device 100G is shown, and includes a light-transmitting insulating substrate 40G, an active layer 10G, a gate dielectric layer 30G, and a gate electrode 20G sequentially provided on the substrate 40G. Both sides of the active layer 10G are doped to form a source region 101G and a drain region 102G respectively, and are externally connected to the source electrode and the drain electrode respectively; the channel region 103G is located between the source region 101G and the drain region 102G.

Positive charge regions 60G are formed on both sides of the source region 101G and the drain region 102G on the substrate 40G through ion implantation or other methods. The positively charged region 60G and the gate 20G have an overlapping portion between the vertical projections of the channel region 103G. Correspondingly, the positively charged region of the overlapping portion can be formed in the channel region 103G and the source region 101G and the source region 101G respectively. The two-dimensional electron gas 70G connected to the drain region 102G, the two-dimensional electron gas 70G here also constitutes the conductive region, and the carrier blocking region 80G is formed in the two-dimensional electron gas connected to the source region 101G and the drain region 102G. Between 70G.

When the device is turned on, a channel is formed below the gate 20G, and the vertically projected portion of the channel between the conductive areas constitutes an actual effective channel.

Example 8

Referring to Figure 23, a planar bottom-gate structure TFT device 100H is shown, and includes a light-transmissive insulating substrate 40H, a gate electrode 20H, a gate dielectric layer 30H, and an active layer 10H sequentially provided on the substrate 40H. In this embodiment, upper metal source electrodes 501H and metal drain electrodes 502H are respectively provided on both sides of the active layer 10H. The active layer 10H can be an amorphous IGZO metal oxide semiconductor layer. The source electrode 501H and the drain electrode 502H are in contact with the active layer. Ohmic contact is formed between layers 10H. Part of the active layer under the source electrode 501H and the drain electrode 502H respectively constitutes the source region and the drain region, and the channel region is located between the source region and the drain region.

Positively charged regions 60H are respectively connected to the source electrode 501H and the drain electrode 502H by ion implantation in the passivation layer covering the upper layer of the device. The positively charged region 60H and the gate 20H have an overlapping portion between the vertical projections of the channel region. Correspondingly, the positively charged region of the overlapping portion can be formed in the channel region with the source region and the drain region respectively. The connected two-dimensional electron gas 70H, the two-dimensional electron gas 70H here also constitutes the conductive region, and the carrier blocking region 80H is formed between the two-dimensional electron gas 70H connected to the source region and the drain region.

When the device is turned on, a channel is formed above the gate 20H, and the portion of the channel vertically projected between the conductive regions 70H constitutes an actual effective channel.

Example 9

Referring to Figure 24, a vertical structure SOI device 100I is shown, and includes a substrate 60I, a buried insulating layer 50I and an active layer 10I disposed in sequence on the substrate 60I, a gate insulating layer 30I disposed on one side of the active layer 10I, a gate Extreme 20I. In the direction away from the substrate 60I, the source region 101I and the drain region 102I are respectively located below and above the active layer 10I. An equivalent source region 1051I connected to the source region 101I and an equivalent drain region 1052I connected to the drain region 102I are formed in the channel region 103I.

When a bias voltage is applied to the gate 20I of the device to turn on the device, the gate 20I controls the formation of a channel 104I connecting the source region 101I and the drain region 102I in the channel region 103I of the device. However, there is only The non-overlapping portion of the vertical projection of the equivalent source region 1051I and the equivalent drain region 1052I on the channel region 103I constitutes the effective channel 1041I for transmitting operating current when the device is turned on, that is, the portion in the channel 104I The remaining part 1042I is not used to transmit the operating current when the device is turned on.

In each of the above implementations/embodiments, the source and drain regions in the device can be common heavily doped semiconductor sources and drains, or they can be Schottky metal source and drain of a metal-semiconductor structure; the gate can be It is a common metal-insulating layer-semiconductor MOS structure gate, or it can be a Schottky junction gate of a metal semiconductor structure; the active layer can be composed of a single semiconductor material, or it can include layers along its thickness direction or plane extension direction. Varying at least two semiconductor materials to form a composite channel.

Moreover, the equivalent source region and the equivalent drain region may be formed spontaneously, or may be formed through gate control of corresponding structures.

Generally speaking, in the above embodiments, the vertical projection of the effective channel, the equivalent source region and/or the equivalent drain region superimposed on the channel region connects the source region and the drain region, thereby ensuring that the effective channel and Carriers in the equivalent source region and/or the equivalent drain region can be injected in one direction or two directions at least in the thickness direction, and a carrier path from the source region to the drain region can be constructed. Of course, referring to FIG. 25 , the present application does not exclude that in some special embodiments, if the vertical projections of the effective channel, the equivalent source region and the equivalent drain region superimposed on the channel region 103J are not able to connect the device 100J The source region 101J and the drain region 102J have an "appropriate interval", which does not completely cut off the flow of carriers from the equivalent source region 1051J to the effective channel 1041J, and from the effective channel 1041J, etc. In the path of the effective drain region 1052J, the injection direction of carriers between the effective channel 1041J, the equivalent source region 1051J, and the equivalent drain region 1052J forms an angle with the thickness direction of the channel region 103J. Such an implementation should also It falls within the protection scope of this application.

The following are the results of Silvaco TCAD simulation verification using the SOI device according to the above implementation mode/example of the present application. Among them, the gradual decrease of the doping concentration in the direction of the channel area close to the effective channel is called "forward doping", and the gradual increase of the doping concentration in the direction of the channel area close to the effective channel is called "reverse doping". ".

Simulation example 1

In Simulation Example 1, the SOI device to which the above-mentioned embodiments/examples of the present application are applied is called the "SOI device of the present application", wherein the SOI device of the present application is forward doped in the entire channel region, and the doping concentration According to the exponential distribution (the exponential factor a in the exponential function y=a ^x is selected as 1.5, 2, or 3). For comparison, an SOI device with a similar structure to the SOI device of this application is used, and the only difference is that the SOI device for comparison (called a comparative SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping) .

Simulation parameters: The source and drain doping is N-type, the doping concentration is 1E21cm ^-3 , the channel doping is P-type, the doping concentration is 1E17cm ^-3 , the channel length L _g is 130nm, and the effective channel length L _eff is 70nm, the length of the equivalent source region L _es and the equivalent drain region L _ed are both 30nm, the thickness of the active layer is 50nm, and the thickness of the gate insulating layer is 5nm, forming fixed charges at the interface between the equivalent source region and the equivalent drain region The areal density is 1E14cm ^-2 .

Refer to Figure 26, which is a comparison diagram of the transfer characteristics of the SOI device of the present application and the comparative SOI device when the drain terminal voltage _Vd is 2V. It can be seen that the SOI device of the present application has stronger short channel effect suppression ability than the comparative SOI device, and the larger the exponential factor, the smaller the sub-threshold swing, and the stronger the short channel effect suppression ability.

Refer to Figure 27, which is a comparison chart of the output characteristics of the SOI device of this application and the comparative SOI device when the gate terminal voltage V _g is 2.5V. It can be seen that the larger the exponential factor of the SOI device of this application, the saturation voltage V _dsat and saturation current I _dsat will be improved to a certain extent, while the kink voltage and output impedance _Ro will be lost.

Simulation example 2

In Simulation Example 2, the SOI device to which the above-mentioned embodiments/examples of the present application are applied is called the "SOI device of the present application", wherein the SOI device of the present application is forward doped in the entire channel region, and the doping concentration According to the exponential distribution (the exponential factor a in the exponential function y=a ^x is selected as 2). The doping depths are respectively 0.25 times, 0.5 times, 0.75 times and full depth doping in the thickness direction of the channel region.

Refer to Figure 28, which is a comparison diagram of the transfer characteristics of the SOI device of the present application when the drain terminal voltage _Vd is 2V. It can be seen that after the doping depth of the SOI device of the present application reaches more than 0.5 times the thickness of the channel region, the sub-threshold swing is close. That is, when the doping depth is greater than or equal to 0.5 times the thickness of the channel region, the SOI device of the present application It can have better ability to suppress short channel effects.

Refer to Figure 29, which is a comparison diagram of the output characteristics of the SOI device of the present application when the gate terminal voltage V _g is 2.5V. It can be seen that when the SOI device of the present application has a doping depth less than 0.5 times the thickness of the channel region, there is almost no loss in saturation voltage V _dsat and saturation current I _dsat , but there is a significant loss in kink voltage.

Simulation example 3

In Simulation Example 3, the SOI device applying the above-mentioned embodiments/examples of the present application is called the "SOI device of the present application", in which the SOI device of the present application is forward doped (FC.for) in the entire channel region. ), forward doping in the first region (Les.for), forward doping in the second region (Led.for), forward doping in the third region (Leff.for), doping depth is the thickness of the entire channel region, and the doping concentration follows an exponential distribution (the exponential factor a in the exponential function y = a ^x is selected as 2). For comparison, an SOI device with a similar structure to the SOI device of this application is used, and the only difference is that the SOI device for comparison (called a comparative SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping) .

Simulation parameters: The source and drain doping is N type, the doping concentration is 1E21cm ^-3 , the channel doping is P type, the doping concentration is 1E17cm ^-3 , the channel length L _g is 130nm, and the effective channel length L _eff is 70nm, the length of the equivalent source region L _es and the equivalent drain region L _ed is both 30nm, the thickness of the active layer is 50nm, and the thickness of the gate insulating layer is 5nm, forming a fixed charge at the interface between the equivalent source region and the equivalent drain region The areal density is 1E14cm ^-2 .

Refer to Figure 30, which is a comparison diagram of the transfer characteristics of the SOI device of the present application and the comparative SOI device when the drain terminal voltage _Vd is 2V. It can be seen that in the SOI device of the present application, when the entire channel is doped and the third region is forward doped, the ability to suppress the short channel effect is the strongest.

Refer to Figure 31, which is a comparison chart of the output characteristics of the SOI device of the present application and the comparative SOI device when the gate terminal voltage V _g is 2.5V. It can be seen that when the entire channel is doped in the SOI device of the present application, the saturation voltage V _dsat and the saturation current I _dsat can be improved, and a larger kink voltage and output impedance _Ro can be obtained.

Simulation example 4

In Simulation Example 4, the SOI device applying the above-mentioned embodiments/examples of the present application is called the "SOI device of the present application", wherein the SOI device of the present application is located in the first region near one end of the equivalent source region away from the source region. and perform forward doping (for) and reverse doping (rev) in the third region (the doped region covers the end of the equivalent source region away from the source region), and the doping depth is 0.75 times the thickness of the channel region, And the doping concentration follows an exponential distribution (the exponential factor a in the exponential function y = a ^x is selected as 2). For comparison, an SOI device with a similar structure to the SOI device of this application is used, and the only difference is that the SOI device for comparison (called a comparative SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping) .

Refer to Figure 32, which is a comparison diagram of the transfer characteristics of the SOI device of the present application and the comparative SOI device when the drain terminal voltage _Vd is 2V. It can be seen that in the SOI device of the present application, when the first region and the third region near the end of the equivalent source region away from the source region are forward doped, the ability to suppress the short channel effect is the strongest; while in the corresponding region Compared with forward doping and uniform doping, reverse doping fails to improve the device's ability to suppress the short channel effect.

Refer to Figure 33, which is a comparison chart of the output characteristics of the SOI device of this application and the comparison SOI device when the gate terminal voltage V _g is 2.5V. It can be seen that in the SOI device of the present application, when the first region and the third region near the end of the equivalent source region away from the source region are forward doped, the saturation voltage _Vdsat , saturation current Idsat and While outputting the impedance Ro, a larger kink voltage is obtained; while reverse doping in the corresponding area will cause a loss of larger saturation voltage V _dsat and saturation current I _dsat .

Simulation example 5

In Simulation Example 5, the SOI device applying the above embodiments/examples of the present application is called the "SOI device of the present application", wherein the SOI devices of the present application are: ① Adjacent to the drain in the effective channel length direction in the third region 1/2 of the depth of the region is forward doped and the second region is reverse doped (left65.for_right65.rev), ② the second region is reverse doped (left100.for_right30.rev), ③ the second The 2/3 depth of the adjacent drain region in the direction of the effective channel length is reversely doped (left110.for_right20.rev). The doping depth is 0.75 times the thickness of the channel region, and the doping concentration is distributed according to the exponential ( The exponential factor a in the exponential function y=a ^x is selected 2). For comparison, an SOI device with a similar structure to the SOI device of this application is used, and the only difference is that the SOI device for comparison (called a comparative SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping) .

Refer to Figure 34, which is a comparison diagram of the transfer characteristics of the SOI device of the present application and the comparative SOI device when the drain terminal voltage _Vd is 2V. It can be seen that in the SOI device of this application, the ability to suppress the short channel effect is the strongest when the above-mentioned

doping

② and ③ are used.

Refer to Figure 35, which is a comparison chart of the output characteristics of the SOI device of the present application and the comparative SOI device when the gate terminal voltage V _g is 2.5V. It can be seen that in the SOI device of this application, when

doping

② and ③ as mentioned above, a larger kink voltage can be obtained without almost losing the saturation voltage V _dsat and saturation current I _dsat compared to uniform doping. and output impedance R _o .

Simulation example 6

In Simulation Example 6, the SOI device applying the above-mentioned embodiments/examples of the present application is called the "SOI device of the present application", wherein the SOI device of the present application is: ① The first region and the third region are reversely doped and the third region is reversely doped. Two regions are forward doped (leftrev_ledfor), ② the first region and the third region are forward doped and the second region is reverse doped (leftfor_ledrev), ③ the first region, the second region and the third region are all forward doped Doping (FC.for), the doping depth of

doping

① and ② is 0.75 times the thickness of the channel region, the doping depth of doping ③ is the thickness of the entire channel region, and the doping concentration follows an exponential distribution (exponential function y =The exponential factor a in a ^x is selected 2). For comparison, an SOI device with a similar structure to the SOI device of this application is used, and the only difference is that the SOI device for comparison (called a comparative SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping) .

Refer to Figure 36, which is a comparison diagram of the transfer characteristics of the SOI device of the present application and the comparative SOI device when the drain terminal voltage _Vd is 2V. It can be seen that in the SOI device of this application, when the above-mentioned

doping

② and ③ are used, the relatively uniform doping has better sub-threshold swing, which reflects the improvement of the short channel effect suppression ability; while in the above-mentioned doping ①, the sub-threshold swing of relatively uniform doping is worse.

Refer to Figure 37, which is a comparison chart of the output characteristics of the SOI device of this application and the comparative SOI device when the gate terminal voltage V _g is 2.5V. It can be seen that in the SOI device of this application, when the above-mentioned

doping

② and ③ are also performed, a larger kink voltage and output can be obtained while improving the saturation voltage V _d sat and saturation current Idsat compared with uniform doping. Impedance Ro, and the improvement of doping ② is more significant than that of doping ③; when doping ①, although the saturation voltage V _dsat and saturation current I _dsat can be improved to a certain extent by relatively uniform doping, a larger loss will occur. kink voltage and output impedance _Ro .

Simulation example 7

In Simulation Example 7, the SOI device applying the above embodiments/examples of the present application is called the "SOI device of the present application". The SOI device of the present application is divided into: ① In the direction from the source region to the drain region, in the direction of the drain region, The doping concentration in the three regions gradually decreases (Hor.linear.dec), ② In the direction from the source region to the drain region, the doping concentration in the third region gradually increases (Hor.linear.inc), And the doping concentration follows an exponential distribution (the exponential factor a in the exponential function y = a ^x is selected as 2). For comparison, an SOI device with a similar structure to the SOI device of this application is used, and the only difference is that the SOI device for comparison (called a comparative SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping) .

Refer to Figure 38, which is a comparison diagram of the transfer characteristics of the SOI device of the present application and the comparative SOI device when the drain terminal voltage _Vd is 2V. It can be seen that the SOI device of the present application has improved suppression ability of the short channel effect when

doping

① and ② as mentioned above, and the suppression ability is stronger when doping ①.

Refer to Figure 39, which is a comparison chart of the output characteristics of the SOI device of this application and the comparative SOI device when the gate terminal voltage V _g is 2.5V. It can be seen that when the SOI device of this application is doped with ① and ② as mentioned above, it will lose the saturation voltage V _dsat and saturation current I _dsat compared with uniform doping, but it can obtain a larger kink voltage. At the same time, the kink voltage and output impedance _Ro of doping ① are higher than that of doping ②.

It should be understood that the described embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of the present invention. Those skilled in the art can make various other substitutions, changes and improvements within the scope of the present invention. Therefore, the present invention is not limited to the above-described embodiments, but only by the claims.

Claims

A non-uniformly doped field effect transistor device including an active layer, characterized in that the active layer includes a source region, a drain region and a channel region located between the source region and the drain region ;

When the device is turned on, an effective channel is formed in the channel region, and an equivalent source region and/or an equivalent drain region that is at least far away from the effective channel in the thickness direction of the channel region, said The field effect transistor device connects the source region and the drain region through the effective channel, equivalent source region and equivalent drain region to contribute operating current;

Wherein, in the direction in which the channel region is close to the effective channel:

The doping concentration of at least part of the first region gradually decreases; and/or,

The doping concentration in at least part of the second region gradually increases; and/or,

The doping concentration of at least part of the third region gradually decreases; and/or,

In the direction from the source region to the drain region:

The doping concentration of at least part of the third region gradually decreases;

The first region is a region in the channel region corresponding to the equivalent source region, the second region is a region in the channel region corresponding to the equivalent drain region, and the third region is the The area in the channel region corresponding to the effective channel.
The non-uniformly doped field effect transistor device according to claim 1, characterized in that, in the direction in which the channel region is close to the effective channel:

The doping concentration in the third region and the first region gradually decreases, and the doping concentration in the second region gradually increases; or,

The doping concentration in the third region and the first region gradually decreases, and the doping concentration in the second region is uniformly doped; or,

The doping concentration in the third region gradually decreases, and the first region and the second region are uniformly doped; or,

The doping concentration in the third region, the first region and the second region gradually decreases; or,

The third region is uniformly doped, the doping concentration in the first region gradually decreases, and the doping concentration in the second region gradually increases; or,

The third region and the first region are uniformly doped, and the doping concentration in the second region gradually increases; or,

The third region and the second region are uniformly doped, and the doping concentration in the first region gradually decreases.
The non-uniformly doped field effect transistor device according to claim 1, characterized in that the doping concentration in the first region, the second region and the third region is according to linear distribution, exponential distribution, Gaussian distribution, residual error A change in distribution.
The non-uniformly doped field effect transistor device according to claim 1, wherein a conductive region that is not connected to the source region and the drain region is formed in the channel region; wherein,

When the conductive region is connected to the source region, the conductive region constitutes the equivalent source region; and/or,

When the conductive region is connected to the drain region, the conductive region constitutes the equivalent drain region.
The non-uniformly doped field effect transistor device according to claim 4, characterized in that it includes a first gate electrode disposed on one side surface of the active layer, the first gate electrode and the conductive region are in The vertical projections on the channel region overlap; wherein the first gate can control the channel region and form a channel therein, and the conductive region in the channel is in the channel region. The non-overlapping portions between upper vertical projections constitute the effective channel.
The field effect transistor device according to claim 5, characterized in that when the device is turned on, the conductance of the conductive region is greater than the conductance of the rest of the channel except the effective channel, so that the conductive region and the effective channel At least one of the channels can inject carriers into another of the channels;

Preferably, the conductance of the conductive region is at least three times greater than the conductance of the rest of the channel except the effective channel;

And/or, the field effect transistor device is a planar structure device or a vertical structure device.
The non-uniformly doped field effect transistor device according to claim 5, characterized in that when the device is turned on, the unit length conductance of the effective channel in the channel is less than the unit length of the rest of the channel except the effective channel. Conductance.
The non-uniformly doped field effect transistor device according to claim 5, characterized in that when the field effect transistor device is an N-type device, the work function of the portion of the first gate corresponding to the effective channel is greater than the work function of the remainder of the first gate;

When the field effect transistor device is a P-type device, the work function of the portion of the first gate corresponding to the effective channel is smaller than the work function of the remaining portion of the first gate; and/or,

The field effect transistor device includes a gate insulating layer disposed between the first gate and a channel region, wherein a portion of the gate insulating layer corresponding to the effective channel has a thickness greater than the remaining portion of the gate insulating layer. thickness; and/or,

The field effect transistor device includes a gate insulating layer disposed between the first gate and a channel region, wherein a dielectric constant of a portion of the gate insulating layer corresponding to the effective channel is greater than the remaining portion of the gate. The dielectric constant of the insulating layer.
The non-uniformly doped field effect transistor device according to any one of claims 4 to 8, further comprising a second gate disposed on a surface of the active layer adjacent to the conductive region, the second gate The gate can control the formation of the conductive region in the channel region; and/or,

The conductive region is formed by carriers introduced by surface doping of the channel region on a side away from the effective channel; and/or,

It also includes an insulating layer disposed on a side surface of the active layer away from the effective channel. The conductive region is a carrier generated in the channel region adjacent to the insulating layer by electrostatic induction of the injected charges in the insulating layer. Fluid composition; and/or,

It also includes a semiconductor material layer disposed on a surface of the active layer away from the effective channel. The active layer and the semiconductor material layer form a heterostructure, and the conductive region is distributed in the heterogeneous structure. The structure consists of a two-dimensional electron gas channel or a two-dimensional hole gas channel; and/or,

The conductive region is composed of a two-dimensional electron gas channel or a two-dimensional hole gas channel formed by surface treatment on a side surface of the channel region away from the effective channel.
A non-uniformly doped field effect transistor device including an active layer, characterized in that the active layer includes a source region, a drain region and a channel region located between the source region and the drain region ;

When the device is turned on, an effective channel is formed in the channel region, and an equivalent source region and/or an equivalent drain region that is at least far away from the effective channel in the thickness direction of the channel region, said The field effect transistor device connects the source region and the drain region through the effective channel, equivalent source region and equivalent drain region to contribute operating current;

Wherein, at least part of the channel region is non-uniformly doped, so that a built-in electric field is formed in the channel region that guides carriers to move from the equivalent source region to the effective channel, and/or , a built-in electric field that guides carriers to move from the effective channel to the equivalent drain region.