CN116825820A

CN116825820A - Non-uniformly doped field effect transistor device

Info

Publication number: CN116825820A
Application number: CN202210887594.7A
Authority: CN
Inventors: 王明湘; 郭烨烨; 张冬利; 王槐生
Original assignee: Suzhou University
Current assignee: Suzhou University
Priority date: 2022-07-26
Filing date: 2022-07-26
Publication date: 2023-09-29
Also published as: WO2024021336A1

Abstract

The application discloses a non-uniform doping field effect transistor device, which is used for solving the problem of short channel effect of a field effect transistor in the prior art, wherein when the device is started, an effective channel and an equivalent source region and/or an equivalent drain region which are far away from the effective channel at least in the thickness direction of the channel region are formed in the channel region, and the field effect transistor device is communicated with the source region and the drain region through the effective channel, the equivalent source region and the equivalent drain region so as to contribute working current; wherein in a direction in which the channel region approaches the effective channel: at least part of the doping concentration in the first region gradually decreases; and/or the doping concentration in at least part of the second region is gradually increased; and/or the doping concentration in at least part of the third region is gradually reduced; and/or in a direction in which the source region points to the drain region: at least a portion of the doping concentration in the third region gradually decreases.

Description

Non-uniformly doped field effect transistor device

Technical Field

The application belongs to the technical field of semiconductor devices, and particularly relates to a non-uniformly doped field effect transistor device.

Background

With the development of integrated circuit technology, the gate length (corresponding to the channel length) of field effect transistors is continuously shrinking, and VLSI chips based on submicron or even below 10 nanometer gate length devices are produced in mass. For such small-sized devices, how to cope with their short channel effects is an important challenge for device technology. The short channel effect comprehensively degrades the threshold voltage and sub-threshold characteristics of the small-size device, and the threshold voltage of the small-size device is not constant any more, but decreases along with the decrease of the channel length and decreases along with the increase of the drain terminal voltage of the device; the subthreshold swing of the device transfer characteristics also deteriorates.

The current method for improving the short channel effect of the field effect transistor device mainly comprises fin field effect transistor FinFET, silicon on insulator SOI, lightly Doped Drain (LDD) structure, metal source drain Schottky barrier transistor (SB MOSFET) and the like. (1) The channel region of the FinFET is a 3D fin-shaped sheet, the grid is of a three-side fence structure, the control of the grid on the channel is enhanced by the two side fences, and the short channel effect is effectively restrained. (2) The SOI technology introduces a buried oxide layer between a silicon channel layer and a backing substrate, and can effectively inhibit leakage current between source and drain under the condition of very thin and full depletion of the channel layer. (3) The LDD is arranged near the drain end channel, the source-drain region far away from the channel is still heavily doped, the drain end PN junction formed by the lightly doped region reduces the influence of drain end voltage on the channel, and the LDD is a main flow technical scheme of a submicron-level short channel device, and the on-state current and the field effect mobility of the device in the scheme are both influenced by the LDD to a certain extent. (4) The working current of the Schottky barrier transistor is tunneling current of a Schottky barrier between a metal source and a semiconductor channel, and the Schottky barrier transistor is insensitive to short channel effects.

On the other hand, the occurrence of the king effect on the output characteristic of a short channel device is also receiving much attention. When the device works in a saturated working state, the drain end of the device is exhausted by higher drain voltage to form a high electric field region, the current carrier is easy to generate collision ionization effect, and the current carrier is coupled and amplified with a parasitic bipolar transistor of the MOS device, so that the drain current is rapidly increased along with the increase of the drain voltage to form a so-called king current, the output characteristic curve of the device is greatly warped, and the normal output characteristic is seriously influenced.

Common methods for improving the king effect mainly include increasing the device channel length and Lightly Doped Drain (LDD) structure. Increasing the channel length can reduce the influence of carriers generated by collision ionization of the drain terminal on the source terminal, weaken the parasitic transistor effect and alleviate the king effect. But an increase in channel length correspondingly reduces the output current of the device. The LDD structure can reduce the peak electric field intensity in the drain end depletion region, weaken the carrier collision ionization effect, and therefore inhibit the king effect, but the LDD structure can introduce additional parasitic resistance, and reduce the field effect mobility and on-state current of the device.

The information disclosed in this background section is only for enhancement of understanding of the general background of the application and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The application aims to provide a field effect transistor device which is used for solving the problem of short channel effect of a field effect transistor in the prior art.

In order to achieve the above object, the present application provides a non-uniformly doped field effect transistor device comprising an active layer including a source region, a drain region, and a channel region between the source region and the drain region;

when the device is started, an effective channel and an equivalent source region and/or an equivalent drain region which are far away from the effective channel at least in the thickness direction of the channel region are formed in the channel region, and the field effect transistor device is communicated with the source region and the drain region through the effective channel, the equivalent source region and the equivalent drain region to contribute to working current;

wherein, in a direction in which the channel region approaches the effective channel:

at least part of the doping concentration in the first region gradually decreases; and/or the number of the groups of groups,

at least part of the doping concentration in the second region is gradually increased; and/or the number of the groups of groups,

at least part of the doping concentration in the third region gradually decreases; and/or the number of the groups of groups,

in a direction in which the source region points to the drain region:

At least part of the doping concentration in the third region gradually decreases;

the first region is a region corresponding to an equivalent source region in the channel region, the second region is a region corresponding to an equivalent drain region in the channel region, and the third region is a region corresponding to an effective channel in the channel region.

In one embodiment, in a direction in which the channel region approaches the effective channel:

the doping concentration in the third region and the first region gradually decreases, and the doping concentration in the second region gradually increases; or alternatively, the first and second heat exchangers may be,

the doping concentration in the third region and the first region is gradually reduced, and the second region is uniformly doped; or alternatively, the first and second heat exchangers may be,

the doping concentration in the third region gradually decreases, and the first region and the second region are uniformly doped; or alternatively, the first and second heat exchangers may be,

the doping concentration in the third region, the first region and the second region is gradually reduced; or alternatively, the first and second heat exchangers may be,

the third region is uniformly doped, the doping concentration in the first region is gradually reduced, and the doping concentration in the second region is gradually increased; or alternatively, the first and second heat exchangers may be,

the third region and the first region are uniformly doped, and the doping concentration in the second region is gradually increased; or alternatively, the first and second heat exchangers may be,

And the third region and the second region are uniformly doped, and the doping concentration in the first region is gradually reduced.

In an embodiment, the doping concentrations in the first region, the second region and the third region vary according to one of a linear distribution, an exponential distribution, a gaussian distribution and a residual error distribution.

In one embodiment, a conductive region is formed in the channel region that does not communicate with the source region and the drain region; wherein, the liquid crystal display device comprises a liquid crystal display device,

when the conductive region is communicated with the source region, the conductive region forms the equivalent source region; and/or the number of the groups of groups,

when the conductive region communicates with the drain region, the conductive region constitutes the equivalent drain region.

In one embodiment, the semiconductor device comprises a first grid electrode arranged on one side surface of the active layer, wherein the first grid electrode and the vertical projection of the conductive region on the channel region are overlapped; wherein the first gate electrode controls the channel region and forms a channel therein, and a portion of the channel that does not overlap with the conductive region as it is perpendicularly projected onto the channel region constitutes the effective channel.

In one embodiment, when the device is turned on, the conductance of the conductive region is greater than the conductance of the remainder of the channel other than the active channel, such that at least one of the conductive region and the active channel can inject carriers into the other.

In one embodiment, the conductance of the conductive region is at least three times greater than the conductance of the remainder of the channel other than the effective channel.

In one embodiment, the field effect transistor device is a planar structure device or a vertical structure device.

In one embodiment, when the device is turned on, the conductance per unit length of the effective channel in the channel is less than the conductance per unit length of the remainder of the channel other than the effective channel.

In an embodiment, when the field effect transistor device is an N-type device, a work function of a portion of the first gate corresponding to the effective channel is greater than a work function of the rest of the first gate;

when the field effect transistor device is a P-type device, a work function of a portion of the first gate corresponding to the effective channel is smaller than a work function of the rest of the first gate.

In one embodiment, the field effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein a thickness of a portion of the gate insulating layer corresponding to the effective channel is greater than a thickness of the remaining portion of the gate insulating layer.

In one embodiment, the field effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein a dielectric constant of a portion of the gate insulating layer corresponding to the effective channel is greater than a dielectric constant of the remaining portion of the gate insulating layer.

In an embodiment, the semiconductor device further includes a second gate disposed on a surface of the active layer adjacent to a side of the conductive region, where the second gate controls formation of the conductive region in the channel region.

In one embodiment, the conductive region is formed by doping the channel region with incoming carriers at a side surface remote from the effective channel.

In an embodiment, the semiconductor device further comprises an insulating layer arranged on the surface of the side, away from the effective channel, of the active layer, and the conductive region is composed of carriers generated in the channel region, close to the insulating layer, through electrostatic induction by injected charges in the insulating layer.

In an embodiment, the semiconductor device further comprises a semiconductor material layer arranged on the surface of one side, far away from the effective channel, of the active layer, the active layer and the semiconductor material layer form a heterostructure, and the conductive area is formed by two-dimensional electron gas channels or two-dimensional hole gas channels distributed in the heterostructure.

In an embodiment, the conductive region is formed by a two-dimensional electron gas channel or a two-dimensional hole gas channel formed by surface treatment of a surface of one side of the channel region away from the effective channel.

The application also provides a field effect transistor device comprising an active layer comprising a source region, a drain region and a channel region between the source region and the drain region;

at least part of the channel region is unevenly doped, so that a built-in electric field for guiding carriers to move from the equivalent source region to an effective channel and/or a built-in electric field for guiding carriers to move from the effective channel to an equivalent drain region are formed in the channel region.

Compared with the prior art, in the embodiment of the application, the device is arranged to form an effective channel in the channel region and an equivalent source region and an equivalent drain region which are far away from the effective channel in the thickness direction of the channel region when the device is started, so that the source region and the drain region are communicated to contribute to working current; in this way, the equivalent drain (source) region in communication with the drain (source) region is structurally remote from the effective channel, reducing the effect of drain terminal voltage on the effective channel; and the peak built-in electric field in the drain end depletion region is reduced when the device is in saturated operation, so that the short channel effect of the device is restrained, and the output characteristic of the device is improved.

In another aspect, a built-in electric field for guiding carriers to move from the equivalent source region to the effective channel and/or guiding carriers to move from the effective channel to the equivalent drain region is formed in the channel region through non-uniform doping in the channel region, so that good inhibition capability on short channel effect can be ensured, and the device has smaller saturated drain voltage V _dsat And larger saturation leakage current I _dsat Voltage of king and output impedance R _o 。

Drawings

FIG. 1 is a schematic diagram of a non-uniformly doped field effect transistor device according to an embodiment of the present application in a state in which an equivalent source region, an equivalent drain region, and an effective channel are formed in an on state;

FIG. 2 is a schematic diagram of a non-uniformly doped field effect transistor device in an on state according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating a non-uniformly doped field effect transistor device according to an embodiment of the present application;

fig. 4 to 13 are schematic structural views of non-uniformly doped field effect transistor devices according to various embodiments of the present application;

fig. 14 to 21 are schematic views of the fabrication of conductive regions according to various embodiments of the present application;

fig. 22 to 24 are schematic structural views of an SOI device to which the scheme of the present application is applied;

Fig. 25 is a schematic view of a structure of an active channel of a non-uniformly doped field effect transistor device and a conductive region having a spacing between vertical projections on the channel region according to an embodiment of the present application;

FIG. 26 is a graph showing the transfer characteristics of the devices in simulation example 1;

FIG. 27 is a graph showing comparison of output characteristics of the respective devices in simulation example 1;

FIG. 28 is a graph showing the transfer characteristics of each device in simulation example 2;

FIG. 29 is a graph showing comparison of output characteristics of the respective devices in simulation example 2;

FIG. 30 is a graph showing the transfer characteristics of each device in simulation example 3;

FIG. 31 is a graph showing comparison of output characteristics of the respective devices in simulation example 3;

FIG. 32 is a graph showing the transfer characteristics of each device in simulation example 4;

FIG. 33 is a graph showing comparison of output characteristics of the respective devices in simulation example 4;

FIG. 34 is a graph showing the transfer characteristics of each device in simulation example 5;

FIG. 35 is a graph showing comparison of output characteristics of the respective devices in simulation example 5;

FIG. 36 is a graph showing the transfer characteristics of each device in simulation example 6;

FIG. 37 is a graph showing comparison of output characteristics of the respective devices in simulation example 6;

FIG. 38 is a graph showing the transfer characteristics of each device in simulation example 7;

fig. 39 is a graph showing comparison of output characteristics of each device in simulation example 7.

Detailed Description

The present application will be described in detail below with reference to the embodiments shown in the drawings. The embodiments are not intended to limit the application, but structural, methodological, or functional modifications of the application from those skilled in the art are included within the scope of the application.

Referring to fig. 1, an embodiment of the non-uniformly doped field effect transistor device of the present application will be described. In the present embodiment, the field effect transistor device 100 includes an active layer 10, and the active layer 10 includes a source region 101, a drain region 102, and a channel region 103.

A source region 101 and a drain region 102 are located on both sides of the active layer 10, respectively, and a channel region 103 is located between the source region 101 and the drain region 102. In cooperation with the schematic view of the device shown in fig. 1 when turned on, an effective channel 1041 and equivalent source and drain regions 1051 and 1052 distant to the effective channel 1041 in the thickness direction of the channel region 103 are formed in the channel region 103 of the field effect transistor, and the field effect transistor device 100 communicates with the source and drain regions 101 and 102 through the effective channel 1041, the equivalent source and drain regions 1051 and 1052 to contribute an operating current.

In some embodiments of the application, the "distance" between the effective channel 1041 and the equivalent source and drain regions 1051, 1052 may include a distance in the length direction of the channel region in addition to the thickness direction of the channel region. In these embodiments, whether the channel region is distant in thickness or length, it is limited that the effective channel 1041, the equivalent source region 1051, and the equivalent drain region 1052 are not affected when the device is turned on, and the source region 101 and the drain region 102 are in communication.

In a typical field effect transistor device 100, the source region 101 of the active layer 10 is used to provide carriers when the device is on, while the drain region 102 is used to collect carriers provided by the source region 101. Correspondingly, in the present application, the mentioned equivalent source region 1051 refers to a structure in which part of carriers supplied from the source region 101 are directly injected into the effective channel 1041, and the equivalent drain region 1052 refers to a structure in which part of carriers are directly received from the effective channel 1041 and injected into the drain region 102.

Referring to fig. 2 in conjunction, the "effective channel 1041" referred to in the present application refers to a portion of the channel through which carriers, which are operating current, pass when the device is turned on. Taking the present embodiment as an example, one side surface of the active layer 10 may be provided with the first gate electrode 20, and there is no space between the vertical projection of the first gate electrode 20 on the active layer 10 and the source and drain regions 101 and 102. Thus, when a gate bias is applied to the first gate 20 to turn on the device, a channel 104 may be controlled to be formed under the first gate 20, and the channel 104 is structurally connected to the source region 101 and the drain region 102, respectively. However, from a functional point of view, only the portion of the channel that does not overlap with the vertical projection of the equivalent source region 1051 and the equivalent drain region 1052 onto the channel region 103 is used to transmit the entire operating current, and therefore only this portion of the channel will be referred to as "effective channel 1041" herein.

In this embodiment, the carrier path at device turn-on includes two main parts: one part is from the source region 101 into the equivalent source region 1051, the effective channel 1041, the equivalent drain region 1052, and the drain region 102 in order, and the other part is from the source region 101 directly into the drain region 102 through the channel 104. The remaining portions of the channel 104, excluding the effective channel 1041, are used to transmit only a portion of the operating current as seen in the carrier path.

It can be seen that the effective channel 1041 in the present application is not limited to having a different device structure or parameter set per se than the remainder of the channel 104. Indeed, in some embodiments, the channel 104 may be formed integrally in the channel region, and only through the arrangement of the equivalent source region 1051 and the equivalent drain region 1052, so that when the device is turned on, carriers provided by the source region 101 are not directly injected into the drain region 102 all through the channel 104. While the regulation of the channel, such as changing the work function of the first gate electrode of the corresponding portion of the effective channel, the thickness of the gate insulating layer, etc., which may be shown in some embodiments below, should not be considered as a necessary precondition for forming the effective channel.

The provision of the equivalent source region 1051 and the equivalent drain region 1052 corresponds to shortening the length of the portion of the channel 104 that can fully conduct the operating current, i.e., the effective channel 1041 is spaced from the source region 101 and the drain region 102. And, the equivalent drain region 1052 in communication with the drain region 102 is structurally far from the effective channel 1041, reducing the effect of the drain potential on the effective channel 1041; while the equivalent source region 1051 in communication with the source region 101 is structurally remote from the effective channel 1041, the potential of the equivalent source region 1051 remains coincident with the source region (typically zero potential) and the effect of the drain potential on the effective channel 1041 is likewise reduced to improve the short channel effect of the device.

Referring to fig. 3 in conjunction, in the specific preparation of the equivalent source region 1051 and the equivalent drain region 1052, by forming a conductive region a in the channel region 103 that does not communicate with the source region 101 and the drain region 102, when the conductive region a communicates with the source region 101, the portion of the conductive region a constitutes the equivalent source region 1051; when conductive region a communicates with drain region 102, this portion of conductive region a constitutes an equivalent drain region 1052.

When the device is turned on, the conductance of the conductive region a is set to be greater than the conductance of the remaining portion 1042 of the channel 104 excluding the effective channel 1041, so that carriers can be injected between the conductive region a and the effective channel 1041. In this way, carriers of the source region 101 are attracted by the more conductive equivalent source region 1051 and are not directly injected all the way into the channel 104 to the remainder 1042 of the channel 104 directly connected to the source region 101; also, carriers transported in the active channel 1041 will be attracted by the dummy drain 1052 and will not all be transported through the remainder 1042 of the channel 104.

To achieve the carrier injection arrangement herein between the equivalent source region 1051, the equivalent drain region 1052, and the effective channel 1041, the conductance of the conductive region a may be set to be at least three times greater than the conductance of the remainder 1042 of the channel 104 except for the effective channel 1041. Further, since carriers flow in the thickness direction of the channel region 103 during the above-described "injection", the interval between the conductive region a and the effective channel 1041 in the thickness direction of the channel region 103 in this embodiment may be set to 5nm to 10 μm, or more preferably 10nm to 1 μm, or more preferably 10nm to 100nm according to the specific design of the device, so as to ensure normal injection of carriers and performance of the device.

It should be noted that "carrier" mentioned in the present application refers to a charge particle capable of freely moving in the corresponding polar channel/conductive region a, and generally, we refer to an electron in an N-type channel or a hole in a P-type channel as "carrier" herein, and correspondingly, a hole in an N-type channel or an electron in a P-type channel is not referred to as "carrier" herein, so that the polarities of the effective channel 1041 and the conductive region a are set to be the same in the present application, so that the carrier interaction between the two channels can ultimately substantially contribute to the operation current of the device.

The morphology and location of the conductive regions may be set according to the application requirements of the device and are not limited to the form shown in fig. 3. For example, the conductive region a in the field effect transistor device 200 shown in fig. 4 may be of a region shape having a larger overall thickness and irregularities with respect to fig. 3. As another example, the conductive regions a in the field effect transistor device 300 shown in fig. 5 are not located at the same height in the thickness direction of the channel region.

Referring to fig. 6, in the present embodiment, a region of the channel region 103 corresponding to the equivalent source region 1051 is referred to as a first region S1, a region of the channel region 103 corresponding to the equivalent drain region 1052 is referred to as a second region S2, and a region of the channel region 103 corresponding to the effective channel 1041 is referred to as a third region S3. "corresponding" herein is to be understood as: in the thickness direction of the channel region 103, the channel region 103 is "divided" into three regions by the vertical projections of the equivalent source region 1051, the equivalent drain region 1052, and the effective channel 1041, so that the region divided by the vertical projection of the equivalent source region 1051 is the first region S1, the region divided by the vertical projection of the equivalent drain region 1052 is the second region S2, and the region divided by the vertical projection of the effective channel 1041 is the third region S3.

Note that, in each embodiment of the present application, the "first region S1", "second region S2", and "third region S3" mentioned above do not include the device channel region 103 to form the partial regions of the channel, the equivalent source region 1051, and the equivalent drain region 1052 described above.

Specifically, in the present embodiment, in the direction in which the channel region 103 approaches the effective channel 1041, the doping concentration in at least part of the first region S1 gradually decreases; and/or, the doping concentration in at least part of the second region S2 is gradually increased; and/or the doping concentration in at least part of the third region S3 gradually decreases; and/or the doping concentration in the third region S3 gradually decreases in a direction in which the source region 101 points to the drain region 102.

Note that, in the doping mentioned in the embodiments/examples of the present application, the doping of the channel region should be P-type for the N-type device; similarly, for a P-type device, the doping of its channel region should be N-type.

With continued reference to fig. 6, in embodiments of the present application, the direction in which the channel region 103 approaches the effective channel 1041 is defined as a direction D pointing from the bottom of the channel region 1041 along the thickness direction of the channel region 1041 toward the effective channel.

Taking the example of a gradual decrease in the doping concentration of at least part of the first region S1, the doping in the first region S1 may be a change in the "longitudinal doping depth" in the thickness direction of the channel region 103. For example, the doping in the first region S1 may be a quarter, half, three quarters, or full depth doping to the thickness of the channel region 103.

With reference to fig. 7, again taking the example of a gradual decrease in doping concentration of at least a portion of the first region S1, the doping in the first region S1 may be a change in the "lateral doping width" along the length of the effective channel 1041. For example, the doping in the first region S1 may be a quarter, half, three quarters, or full width doping of the first region S1 along the length of the effective channel 1041.

The doping of at least part of the second region S2 and the third region S3 in the embodiments of the present application may be partially or fully referred to in the description of the doping in the first region above. In addition, the description of the non-uniform doping of the first region S1, the second region S2, and the third region S3 in each embodiment and example of the present application is not a limiting exclusion of the doping of the rest of the channel region 103. For example, where only the first region S1 is defined as being non-uniformly doped, it does not mean that the remainder of the channel region 103 is intrinsic.

Similarly, referring to fig. 8 and 9 in combination, in the direction in which the source region 101 points to the drain region 102, the doping concentration in at least part of the third region S3 gradually decreases, and may be changed in the thickness direction of the channel region 103 by a "longitudinal doping depth" or may be changed in the length direction of the effective channel 1041 by a "lateral doping width", which will not be described herein.

In general, by at least partial non-uniform doping in the channel region 103, a built-in electric field is formed within the channel region 103 that directs carriers from the equivalent source region 1051 to the effective channel 1041 and/or that directs carriers from the effective channel 1041 to the equivalent drain region 1052. Therefore, the doping concentration variations in the first region S1, the second region S2, and the third region S3 mentioned in the present embodiment may be implemented in cooperation with each other. Some exemplary embodiments are given below:

in one embodiment, the doping concentrations in the third region S3 and the first region S1 gradually decrease and the doping concentration in the second region S2 gradually increases in the direction in which the channel region 103 approaches the effective channel 1041. In this embodiment, doping through the third region S3 and the first region S1 provides at least a built-in electric field that directs carriers from the equivalent source region 1051 to the effective channel 1041, and doping through the second region S2 provides a built-in electric field that directs carriers from the effective channel 1041 to the equivalent drain region 1052.

In one embodiment, the doping concentrations in the third region S3 and the first region S1 gradually decrease in the direction in which the channel region 103 approaches the effective channel 1041, and the second region S2 is uniformly doped. In this embodiment, doping through the third region S3 and the first region S1 provides at least a built-in electric field that directs carriers from the equivalent source region 1051 to the effective channel 1041.

In one embodiment, the doping concentration in the third region S3 gradually decreases in the direction in which the channel region 103 approaches the effective channel 1041, and the doping is uniform in the first region S1 and the second region S2. In this embodiment, doping through the third region S3 provides at least a built-in electric field that directs carriers from the equivalent source region 1051 to the effective channel 1041.

In one embodiment, the third region S3 is uniformly doped, the doping concentration in the first region S1 gradually decreases and the doping concentration in the second region S2 gradually increases in the direction in which the channel region 103 approaches the effective channel 1041. In this embodiment, at least a built-in electric field that directs carriers from the equivalent source region 1051 to the effective channel 1041 is provided by doping in the first region S1, and a built-in electric field that directs carriers from the effective channel 1041 to the equivalent drain region 1052 is provided by doping in the second region S2.

In one embodiment, the third region S3 and the first region S1 are uniformly doped, and the doping concentration in the second region S2 gradually increases in the direction in which the channel region 103 approaches the effective channel 1041. In this embodiment, doping through the second region S2 provides at least a built-in electric field that directs carriers from the effective channel 1041 to the equivalent drain region 1052.

In one embodiment, the third region S3 and the second region S2 are uniformly doped, and the doping concentration in the first region S1 gradually decreases in the direction in which the channel region 103 approaches the effective channel 1041. In this embodiment, doping through the first region S1 provides at least a built-in electric field that directs carriers from the equivalent source region 1051 to the effective channel 1041.

In one embodiment, the doping concentrations in the third region S3, the second region S2 and the first region S1 gradually decrease in the direction in which the channel region 103 approaches the effective channel 1041. In this embodiment, doping through the first region S1 and the third region S3 provides at least a built-in electric field that directs carriers from the equivalent source region 1051 to the effective channel 1041.

In one embodiment, the doping concentration in the third region S3 gradually decreases in the direction of the channel region 103 approaching the effective channel 1041, and simultaneously, the doping concentration in the third region S3 gradually decreases in the direction of the source region toward the drain region. In the present embodiment, the doping concentration in the third region S3 has a tendency to gradually change in both directions, and at least a built-in electric field guiding the movement of carriers from the equivalent source region 1051 to the effective channel 1041 and the movement of the effective channel 1041 to the equivalent drain region 1052 may be provided by the third region S3.

In the present embodiment, the doping concentrations in the first region S1, the second region S2, and the third region S3 vary according to one of a linear distribution, an exponential distribution, a gaussian distribution, and a residual error distribution. Also, in some embodiments, the doping concentration in these regions may be made to have a greater rate of change, resulting in a greater built-in electric field that directs carrier movement as described above.

Taking the doping concentrations in the first region S1, the second region S2 and the third region S3 as an example according to an exponential distribution, the exponential factor therein may be set to be larger (i.e., the exponential function y=a ^x Greater) such that at least part of the performance of the device is improved.

In this embodiment, the doping concentration in the channel region 103 may be set to: at the interface adjacent to the channel 104, the mobility of carriers in the corresponding region of the channel 104 is not affected, thereby affecting the formation of the inversion layer and deteriorating the on-characteristics of the device.

Exemplary, for a silicon device, if the doping concentration in channel 104 is 3.5e18cm ^-3 The doping concentration in the channel region 103 at the interface adjacent to the channel 104 may be, for example, 3.5e12cm ^-3 、3.5E13cm ^-3 、5.5E14cm ^-3 Etc.

In the above embodiments, the field effect transistor device of the present application is explained by the field effect transistor device including the equivalent source region and the equivalent drain region at the same time, and in some embodiments, the field effect transistor device may include only the equivalent source region or the equivalent drain region.

Referring to fig. 10, a further embodiment of a field effect transistor device 200 of the present application is described.

Unlike the above-described embodiments, in the present embodiment, at the time of device on, an equivalent drain region is not formed in the channel region 103 at this time. The field effect transistor device 200 communicates with the source region 101 and the drain region 102 through the effective channel 1041, the equivalent source region 1051 to contribute to the operating current.

In this embodiment mode, the influence of the drain potential on the potential in the vicinity of the source of the channel region 103 is reduced by the arrangement of the equivalent source region 1051 alone, thereby improving the short channel effect of the device. Correspondingly, the effective channel 1041 is directly connected to the drain region 102.

When the device is turned on, in carrier transport, a carrier portion provided by the source region 101 enters the equivalent source region 1051, and is injected into the effective channel 1041 from an end of the equivalent source region 1051 remote from the source region 101; carriers flowing through the active channel 1041 are re-injected back into the drain region 102. That is, in this embodiment, only the conductive region unidirectionally injects carriers into the effective channel 1041.

Accordingly, in the channel region of the present embodiment, only the first region S1 corresponding to the equivalent source region 1051 and the third region S3 corresponding to the effective channel 1041 are present. Similarly, in the direction in which the channel region 103 approaches the effective channel 1041, the doping concentration in at least part of the first region S1 gradually decreases; and/or, the doping concentration in at least part of the third region S3 gradually decreases; and/or the doping concentration in the third region S3 gradually decreases in a direction in which the source region 101 points to the drain region 102.

Referring to fig. 11, a further embodiment of a field effect transistor device 300 of the present application is described.

Unlike the above embodiment, in this embodiment, at the time of device on, an equivalent source region is not formed in the channel region 103 at this time. The field effect transistor device 300 communicates with the source region 101 and the drain region 102 through the effective channel 1041, the equivalent drain region 1052 to contribute to the operating current.

In this embodiment mode, the influence of the drain potential on the effective channel 1041 is reduced by the arrangement of the equivalent drain region 1052 alone, thereby improving the short channel effect of the device. Correspondingly, the effective channel 1041 is directly connected to the source region.

In carrier transport, carriers provided by the source region 101 enter the active channel 1041, and a portion of the carriers are injected into the equivalent drain region 1052 from an end of the active channel 1041 remote from the source region 101 and are re-injected back into the drain region 102. That is, in this embodiment, only the effective channel 1041 unidirectionally injects carriers into the conductive region.

Accordingly, in the channel region of the present embodiment, only the second region S2 corresponding to the equivalent drain region 1052 and the third region S3 corresponding to the effective channel 1041 are present. Similarly, in the direction in which the channel region 103 approaches the effective channel 1041, the doping concentration in at least part of the second region S2 gradually increases; and/or, the doping concentration in at least part of the third region S3 gradually decreases; and/or the doping concentration in the third region S3 gradually decreases in a direction in which the source region 101 points to the drain region 102.

In the above embodiments of the field effect transistor device 200, 300, the specific defining and doping manners of the first region S1, the second region S2, and the third region S3 may be described with reference to the embodiments of the field effect transistor device 100, which are not described herein again.

In the above-described embodiment, a structure in which a part of a channel formed by gate control constitutes an effective channel has been shown. In such a structure, in order to further improve the ability of the device to suppress short channel effects, the conductance per unit length of the effective channel in the channel may be set smaller than the conductance per unit length of the rest of the channel except for the effective channel. Some corresponding embodiments are described below.

Referring to fig. 12, a further embodiment of a field effect transistor device 400 of the present application is described.

The field effect transistor device 400 includes an active layer 10 including a source region 101, a drain region 102, and a channel region 103. A source region 101 and a drain region 102 are located on both sides of the active layer 10, respectively, and a channel region 103 is located between the source region 101 and the drain region 102.

An insulating layer 30 and a first gate 20 are sequentially disposed over the channel region, and the thickness of the gate insulating layer 302 corresponding to the effective channel 1041 is greater than the thickness of the remaining gate insulating layer 301. That is, the gate insulating layer 301 at the corresponding portions of the equivalent source region 1051 and the equivalent drain region 1052 is relatively thinned, so that the modulating capability of the corresponding gate of the channel 1042 except the effective channel 1041 to the corresponding partial channel 1042 can be enhanced, and the conductance of the corresponding partial channel 1042 can be increased.

In the present embodiment, the dielectric constant of the gate insulating layer 302 corresponding to the effective channel 1041 may be set to be larger than that of the remaining gate insulating layer 301, so as to further increase the conductance of the channel 1042 other than the effective channel 1041.

Referring to fig. 13, a further embodiment of a field effect transistor device 500 of the present application is described.

The field effect transistor device 500 includes an active layer 10, the active layer 10 including a source region 101, a drain region 102, and a channel region 103. A source region 101 and a drain region 102 are located on both sides of the active layer 10, respectively, and a channel region 103 is located between the source region 101 and the drain region 102.

The first gate 20 is disposed above the channel region 103, and the portion 201 and the rest 202 of the first gate 20 corresponding to the effective channel 1041 are made of different materials, so that the channels formed by the portion 201 and the rest 202 corresponding to the effective channel 201 in the first gate 20 have different modulation capacities, and the conductance of the effective channel 1041 is greater than the conductance of the rest 1042 of the channels 104 except for the effective channel 1041.

In this embodiment, if the field effect transistor device 500 is an N-type device, the work function of the portion 201 of the first gate 20 corresponding to the effective channel 1041 is set to be larger than the work function of the remaining portion 202 of the first gate 20; correspondingly, if the field effect transistor device 500 is a P-type device, the work function of the portion 201 of the first gate 20 corresponding to the effective channel 1041 is set to be smaller than the work function of the remaining portion 202 of the first gate 20.

In particular, in the case of an N-type device, the portion 201 of the first gate 20 corresponding to the effective channel 1041 may be formedMetals of large work function, e.g. gold, platinum, or P-doped (P+) polysilicon, or ITO, ruO of large work function obtained by adjusting the composition of the compounds ₂ WN, moN, etc. as gate materials; the remainder 202 may employ a smaller work function metal such as aluminum, hafnium, titanium, or N-doped (n+) polysilicon, or a smaller work function Ru-Hf, WN, hfN, tiN, taN, taSiN, etc., obtained by tuning the composition of the compound, as the gate material. In the case of a P-type device, the portion 201 of the first gate 20 corresponding to the effective channel 1041 may employ a metal with a smaller work function, such as aluminum, hafnium, titanium, or N-doped (n+) polysilicon, or ru—hf, WN, hfN, tiN, taN, taSiN, etc. with a smaller work function obtained by adjusting the composition of the compound, as the gate material; the remainder 202 may be made of a metal with a larger work function, such as gold, platinum, or P-doped (p+) polysilicon, or ITO, ruO with a larger work function obtained by adjusting the composition of the compound ₂ WN, moN, etc. as gate materials.

The following describes the formation of the first conductive region and the second conductive region in the present application in some specific embodiments:

Example 1

The first conductive region A1 and the second conductive region A2 are formed by doping the channel region 103A with carriers introduced at a side surface remote from the effective channel 1041A.

Correspondingly, referring to fig. 14, in the case of an N-type silicon-based device 100A, the doping concentration of the interface may be varied by doping donor atoms, such as phosphorus, arsenic, etc., at the surface of the channel region 103A remote from the active channel 1041A; referring to fig. 15, in the case of a P-type silicon-based device 100A, the doping concentration of the interface may be varied by doping acceptor atoms, such as boron, at the surface of the channel region 103A remote from the active channel 1041A.

Example 2

Referring to fig. 16 and 17 in combination, the field effect transistor device 100B further includes an insulating layer 40B disposed on a side surface of the active layer 10B remote from the effective channel 1041B, and the conductive region a is formed on a side surface of the channel region by electrostatic induction from injected charges in the insulating layer 40B.

Correspondingly, referring to fig. 16, in the case of an N-type device, this can be achieved by locally injecting positive charges, e.g., h+, holes, in the insulating layer 40B; referring to fig. 17, in the case of a P-type device, this can be achieved by locally injecting negative charges, such as F-, cl-, electrons, etc., into the insulating layer 40B. In this way, a high density of fixed charges is formed in the insulating layer 40B, and carriers of the conductive region a are generated by electrostatic induction at the channel region 103B adjacent to the insulating layer 40B. Here, "local" refers to a partial region of the insulating layer 40B where the conductive region a is to be formed corresponding to the channel region.

In a specific charge injection process, the charge may be injected into the insulating layer 40B at a position more adjacent to the channel region 103B, so that the conductive region a formed in the channel region 103B can store more carriers. Of course, in some other alternative embodiments, a "dual insulating layer" structure may be further used, specifically including a charge trapping layer disposed on the surface of the channel region 103B, and a conventional insulating layer covering the charge trapping layer, where the charge trapping layer may be made of a material that is easier to store charges, or nano-particles of metal or semiconductor are introduced therein, so as to store charges more stably, thereby ensuring stable and controllable carriers in the conductive region.

Example 3

Referring to fig. 18, the field effect transistor device 100C includes a semiconductor material layer 40C disposed on an active layer 10C, the semiconductor material layer 40C and the active layer 10C constituting a heterostructure, and a conductive region a formed of two-dimensional electron gas channels or two-dimensional hole gas channels distributed in the heterostructure.

Specifically, the semiconductor material layer 40C and the active layer 10C have different band gap widths, and the semiconductor material layer 40C may be divided into two parts connected to the source region 101C and the drain region 102C, respectively, so that the formed two-dimensional electron gas channel does not conduct the source and drain regions.

Of course, in some alternative embodiments, the channel region 103C may be further surface treated to form a two-dimensional electron gas channel or a two-dimensional hole gas channel, which are well known to those skilled in the art, and are within the scope of the present application. Also, the semiconductor material layer 40C may be a barrier layer, which may be doped or intrinsic.

Example 4

Referring to fig. 19, a field effect transistor device 100D is fabricated as a device including at least two gates. Specifically, the field effect transistor device 100D includes a first gate insulating layer 30D and a first gate electrode 20D sequentially disposed on one side surface of the active layer 10D, and a second gate insulating layer 40D and a second gate electrode 50D sequentially disposed on one side surface of the active layer 10D adjacent to the conductive region a.

The second gate 50D is correspondingly divided into two parts, one part of the vertical projection on the active layer 10D being connected to the source region 101D and the other part of the vertical projection on the active layer 10D being connected to the drain region 102D. Thus, when an appropriate bias is applied to the two portions of the second gate 50D, conductive regions a communicating with the source region 101D and communicating with the drain region 102D can be formed at corresponding positions in the channel region 103D, respectively.

In this embodiment, the absolute value of the bias voltage applied to the second gate 50D should be greater than the absolute value of the turn-on voltage applied to the device. Correspondingly, if an N-type device, a positive bias greater than the first gate 20D is applied to the second gate 50D; in the case of a P-type device, a negative bias voltage is applied to the second gate 50D that is greater in absolute value than the first gate 20D.

Example 5

Referring to fig. 20, a field effect transistor device 100E is fabricated to include at least two gates similar to embodiment 4. However, in this embodiment, in order to enable the conductance of the conductive region a to be larger than the conductance of the portion 1042E of the channel 104E other than the effective channel 1041E, the first gate 20E and the second gate 50E of different work function gate materials may be used. Namely: the work function difference between the first gate electrode 20E and the active layer 10E and the work function difference between the second gate electrode 50E and the active layer 10E are not equal.

Correspondingly, in the case of an N-type device, the first gate 20E may be made of a metal with a larger work function, such as gold, platinum, or P-doped (P+) polysilicon, or ITO, ruO2 with a larger work function obtained by adjusting the composition of the compoundWN, moN, etc. as gate materials; the second gate 50E may employ a metal of a smaller work function such as aluminum, hafnium, titanium, or N-doped (n+) polysilicon, or Ru-Hf, WN, hfN, tiN, taN, taSiN, etc. of a smaller work function obtained by adjusting the composition of the compound, as the gate material. In the case of a P-type device, the first gate 20E may employ a metal with a smaller work function, such as aluminum, hafnium, titanium, or N-doped (n+) polysilicon, or ru—hf, WN, hfN, tiN, taN, taSiN, etc. with a smaller work function obtained by adjusting the composition of the compound, as the gate material; the second gate 50E may employ a metal with a larger work function such as gold, platinum, or P-doped (P+) polysilicon, or ITO, ruO with a larger work function obtained by adjusting the composition of the compound ₂ WN, moN, etc. as gate materials.

In the N-type device, the difference between the work function of the first gate 20E and the work function of the active layer 10E may be greater than zero (Φms > 0V), so that the channel 104E is an enhanced channel; meanwhile, the work function difference between the second gate electrode 50E and the active layer 10E is set to be smaller than zero (Φms < 0V), so that the conductive region a can form a certain number of carriers under the bias applied thereto in the device off state. In a P-type device, the work function difference between the first gate 20E and the active layer may be set to be less than zero (Φms < 0V), so that the channel 104E is an enhanced channel; meanwhile, the work function difference between the second gate electrode 50E and the active layer 10E is set to be greater than zero (Φms > 0V), so that the conductive region a can form a certain number of carriers under the bias applied thereto in the device off state.

Example 6

Referring to fig. 21, a field effect transistor device 100F is fabricated to include at least two gates 20F, 50F similar to embodiment 4. However, in the present embodiment, in order to enable the conductance of the conductive region a to be larger than the conductance of the portion 1042F of the channel 104F other than the effective channel 1041F, the capacitance per unit area of the second gate insulating layer 40F may be set larger than the capacitance per unit area of the first gate insulating layer 30F.

Specifically, this can be achieved by adjusting the dielectric constants of the first gate insulating layer 30F and the second gate insulating layer 40F, or the thicknesses of the first gate insulating layer 30F and the second gate insulating layer 40F.

For example, when the thicknesses of the first gate insulating layer 30F and the second gate insulating layer 40F are equal, only the dielectric constant factor of the gate insulating layer may be considered, and the dielectric constant of the first gate insulating layer 30F higher than the dielectric constant of the second gate insulating layer 40F may be set. Illustratively, the first gate insulating layer 30F may employ silicon dioxide, and the second gate insulating layer 40F may employ a high-permittivity dielectric such as hafnium oxide, aluminum oxide, or the like.

For another example, when the first gate insulating layer 30F and the second gate insulating layer 40F are made of the same material, only the thickness of the gate insulating layer may be considered, and the thickness of the second gate insulating layer 40F may be set smaller than that of the first gate insulating layer 30F.

In a specific device application, the second gate in embodiments 4 to 6 may also be directly floating or grounded, so as to avoid excessive device connection terminals increasing the complexity of the device application.

In addition, the conductive regions may be formed by combining the conductive regions in the above embodiments, so as to achieve a better implementation effect.

The field effect transistor devices described in the above embodiments/examples may be planar structure devices or vertical structure devices. The specific arrangement of the scheme of the present application when applied to an SOI device will be exemplarily described below taking an SOI device (TFT device) as an example.

Example 7

Referring to fig. 22, a TFT device 100G having a planar top gate structure includes a light-transmitting insulating substrate 40G, and an active layer 10G, a gate dielectric layer 30G, and a gate electrode 20G sequentially disposed on the substrate 40G. The two sides of the active layer 10G are doped to form a source region 101G and a drain region 102G respectively, and are externally connected with a source electrode and a drain electrode respectively; the channel region 103G is located between the source region 101G and the drain region 102G.

Positive charge regions 60G are formed on the substrate 40G on both sides of the source region 101G and the drain region 102G by ion implantation or the like. The positive charge region 60G and the gate electrode 20G have an overlapping portion between the vertical projections of the channel region 103G, and correspondingly, the positive charge region of the overlapping portion may form a two-dimensional electron gas 70G in the channel region 103G connected to the source region 101G and the drain region 102G, respectively, where the two-dimensional electron gas 70G also forms a conductive region, and the carrier blocking region 80G is formed between the two-dimensional electron gas 70G connected to the source region 101G and the drain region 102G.

When the device is turned on, a channel is formed under the gate 20G, and the portion of the channel that is vertically projected between the conductive regions constitutes the actual effective channel.

Example 8

Referring to fig. 23, a TFT device 100H having a planar bottom gate structure includes a light-transmitting insulating substrate 40H, and a gate electrode 20H, a gate dielectric layer 30H, and an active layer 10H sequentially disposed on the substrate 40H. In this embodiment, the upper metal source electrode 501H and the metal drain electrode 502H are disposed on two sides of the active layer 10H, respectively, and the active layer 10H may be an amorphous IGZO metal oxide semiconductor layer, and ohmic contacts are formed between the source electrode 501H and the drain electrode 502H and the active layer 10H. The portions of the active layer under the source electrode 501H and the drain electrode 502H respectively form a source region and a drain region, and the channel region is located between the source region and the drain region.

Positive charge regions 60H respectively connecting the source electrode 501H and the drain electrode 502H are implanted by ions in a passivation layer overlying the device. The positive charge region 60H and the gate electrode 20H have an overlapping portion between the vertical projections of the channel region, and correspondingly, the positive charge region of the overlapping portion may form a two-dimensional electron gas 70H in the channel region connected to the source region and the drain region, respectively, where the two-dimensional electron gas 70H also constitutes a conductive region, and the carrier blocking region 80H is formed between the two-dimensional electron gas 70H connected to the source region and the drain region.

When the device is turned on, the gate 20H forms a channel over which the portion of the vertical projection that lies between the conductive regions 70H forms a virtually effective channel.

Example 9

Referring to fig. 24, the SOI device 100I having a vertical structure includes a substrate 60I, a buried insulating layer 50I and an active layer 10I sequentially provided on the substrate 60I, a gate insulating layer 30I provided on one side of the active layer 10I, and a gate electrode 20I. The source region 101I and the drain region 102I are located below and above the active layer 10I, respectively, in a direction away from the substrate 60I. The channel region 103I has an equivalent source region 1051I communicating with the source region 101I and an equivalent drain region 1052I communicating with the drain region 102I.

When a bias is applied to the gate 20I of the device to turn the device on, the gate 20I controls the formation of a channel 104I connecting the source region 101I and the drain region 102I in the channel region 103I of the device, but only the portion of the channel 104I that does not overlap between the perpendicular projections of the equivalent source region 1051I and the equivalent drain region 1052I on the channel region 103I constitutes an effective channel 1041I for transmitting an operating current when the device is turned on, i.e., the remaining portion 1042I of the channel 104I is not for transmitting an operating current when the device is turned on.

In the foregoing embodiments/examples, the source region and the drain region in the device may be a common heavily doped semiconductor source/drain, or may be a schottky metal source/drain of a metal-semiconductor structure; the grid electrode can be a common metal-insulating layer-semiconductor MOS structure grid electrode or a Schottky junction grid electrode of a metal semiconductor structure; the active layer may be formed of a single semiconductor material or may include at least two semiconductor materials varying in a thickness direction or a plane extending direction thereof to form a composite channel.

And the equivalent source region and the equivalent drain region may be formed spontaneously or by gate control of corresponding structures.

In general, in the above-described embodiments, the vertical projection of the effective channel, the equivalent source region, and/or the equivalent drain region superimposed on the channel region communicates with the source region and the drain region, so as to ensure that carriers of the effective channel and the equivalent source region and/or the equivalent drain region can be injected unidirectionally or bidirectionally at least in the thickness direction, and construct a carrier path from the source region to the drain region. Of course, referring to fig. 25, the present application is not limited to the specific embodiments, and such embodiments are intended to be within the scope of the present application if the vertical projection of the effective channel, the equivalent source region, and the equivalent drain region superimposed on the channel region 103J does not allow the source region 101J and the drain region 102J of the device 100J to communicate, but rather has a "proper spacing" that does not completely shut off the passage of carriers from the equivalent source region 1051J to the effective channel 1041J and from the effective channel 1041J to the equivalent drain region 1052J, and the injection direction of carriers between the effective channel 1041J, the equivalent source region 1051J, and the equivalent drain region 1052J forms an angle with the thickness direction of the channel region 103J.

The following is the result of performing Silvaco TCAD simulation verification by applying the SOI device of the above embodiment/example of the present application. The gradual decrease of the doping concentration in the direction of the channel region near the effective channel is called "forward doping", and the gradual increase of the doping concentration in the direction of the channel region near the effective channel is called "reverse doping".

Simulation example 1

In simulation example 1, an SOI device to which the above-described embodiment/example of the present application is applied is referred to as an "SOI device of the present application", in which the SOI device of the present application is forward doped in the entire channel region, and the doping concentration is distributed in accordance with an exponential (exponential function y=a ^x The exponential factor a of (1.5), 2, 3). As a comparison, an SOI device having a similar structure to the SOI device of the present application was used, and the difference was only that the SOI device as a comparison (referred to as a comparison SOI device in this simulation example) did not have the above-described variation in doping concentration (uniform doping).

Simulation parameters: the source and drain doping is N type, the doping concentration is 1E21cm ^-3 The channel is doped with P type, the doping concentration is 1E17cm ^-3 Channel length L _g 130nm, effective channel length L _eff 70nm equivalent source region L _es And equivalent drain region L _ed The length is 30nm, the thickness of the active layer is 50nm, the thickness of the gate insulating layer is 5nm, and the fixed charge surface density at the interface of the equivalent source region and the equivalent drain region is 1E14cm ^-2 。

Referring to FIG. 26, the voltages V at the drain terminals of the SOI device of the present application and the comparative SOI device are shown _d Transfer characteristics at 2V are compared. It can be seen that the SOI device of the application has stronger short channel effect inhibition capability than the comparison SOI device, and the larger the index factor is, the smaller the subthreshold swing is, and short channel effect inhibition is performedThe stronger the capability.

Referring to FIG. 27, the gate voltage V of the SOI device of the present application and a comparative SOI device _g The output characteristics at 2.5V are compared with each other. It can be seen that the greater the index factor of the SOI device of the present application, the higher the saturation voltage V _dsat And saturation current I _dsat Will have a certain improvement and will lose the king voltage and the output impedance R _o 。

Simulation example 2

In simulation example 2, an SOI device to which the above-described embodiment/example of the present application is applied is referred to as an "SOI device of the present application", in which the SOI device of the present application is forward doped in the entire channel region, and the doping concentration is distributed in accordance with an exponential (exponential function y=a ^x The exponential factor a of (2) is selected). The doping depths are 0.25 times, 0.5 times, 0.75 times and full depth doping in the thickness direction of the channel region, respectively.

Referring to FIG. 28, the voltage V at the drain terminal of the SOI device of the present application is shown _d Transfer characteristics at 2V are compared. It can be seen that the SOI device has better short channel effect inhibition capability after the doping depth reaches more than 0.5 times of the thickness of the channel region, and the subthreshold swing is close, namely, the doping depth is more than or equal to 0.5 times of the thickness of the channel region.

Referring to FIG. 29, the voltage V at the gate terminal of the SOI device of the present application is shown _g The output characteristics at 2.5V are compared with each other. It can be seen that the saturation voltage V of the SOI device of the present application is less than 0.5 times the channel region thickness _dsat And saturation current I _dsat Almost no loss is observed, but there is a significant loss in the kine voltage.

Simulation example 3

In simulation example 3, an SOI device to which the above embodiments/examples of the present application are applied is referred to as an "SOI device of the present application", in which the SOI device of the present application is forward doped in the entire channel region (fc.for), forward doped in the first region (les.for), forward doped in the second region (led.for), forward doped in the third region (leff.for), the doping depth is the entire channel region thickness, and the doping concentration is distributed in accordance with an exponential (exponential function y=a ^x The exponential factor a of (2) is selected). As a comparison, an SOI device having a similar structure to the SOI device of the present application was used, and the difference was only that the SOI device as a comparison (referred to as a comparison SOI device in this simulation example) did not have the above-described variation in doping concentration (uniform doping).

Referring to FIG. 30, the voltages V at the drain terminals of the SOI device of the present application and the reference SOI device are shown _d Transfer characteristics at 2V are compared. It can be seen that the SOI device of the present application has the greatest suppression of short channel effects when doped throughout the channel and doped forward in the third region.

Referring to FIG. 31, the gate voltage V of the SOI device of the present application and a comparative SOI device _g The output characteristics at 2.5V are compared with each other. It can be seen that the saturation voltage V can be improved when the whole channel is doped in the SOI device of the present application _dsat And saturation current I _dsat And obtain a larger king voltage and output impedance R _o 。

Simulation example 4

In simulation example 4, an SOI device to which the above embodiments/examples of the present application are applied is referred to as an "SOI device of the present application", in which the present applicationThe SOI device is doped forward (for) and reverse (rev) in a first region and a third region, respectively, near an end of the equivalent source region remote from the source region (the doped region covers the end of the equivalent source region remote from the source region), the doping depth is 0.75 times the thickness of the channel region, and the doping concentration is distributed according to an exponential (exponential function y=a ^x The exponential factor a of (2) is selected). As a comparison, an SOI device having a similar structure to the SOI device of the present application was used, and the difference was only that the SOI device as a comparison (referred to as a comparison SOI device in this simulation example) did not have the above-described variation in doping concentration (uniform doping).

Referring to FIG. 32, the voltages V at the drain terminals of the SOI device of the present application and the comparative SOI device are shown _d Transfer characteristics at 2V are compared. It can be seen that the suppression capability to the short channel effect is strongest when the first region and the third region near one end of the equivalent source region far away from the source region are doped in the forward direction in the SOI device; the opposite doping in the corresponding region, relative to the forward doping and the uniform doping, can not improve the inhibition capability of the device short channel effect.

Referring to FIG. 33, the gate voltages V of the SOI device of the present application and the comparative SOI device, respectively _g The output characteristics at 2.5V are compared with each other. It can be seen that the saturation voltage V can be hardly lost when the first region and the third region near the end of the equivalent source region far from the source region are doped positively in the SOI device _d At the same time of sat, saturation current Idsat and output impedance Ro, obtaining larger kine voltage; the counter doping in the corresponding region will lose a larger saturation voltage V _dsat And saturation current I _dsat 。

Simulation example 5

In simulation example 5, an SOI device to which the above-described embodiments/examples of the present application are applied is referred to as "the SOI device of the present application", wherein the SOI devices of the present application are each: (1) forward doping is performed in the third region at a depth of 1/2 of the effective channel length direction adjacent to the drain region and reverse doping is performed in the second region (left65.for_right 65. Rev), (2) reverse doping is performed in the second region (left100.for_right 30. Rev), (3) reverse doping is performed in the second region at a depth of 2/3 of the effective channel length direction adjacent to the drain region (left110.for_right 20. Rev), the doping depth is 0.75 times the thickness of the channel region, and the doping concentration is distributed according to an index (exponential function y=a ^x The exponential factor a of (2) is selected). As a comparison, an SOI device having a similar structure to the SOI device of the present application was used, and the difference was only that the SOI device as a comparison (referred to as a comparison SOI device in this simulation example) did not have the above-described variation in doping concentration (uniform doping).

Referring to FIG. 34, the voltages V at the drain terminals of the SOI device of the present application and the comparative SOI device are shown _d Transfer characteristics at 2V are compared. It can be seen that the suppression ability against short channel effects is strongest in the above doping (2) and (3) in the SOI device of the present application.

Referring to FIG. 35, the gate voltage V of the SOI device of the present application and a reference SOI device _g The output characteristics at 2.5V are compared with each other. It can be seen that the saturation voltage V is hardly lost in the SOI device of the present application when compared with the uniform doping, as in the doping (2) and (3) described above _dsat Saturation current I _dsat In the case of (a), a large king voltage and output impedance R are obtained _o 。

Simulation example 6

In simulation example 6, an SOI device to which the above-described embodiments/examples of the present application are applied is referred to as "the SOI device of the present application", wherein the SOI devices of the present application are each: (1) the first and third regions are counter-doped and the second region is forward doped (leftrev_ledfor), (2) the first and third regions are forward doped and the second region is counter-doped (leftrev_ledev), (3) the first, second and third regions are all forward doped (fc.for), the doping depth of the doping (1) and (2) is 0.75 times the thickness of the channel region, the doping depth of the doping (3) is the entire thickness of the channel region, and the doping concentration is according to an exponential profile (exponential function y=a ^x The exponential factor a of (2) is selected). As a comparison, an SOI device having a similar structure to the SOI device of the present application was used, and the difference was only that the SOI device as a comparison (referred to as a comparison SOI device in this simulation example) did not have the above-described variation in doping concentration (uniform doping).

Referring to FIG. 36, the voltages V at the drain terminals of the SOI device of the present application and the comparative SOI device are shown _d Transfer characteristics at 2V are compared. It can be seen that the relatively uniform doping in the SOI device has better subthreshold swing during the doping (2) and (3), and shows better improvement of short channel effect inhibition capability; whereas in the above doping (1), the subthreshold swing of the relatively uniform doping is worse.

Referring to FIG. 37, the gate voltage V of the SOI device of the present application and the comparative SOI device _g The output characteristics at 2.5V are compared with each other. It can be seen that the saturation voltage V can be improved compared to the uniform doping also in the SOI device of the present application when the doping (2) and (3) are described above _d In the case of sat and saturation current Idsat,obtaining larger king voltage and output impedance Ro, and improving doping (2) relative to doping (3) more remarkably; while in the case of the above-mentioned doping (1), the saturation voltage V can be improved to a certain extent although relatively uniform doping is possible _dsat Saturation current I _dsat But with a larger loss of the kine voltage and the output impedance R _o 。

Simulation example 7

In simulation example 7, the SOI device to which the above embodiments/examples of the present application are applied is referred to as "the SOI device of the present application", and the SOI device of the present application is divided into: (1) the doping concentration in the third region gradually decreases (hor.linear.dec) in the direction of the source region toward the drain region, (2) the doping concentration in the third region gradually increases (hor.linear.inc) in the direction of the source region toward the drain region, and the doping concentration is distributed according to an index (exponential function y=a) ^x The exponential factor a of (2) is selected). As a comparison, an SOI device having a similar structure to the SOI device of the present application was used, and the difference was only that the SOI device as a comparison (referred to as a comparison SOI device in this simulation example) did not have the above-described variation in doping concentration (uniform doping).

Referring to FIG. 38, the voltages V at the drain terminals of the SOI device of the present application and the comparative SOI device are shown _d Transfer characteristics at 2V are compared. It can be seen that the SOI device of the present application has improved suppression capability for short channel effect in both doping (1) and (2), and has stronger suppression capability in doping (1).

Referring to FIG. 39, the gate voltage V of the SOI device of the present application and the comparative SOI device _g The output characteristics at 2.5V are compared with each other. It can be seen that the SOI device of the present application is superior to the uniform doping in doping (1) and (2)Saturation voltage of impurity loss V _dsat Saturation current I _dsat But a larger kine voltage may be obtained. At the same time, the kine voltage and the output impedance R of the doping (1) relative to the doping (2) _o Higher.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements or structures, these described elements should not be limited by these terms. These terms are only used to distinguish one such descriptive object from another. For example, a first channel may be referred to as a second channel, and similarly a second channel may also be referred to as a first channel, without departing from the scope of the application.

Also, the same reference numerals or labels may be used in different embodiments, but this does not represent a structural or functional association but is merely for convenience of description.

Terms such as "upper," "lower," and the like used herein to refer to a spatially relative position are used for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. The term spatially relative position may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

When an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on, connected to, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" another element or layer, there are no intervening elements or layers present.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment contains only one independent technical solution, and that such description is provided for clarity only, and that the technical solutions of the embodiments may be appropriately combined to form other embodiments that will be understood by those skilled in the art.

Claims

1. A non-uniformly doped field effect transistor device comprising an active layer, wherein the active layer comprises a source region, a drain region, and a channel region between the source region and the drain region;

in a direction in which the source region points to the drain region:

2. The non-uniformly doped field effect transistor device of claim 1, wherein in a direction in which the channel region is proximate to the effective channel:

3. The non-uniformly doped field effect transistor device of claim 1, wherein the doping concentration in the first, second and third regions varies according to one of a linear profile, an exponential profile, a gaussian profile, a residual error profile.

4. The non-uniformly doped field effect transistor device of claim 1, wherein a conductive region is formed in the channel region that does not communicate with the source and drain regions; wherein, the liquid crystal display device comprises a liquid crystal display device,

5. The non-uniformly doped field effect transistor device of claim 4, comprising a first gate disposed on a side surface of the active layer, the first gate and the vertical projection of the conductive region onto the channel region overlapping; wherein the first gate electrode controls the channel region and forms a channel therein, and a portion of the channel that does not overlap with the conductive region as it is perpendicularly projected onto the channel region constitutes the effective channel.

6. The field effect transistor device of claim 5, wherein when the device is turned on, the conductance of said conductive region is greater than the conductance of the remainder of said channel other than the effective channel, such that at least one of said conductive region and the effective channel can inject carriers into the other of said conductive region and the effective channel;

Preferably, the conductance of the conductive region is at least three times greater than the conductance of the remainder of the channel other than the effective channel;

and/or the field effect transistor device is a planar structure device or a vertical structure device.

7. The non-uniformly doped field effect transistor device of claim 5, wherein when the device is turned on, the conductance per unit length of an effective channel in the channels is less than the conductance per unit length of the rest of the channels except for the effective channel.

8. The non-uniformly doped field effect transistor device of claim 5, wherein when the field effect transistor device is an N-type device, a work function of a portion of the first gate corresponding to an effective channel is greater than a work function of a remaining portion of the first gate;

when the field effect transistor device is a P-type device, the work function of a part corresponding to the effective channel in the first gate is smaller than that of the rest part of the first gate; and/or the number of the groups of groups,

the field effect transistor device comprises a gate insulating layer arranged between the first gate and the channel region, wherein the thickness of a part corresponding to the effective channel in the gate insulating layer is larger than that of the rest part of the gate insulating layer; and/or the number of the groups of groups,

The field effect transistor device comprises a gate insulating layer arranged between the first gate electrode and the channel region, wherein the dielectric constant of a part corresponding to the effective channel in the gate insulating layer is larger than that of the rest part of the gate insulating layer.

9. The non-uniformly doped field effect transistor device of any of claims 4 to 8, further comprising a second gate disposed on a side surface of said active layer adjacent to a conductive region, said second gate being operable to control formation of said conductive region in said channel region; and/or the number of the groups of groups,

the conductive region is formed by doping introduced carriers on the surface of one side of the channel region far from the effective channel; and/or the number of the groups of groups,

the conductive region is formed by carriers generated at the position, close to the insulating layer, of the channel region by electrostatic induction through injected charges in the insulating layer; and/or the number of the groups of groups,

the semiconductor material layer is arranged on the surface of one side, far away from the effective channel, of the active layer, the active layer and the semiconductor material layer form a heterostructure, and the conductive area is formed by two-dimensional electron gas channels or two-dimensional hole gas channels distributed in the heterostructure; and/or the number of the groups of groups,

The conductive region is composed of a two-dimensional electron gas channel or a two-dimensional hole gas channel formed by surface treatment of the surface of one side of the channel region away from the effective channel.

10. A non-uniformly doped field effect transistor device comprising an active layer, wherein the active layer comprises a source region, a drain region, and a channel region between the source region and the drain region;