JPS61214477A - Mos type semiconductor device - Google Patents
Mos type semiconductor deviceInfo
- Publication number
- JPS61214477A JPS61214477A JP5736085A JP5736085A JPS61214477A JP S61214477 A JPS61214477 A JP S61214477A JP 5736085 A JP5736085 A JP 5736085A JP 5736085 A JP5736085 A JP 5736085A JP S61214477 A JPS61214477 A JP S61214477A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- concentration
- impurity
- semiconductor layer
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 239000012535 impurity Substances 0.000 claims abstract description 107
- 239000000758 substrate Substances 0.000 claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- 239000000969 carrier Substances 0.000 abstract description 12
- 230000003313 weakening effect Effects 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 12
- 230000005684 electric field Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241001504505 Troglodytes troglodytes Species 0.000 description 1
- 150000001793 charged compounds Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明はＭＯＳ型半導体装置に関し、特に微細化、高
耐圧化、高速化および信頼性の高度化が図れるＭＯＳ型
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type semiconductor device, and particularly to a MOS type semiconductor device that can be miniaturized, increased in voltage resistance, increased in speed, and improved in reliability.
［従来の技術］
従来、ＭＯＳ電界効果トランジスタ（以下ＭＯＳＦＥＴ
と記す）の微細化のた・めにＬＤＤ（ＬＩＯｈｔ＋ｙ
Ｑ ｏｐｅｄ ＤＩＨｕｓｉｏｎ）構造（低濃度拡
散層を有する構造）や、Ｇｒａｄｅｄ Ｊｕｎｃｔｉ
ｏｎ （傾斜型接合）構造が使用されている。[Prior art] Conventionally, MOS field effect transistors (hereinafter referred to as MOSFETs)
LDD (LIOht+y
Q oped DIHusion structure (structure with low concentration diffusion layer), Graded Junction
on (slanted junction) structure is used.
第１図はＬＯＯ構造のＭＯＳＦＥＴを示す断面図である
。図において、ｐ形シリコン基板１上の一部にソース用
高濃度ｎ＋不純物層２．低濃度ｎ−不純物層４が形成さ
れており、またｐ形シリコン基板１上の他の一部に低濃
度ｎ−不純物層４と間隔を隔てて低濃度ｎ−不純物層５
．ドレイン円高濃度ｎ＋不純物層３が形成されている。FIG. 1 is a sectional view showing a MOSFET with an LOO structure. In the figure, a high concentration n+ impurity layer 2 for source is formed on a part of a p-type silicon substrate 1. A low concentration n-impurity layer 4 is formed, and a low concentration n-impurity layer 5 is formed on another part of the p-type silicon substrate 1 with a spacing therebetween.
．． A drain circle high concentration n+ impurity layer 3 is formed.
６はゲート絶縁膜であり、７はゲート電極である。6 is a gate insulating film, and 7 is a gate electrode.
第２図＆ｔ Ｇ ｒａｄｅｄ Ｊ ｕｎｃｔｉｏｎ構造
のＭＯＳＦＥＴを示す断面図である。図において、ｐ形
シリコン基板１上の一部に低濃度ｎ−不純物［４が形成
されており、この不純物層上にソース用高濃度ｎ１不純
物層２が形成されている。またｐ形シリコン基板１上の
他の一部に低部［ｎ−不純物層４と間隔を隔てて低濃度
ｎ−不純物層５が形成されており、この不純物層上にド
レイン円高濃度ｎ＋不純物層３が形成されている。FIG. 2 is a sectional view showing a MOSFET having a graded junction structure. In the figure, a low concentration n- impurity [4] is formed on a part of a p-type silicon substrate 1, and a high concentration n1 impurity layer 2 for source is formed on this impurity layer. In addition, a low concentration n- impurity layer 5 is formed in another part of the p-type silicon substrate 1 at a distance from the n- impurity layer 4, and a drain circle with a high concentration n+ impurity layer is formed on this impurity layer. Layer 3 is formed.
これらの構造の特徴は、ソース円高濃度ｎ＋不純物層２
およびドレイン用高引Ｉ＋不純物層３のまわりの一部に
あるいはまわり全体に低濃度ｎ−不純物層４Ｆ３よび低
濃度ｎ−不純物層５を付加した点であり、その利点とし
ては、低濃度ｎ−不純物層５によってドレイン円高濃度
ｎ＋不純物層３の空乏層が広がってこの空乏層内での電
界強度が弱くなり、このためソース・ドレイン耐圧の向
上とホットエレクトロンの注入の減少が図れることであ
る。The characteristics of these structures are that the source circle has a high concentration n+ impurity layer 2
Also, a low concentration n- impurity layer 4F3 and a low concentration n- impurity layer 5 are added to a part or the entire surrounding of the high I+ impurity layer 3 for the drain, and the advantage is that the low concentration n- The impurity layer 5 expands the depletion layer of the drain circle high concentration n+ impurity layer 3 and weakens the electric field strength within this depletion layer, thereby improving the source/drain breakdown voltage and reducing the injection of hot electrons. .
【発明が解決しようとする問題点］
しかしながら、従来のＭＯＳＦＥＴにおいては、ソース
円高濃度ｎ＋不純物層２のまわりの一部にあるいはまわ
り全体に形成された低濃度ｎ−不純物層４での抵抗成分
の増加がＭＯＳＦＥＴのコンダクタンスを大きく低下さ
せるという基本的な欠点があり、このコンダクタンスの
低下はこのＭＯＳＦＥＴをＬＳＩなどで使用する場合に
大きな障害になっている。Problems to be Solved by the Invention] However, in the conventional MOSFET, the resistance component in the low concentration n- impurity layer 4 formed partially or entirely around the source circle high concentration n+ impurity layer 2 The fundamental drawback is that an increase in the MOSFET greatly reduces the conductance of the MOSFET, and this reduction in conductance is a major obstacle when using this MOSFET in LSIs and the like.
また、ＬＬＤ構造のＭＯＳＦＥＴではその製造プロセス
が相当複雑になり、Ｇ ｒａｄｅｄ Ｊ ｕｎｃｔｉ
。In addition, the manufacturing process for LLD structure MOSFETs is considerably complicated, and graded junction
.
ｎ構造のＭＯＳＦＥＴでは低濃度ｎ−不純物層４゜５が
ｐ形シリコン基板１内に深く形成されるためバンチスル
ーが発生しやすいという欠点があった。In the n-structure MOSFET, the low concentration n-impurity layer 4.5 is formed deep within the p-type silicon substrate 1, so there is a drawback that bunch-through is likely to occur.
以上のように、従来のＭＯＳＦＥＴには種々の欠点があ
り、コンダクタンスの低下を生じずに、ＭＯＳ型半導体
装置の微細化、高耐圧化および信頼性の高度化を達成す
ることは基本的に困難であった。As mentioned above, conventional MOSFETs have various drawbacks, and it is fundamentally difficult to achieve miniaturization, high breakdown voltage, and high reliability of MOS semiconductor devices without causing a decrease in conductance. Met.
この発明は上記のような欠点を除去するためになされた
もので、微細化、高耐圧化、高速化および信頼性の高度
化を図れるＭＯＳ型半導体装１を提供することを目的と
する。The present invention was made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a MOS type semiconductor device 1 that can be miniaturized, have a high breakdown voltage, operate at high speed, and have high reliability.
［問題点を解決するための手段］
この発明に係るＭＯＳ型半導体装置は、第１１１電形の
半導体基板上に該半導体基板の不純物濃度より不純物濃
度が高い第１導電形の半導体層を形成し、該第１ｓ電形
の半導体層上に不純物濃度が高い第２導電形の第１半導
体層を形成し、上記半導体基板上に上記第１導電形の半
導体層と間隔を隔てて不純物濃度が低い第２導電形の半
導体層を形成し、該第２１！′Ｉｌ形の半導体層上に不
純物濃度が高い第２導電形の第２半導体層を形成し、少
なくとも上記第１導電形の半導体層上および上記半導体
基板上に不純物濃度が低い表面半導体層を形成し、該表
面半導体層の一方側が上記第２導電形の第１半導体層に
接触しその他方側が少なくとも第２導電形の半導体層に
接触するようにし、上記第２導電形の第１半導体層上、
上記表面半導体層上、上記第２導電形の半導体層上およ
び上記第２導電形の第２半導体層上にゲート絶縁膜を形
成し、該ゲート絶縁膜上にゲート電極を形成するように
したものである。[Means for Solving the Problems] A MOS semiconductor device according to the present invention includes forming a semiconductor layer of a first conductivity type on a semiconductor substrate of a 111th conductivity type, the impurity concentration of which is higher than that of the semiconductor substrate. , a first semiconductor layer of a second conductivity type with a high impurity concentration is formed on the semiconductor layer of the first S conductivity type, and a first semiconductor layer of a second conductivity type with a low impurity concentration is formed on the semiconductor substrate at a distance from the semiconductor layer of the first conductivity type. A semiconductor layer of a second conductivity type is formed, and the 21st! 'A second semiconductor layer of a second conductivity type with a high impurity concentration is formed on the Il type semiconductor layer, and a surface semiconductor layer with a low impurity concentration is formed at least on the semiconductor layer of the first conductivity type and on the semiconductor substrate. one side of the surface semiconductor layer is in contact with the first semiconductor layer of the second conductivity type, and the other side is in contact with at least the semiconductor layer of the second conductivity type; ,
A gate insulating film is formed on the surface semiconductor layer, the second conductivity type semiconductor layer, and the second conductivity type second semiconductor layer, and a gate electrode is formed on the gate insulating film. It is.
［作用１
この発明においては、不１ｉｌｌ物濃度が高い第２導電
形の第２半導体層のまわりの不純物濃度が低い第２導電
形の半導体層は、上記第２導電形の第２半導体層の空乏
層を広げてこの空乏層内の電界強度を弱くし衝突電離に
よるキャリアの発生を減少させ、不純物濃度が高い第２
導電形の第１半導体層のまわりの不純物１１度が高い第
１′ｓ電形の半導体層では、上記の発生したキャリアの
一方が集積してもこの部分の電位の変化を最小に抑制す
る。[Operation 1] In the present invention, the semiconductor layer of the second conductivity type with a low impurity concentration surrounding the second semiconductor layer of the second conductivity type with a high impurity concentration is By widening the depletion layer and weakening the electric field strength within this depletion layer, the generation of carriers due to impact ionization is reduced.
In the semiconductor layer of the 1's conductivity type in which the impurity level around the first semiconductor layer of the conductivity type is high, even if one of the generated carriers is accumulated, the change in the potential of this portion is suppressed to the minimum.
また、上記第１導電形の半導体層はＭＯＳ型半導体装置
のコンダクタンスを向上させる。Further, the semiconductor layer of the first conductivity type improves the conductance of the MOS type semiconductor device.
［実施例］
以下、この発明の実ｍ例を図について説明するが、その
前にこの発明の概要について若干説明する。[Example] Hereinafter, actual examples of the present invention will be explained with reference to the drawings, but before that, an outline of the present invention will be briefly explained.
ＭＯＳＦＥＴの耐圧は、ドレイン接合における高電界下
での衝突電離による「なだれ降伏」によって、あるいは
Ｗ突電離で発生した電子−正孔対。The breakdown voltage of a MOSFET is determined by "avalanche breakdown" due to impact ionization under a high electric field at the drain junction, or by electron-hole pairs generated by W impact ionization.
のうち、たとえばｎチャンネルＭＯＳＦＥＴであれば正
孔がドレイン電界によってソース近くまで流れてそこに
高密度で集積し、このためソース近くの基板内部の電位
が上昇してソースから電子が多量に基板に注入されＭＯ
ＳＦＥＴがバイポーラトランジスタのように動作するこ
とによって低下する。特に後者のバイポーラ動作は、短
チャンネルＭＯＳＦＥＴ１．：おいて耐圧低下の主な原
因となっている。この発明はこのＭＯＳＦＥＴのバイポ
ーラ動作をも抑制することができる。すなわち、ドレイ
ン付近の不純物の濃度分布を緩やかに変化させることに
よって電界集中を防ぎ衝突電離による電子−正孔対の発
生をまず抑制する。そして、多量の正孔がソース近くに
集積しても、ソース近くにはｐ＋層があるため基板内部
の電位の上昇が抑制されソースから基板への電子の注入
が発生しない。このように、この発明の構造のＭＯＳＦ
ＥＴは短チャンネルＭＯＳＦＥＴでは不可能であった高
いソース・ドレイン耐圧を実現できることが理論的に明
らかである。For example, in the case of an n-channel MOSFET, holes flow close to the source due to the drain electric field and accumulate there at high density, which increases the potential inside the substrate near the source and causes a large amount of electrons to flow from the source to the substrate. Injected MO
This is due to the fact that the SFET behaves like a bipolar transistor. In particular, the latter bipolar operation is suitable for short channel MOSFET1. : This is the main cause of a decrease in breakdown voltage. The present invention can also suppress bipolar operation of this MOSFET. That is, by gently changing the impurity concentration distribution near the drain, electric field concentration is prevented and the generation of electron-hole pairs due to collision ionization is first suppressed. Even if a large amount of holes accumulate near the source, since there is a p+ layer near the source, the rise in potential inside the substrate is suppressed and injection of electrons from the source to the substrate does not occur. In this way, the MOSFET of the structure of this invention
It is theoretically clear that ETs can achieve high source-drain breakdown voltages that are not possible with short channel MOSFETs.
第１図はこの発明の実施例であるｎチャンネルＭＯＳＦ
ＥＴを示す断面図である。図において、不純物濃度が１
Ｑ Ｉ Ｇ ／ ｃａｌ程度のｐ形シリコン基板１上の
一部に不純物濃度が１０′５〜１０１’７ａｍ”の高濃
度ｐ＋不純物層９が形成されており、この不純物層上に
ソース同高濃度ｎ＋不純物履２が形成されている。また
ｐ形シリコン基板１上の他の一部に高濃度ｐ＋不純物１
１９と間隔を隔テテ不純物濃度が１０＋４〜１０Ｉ６／
Ｃｌ１１′の低濃度ｎ−不純物層８が形成されており、
この不純物層上にドレイン用高ｍａｎ＋不純物層３が形
成されている。高濃度ｐ＋不純物Ｍ９上およびｐ形シリ
コン基板１上に不純物濃度が〜１０”／Ｃ１３のｐ形ま
たはｎ形の低濃度不純物層１０が形成されており、この
不純物層の一方側がソース円高濃度ｎ＋不純物層２に接
触しその他方側が低濃度ｎ−不純物層８に接触している
。ソース円高濃度ｎ＋不純物層２上、低濃度不純物層１
０上、低部ｉ［ｎ−不純物層８上およびドレイン用高濃
度ｎ＋不純物１１３上にゲート絶縁膜６が形成されてお
り、このゲート絶縁膜上にゲート電極７が形成されてい
る。ｐ形シリコン基板１はイオン注入で形成してもよく
、あるいはエピタキシャル成長によって形成してもよい
。またｐ形シリコン基板１内への不純物の導入、すなわ
ちソース円高濃度ｎ＋不純物層２．高漢度ｐ＋不純物層
９．低濃度不純物層１０、低濃度ｎ−不純物層８および
ドレイン円高濃度ｎ＋不純物層３は、イオン注入や拡散
によって形成してもよく、あるいはＭ Ｂ Ｅ （Ｍ
ｏｌｅｃｕｌａｒｌ Ｏｎ Ｂｅａｍ ｌ：、ｐｉ
ｔａｘｉｙ ：分子イオンビームエピタキシ）やＦ Ｉ
Ｂ （Ｆｏｃｕｓｅｄ Ｉ ｏｎ Ｂｅａｍ ：
集束イオンビーム）によって形成してもよい。低濃度ｎ
＋不純物層８はドレイン円高濃度ｎ＋不純物層３の空乏
層を広げてこの空乏層内の電界強度を弱め、ソース・ド
レイン耐圧の低下の原因とな ゛るキャリアの発生
を減少させる。高濃度ｐ１不純物層９はこの発生したキ
ャリアのうち正孔がソース層高ｗｒｅｎ＋不純物眉２前
面に集積しても、高濃度ｐ＋不純物層９のためにソース
円高濃度ｎ＋不純物層２とｐ形シリコン基板１１ＩＩｌ
のビルトイン電圧の低下を防ぎ、ソース円高濃度ｎ＋不
純物層２からｐ形シリコン基板１への電子の流入を防ぐ
。Figure 1 shows an n-channel MOSFET which is an embodiment of the present invention.
It is a sectional view showing ET. In the figure, the impurity concentration is 1
A high-concentration p+ impurity layer 9 with an impurity concentration of 10'5 to 101'7 am'' is formed on a part of the p-type silicon substrate 1 of approximately Q I G / cal, and on this impurity layer there is a source with the same high concentration. An n+ impurity layer 2 is formed.Also, a high concentration p+ impurity 1 is formed on another part of the p-type silicon substrate 1.
19 and the impurity concentration is 10+4~10I6/
A low concentration n-impurity layer 8 of Cl11' is formed,
A high man+ impurity layer 3 for drain is formed on this impurity layer. A p-type or n-type low concentration impurity layer 10 with an impurity concentration of ~10''/C13 is formed on the high concentration p+ impurity M9 and on the p type silicon substrate 1, and one side of this impurity layer is a source circle with high concentration. The other side is in contact with the n+ impurity layer 2, and the other side is in contact with the low concentration n- impurity layer 8.The source circle is on the high concentration n+ impurity layer 2, and the low concentration impurity layer 1
A gate insulating film 6 is formed on the low part i[n- impurity layer 8 and on the high concentration n+ impurity 113 for drain, and a gate electrode 7 is formed on this gate insulating film. P-type silicon substrate 1 may be formed by ion implantation or epitaxial growth. Also, the introduction of impurities into the p-type silicon substrate 1, that is, the source circle high concentration n+ impurity layer 2. High degree p+ impurity layer 9. The low concentration impurity layer 10, the low concentration n- impurity layer 8, and the drain circle high concentration n+ impurity layer 3 may be formed by ion implantation or diffusion, or by M B E (M
olecular On Beam l:, pi
taxi: molecular ion beam epitaxy) and FI
B (Focused on Beam:
It may also be formed by a focused ion beam). low concentration n
The + impurity layer 8 widens the depletion layer of the heavily doped n+ impurity layer 3 in the drain circle, weakens the electric field strength within this depletion layer, and reduces the generation of carriers that cause a decrease in source-drain breakdown voltage. Even if holes among the generated carriers are accumulated on the front surface of the source layer high wren + impurity eyebrow 2, the high concentration p1 impurity layer 9 makes the source circle high concentration n+ impurity layer 2 and p type. Silicon substrate 11IIl
This prevents the built-in voltage from decreasing and prevents electrons from flowing into the p-type silicon substrate 1 from the source circle high concentration n+ impurity layer 2.
このため、ＭＯＳＦＥＴの高耐圧化ひいては微細化が実
現され、また信頼度の高度化が実現される。Therefore, higher breakdown voltage and further miniaturization of the MOSFET can be realized, and higher reliability can be realized.
低濃度不純物層１０はｐ形シリコン基板１表面のしきい
値電圧を制御するためのもので、高濃度ｐ“不純物１１
９によるしきい値電圧の上昇を抑制する。また、ソース
用高濃度ｎ＋不純物１Ｉ１２のまねりに高濃度ｐ＋不純
物！１９を形成することによってＭＯＳＦＥＴのコンダ
クタンスが向上し、その高速化が実現されも。The low concentration impurity layer 10 is for controlling the threshold voltage of the surface of the p-type silicon substrate 1, and the high concentration p" impurity layer 11
This suppresses the increase in threshold voltage caused by 9. In addition, a high concentration p+ impurity is added to imitate the high concentration n+ impurity 1I12 for the source! By forming 19, the conductance of the MOSFET can be improved and its speed can be increased.
第２図は、この発明の他の実施例である５ＯＩ（３１１
１ｃｏｎ Ｑｎ Ｉｎ５ｕｌａｔｏｒ）ｎチャンネ
ル間Ｏ８ＦＥＴを示す断面図である。図において、絶縁
物１１上に第１図のｎチャンネル間Ｏ８ＦＥＴと同様な
構造が形成されており、これによってもＭＯＳＦＥＴの
微細化、高耐圧化、高速化および信頼度の高度化が実現
される。FIG. 2 shows 5OI (311
1con Qn In5ulator) is a cross-sectional view showing an n-channel O8FET. In the figure, a structure similar to the n-channel O8FET in Figure 1 is formed on an insulator 11, and this also realizes miniaturization, higher voltage resistance, higher speed, and higher reliability of the MOSFET. .
上述のような構造の作用は、ソース側またはドレイン側
の構造のみを単独で採用してもバンチスルー発生による
耐圧低下や接合耐圧の低下を招き、この発明のような効
果は期待できない。すなわち、この発明の特徴はＭＯＳ
ＦＥＴの耐圧低下をその原因となる正孔の発生と正孔の
持つ正電荷の影響を抑制することによって実現し、キャ
リアの発生を防ぐことによってホットエレクトロンの発
生も同時に減少させて信頼度の高度化を図り、さらにソ
ースのまわりにｐ＋層を形成することによって低抵抗化
を図りコンダクタンスの向上を実現する、高性能微細化
ＭＯＳＦＥＴである。As for the effects of the structure described above, even if only the structure on the source side or the drain side is adopted alone, the withstand voltage and the junction breakdown voltage will be lowered due to bunch-through generation, and the effects of the present invention cannot be expected. In other words, the feature of this invention is that MOS
This reduces the breakdown voltage of FETs by suppressing the generation of holes that cause this and the effect of the positive charge that holes have.By preventing the generation of carriers, the generation of hot electrons is also reduced, resulting in a high level of reliability. This is a high-performance miniaturized MOSFET that achieves lower resistance and improved conductance by forming a p+ layer around the source.
なお、ソース用高漢度ｎ＋不粍物層２とドレイン用高濃
度ｎ＋不純物＠３の深さは異なってもよく、たとえばソ
ース用高濃度ｎ＋不純物層２Ｉ３よび高濃度ｐ＋不純物
層９の深さをドレイン用高晴度ｎ＋不純物層３および低
濃度ｎ−不不純物日の深さより浅くすることによって、
コンダクタンスの低下を防ぎながらパンチスルーによる
耐圧低下を一層効果的に防止することができる。Note that the depths of the high concentration n+ impurity layer 2 for the source and the high concentration n+ impurity @3 for the drain may be different, for example, the depths of the high concentration n+ impurity layer 2I3 and the high concentration p+ impurity layer 9 for the source. By making the depth shallower than the depth of the high concentration n+ impurity layer 3 for the drain and the low concentration n- impurity layer 3,
It is possible to more effectively prevent a decrease in breakdown voltage due to punch-through while preventing a decrease in conductance.
また、上記実施例では、ソース円高濃度ｎ＋不純物層２
およびドレイン層高１１度０４″不純物層３のまわり全
体に高温度ｐ＋不純物層９および低濃度ｎ−不純物Ｎ８
を形成する場合について説明したが、ソース用高濃度ｎ
＋不純物１１２６よびドレイン用高引Ｉ＋不純物１１３
のまわりの一部に高１１度り＋不純物ｗ９および低濃度
ｎ−不純物履８を形成する場合についても、上記実施例
と同様の効果を奏する。Further, in the above embodiment, the source circle high concentration n+ impurity layer 2
and a high temperature p+ impurity layer 9 and a low concentration n- impurity N8 all around the drain layer height 11 degrees 04'' impurity layer 3.
We have explained the case of forming a high concentration n for source.
+Impurity 1126 and drain I + impurity 113
The same effect as in the above embodiment can be obtained also when forming the high 11 degree + impurity w9 and the low concentration n- impurity footwear 8 in a part around the .
また、上記実施例では、ｎチャンネルＭＯＳＦＥＴの場
合について説明したが、各部をｐ形からｎ形にｎ形から
ｐ形にしたｐチャンネルＭＯＳＦＥＴについてもこの発
明は適用できる。Further, in the above embodiments, the case of an n-channel MOSFET has been described, but the present invention can also be applied to a p-channel MOSFET in which each part is changed from a p-type to an n-type or from an n-type to a p-type.
［発明の効果１
以上のようにこの発明によれば、第１導電形の半導体基
板上に該半導体基板の不純物濃度より不純物濃度が高い
第１導電形の半導体層を形成し、該第１導電形の半導体
層上に不純物濃度が高い第２導電形の第１半導体層を形
成し、上記半導体基板上に不純物濃度が低い第２導電形
の半導体層を形成し、該第２導電形半導体層上に不純物
濃度が高い第２導電形の第２半導体層を形成したので、
上記第２導電形の半導体層は、上記第２導電形の第２半
導体層の空乏層を広げてこの空乏層内の電界強度を弱ク
シ衝突電離によるキャリアの発生を減少させ、上記第１
導電形の半導体層では、上記の発生したキャリアの一方
が集積してもこの部分の電位の変化を最小に抑制する。[Effect of the Invention 1 As described above, according to the present invention, a semiconductor layer of a first conductivity type having an impurity concentration higher than that of the semiconductor substrate is formed on a semiconductor substrate of a first conductivity type, and a first semiconductor layer of a second conductivity type with a high impurity concentration is formed on the semiconductor layer of the shape, a second conductivity type semiconductor layer with a low impurity concentration is formed on the semiconductor substrate, the second conductivity type semiconductor layer with a low impurity concentration; Since a second semiconductor layer of the second conductivity type with a high impurity concentration was formed on top,
The semiconductor layer of the second conductivity type widens the depletion layer of the second semiconductor layer of the second conductivity type to reduce the generation of carriers due to weak comb impact ionization by reducing the electric field strength within the depletion layer.
In a conductive type semiconductor layer, even if one of the generated carriers is accumulated, changes in the potential of this portion are suppressed to a minimum.
また、上記第１導電形の半導体層はＭＯＳＦＥＴのコン
ダクタンスを向上させる。°このため、微細化、高耐圧
化。Further, the semiconductor layer of the first conductivity type improves the conductance of the MOSFET. °For this reason, miniaturization and high voltage resistance.
高速化、および信頼度の高度化が図れるＭＯＳ ＦＥＴ
を従来のＭＯＳ Ｆ Ｅ Ｔより簡単な製造方法により
しかも精度良く作ることができる。MOS FET with higher speed and higher reliability
can be manufactured using a simpler manufacturing method than conventional MOS FETs and with higher precision.
第１図は、この発明の実施例であるｎチャンネル間Ｏ８
ＦＥＴを示す断面図である。
第２図は、この発明の他の実施例である５ＯＩｎチャン
ネルＭＯＳＦＥＴを示す断面図である。
第３図は、従来のＬＤＤ構造のＭＯＳＦＥＴを示す断面
図である。
第４図は、従来のＱ ｒａｄｅｄ Ｊ ｕｎｃｔｉｏｎ
構造のＭＯＳＦＥＴを示す断面図である。
図において、１はｐ形シリコン基板、２はソース円高濃
度ｎ＋不純物層、３はドレイン同高濃度ｎ＋不純物層、
４．５は低部［ｎ−不純物層、６はゲート絶縁膜、７は
ゲート電極、８は低濃度ｎ−不純物層、９は高濃度ｐ＋
不純物層、１０は低濃度不純物層である。
なお、各図中同一符号は同一または相当部分を示す。
代 理 人 大 岩 増 雄第１図
第２図
１に−ａ＠
第３図
第４図FIG. 1 shows an O8 between n channels, which is an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing an FET. FIG. 2 is a sectional view showing a 5OIn channel MOSFET which is another embodiment of the present invention. FIG. 3 is a cross-sectional view showing a conventional LDD structure MOSFET. Figure 4 shows a conventional Q rated junction.
FIG. 2 is a cross-sectional view showing a MOSFET structure. In the figure, 1 is a p-type silicon substrate, 2 is a source circle high concentration n+ impurity layer, 3 is a drain same high concentration n+ impurity layer,
4.5 is the lower part [n- impurity layer, 6 is the gate insulating film, 7 is the gate electrode, 8 is the low concentration n- impurity layer, 9 is the high concentration p+
The impurity layer 10 is a low concentration impurity layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 1-a@ Figure 3 Figure 4
Claims (1)
度より不純物濃度が高い第１導電形の半導体層と、 前記不純物濃度が高い第１導電形の半導体層上に形成さ
れる不純物濃度が高い第２導電形の第１半導体層と、 前記半導体基板上に前記不純物濃度が高い第１導電形の
半導体層と間隔を隔てて形成される不純物濃度が低い第
２導電形の半導体層と、 前記不純物濃度が低い第２導電形の半導体層上に形成さ
れる不純物濃度が高い第２導電形の第２半導体層と、 少なくとも前記不純物濃度が高い第１導電形の半導体層
上および前記半導体基板上に形成され、かつ一方側が前
記不純物濃度が高い第２導電形の第１半導体層に接触し
他方側が少なくとも前記不純物濃度が低い第２導電形の
半導体層に接触している不純物濃度が低い表面半導体層
と、 前記不純物濃度が高い第２導電形の第１半導体層上、前
記不純物濃度が低い表面半導体層上、前記不純物濃度が
低い第２導電形の半導体層上および前記不純物濃度が高
い第２導電形の第２半導体層上に形成されるゲート絶縁
膜と、 前記ゲート絶縁膜上に形成されるゲート電極とを備えた
ＭＯＳ型半導体装置。[Scope of Claims] A semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on the semiconductor substrate and having an impurity concentration higher than that of the semiconductor substrate; and a first conductivity type semiconductor layer having an impurity concentration higher than that of the semiconductor substrate. a first semiconductor layer of a second conductivity type with a high impurity concentration formed on a semiconductor layer of a conductivity type; and a semiconductor layer of a first conductivity type with a high impurity concentration formed on the semiconductor substrate at a distance. a second conductivity type semiconductor layer with a low impurity concentration; a second conductivity type second semiconductor layer with a high impurity concentration formed on the second conductivity type semiconductor layer with a low impurity concentration; a second conductivity type formed on a semiconductor layer of a high first conductivity type and on the semiconductor substrate, one side in contact with the first semiconductor layer of a second conductivity type in which the impurity concentration is high, and the other side at least in the low impurity concentration; a surface semiconductor layer with a low impurity concentration that is in contact with the semiconductor layer; on the first semiconductor layer of the second conductivity type with the high impurity concentration; A MOS semiconductor device comprising: a gate insulating film formed on a semiconductor layer of a conductivity type and a second semiconductor layer of a second conductivity type having a high impurity concentration; and a gate electrode formed on the gate insulating film. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5736085A JPS61214477A (en) | 1985-03-19 | 1985-03-19 | Mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5736085A JPS61214477A (en) | 1985-03-19 | 1985-03-19 | Mos type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61214477A true JPS61214477A (en) | 1986-09-24 |
Family
ID=13053409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5736085A Pending JPS61214477A (en) | 1985-03-19 | 1985-03-19 | Mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61214477A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63141372A (en) * | 1986-12-04 | 1988-06-13 | Seiko Instr & Electronics Ltd | Insulated gate field effect transistor |
| EP0583897A2 (en) * | 1992-08-03 | 1994-02-23 | Hughes Aircraft Company | Field-effect transistor with structure for suppressing hot-electron effects, and method of fabricating the transistor |
| WO2004070847A1 (en) * | 2003-02-07 | 2004-08-19 | Matsushita Electric Industrial Co., Ltd. | Field-effect transistor, its manufacturing method, and complementary field-effect transistor |
-
1985
- 1985-03-19 JP JP5736085A patent/JPS61214477A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63141372A (en) * | 1986-12-04 | 1988-06-13 | Seiko Instr & Electronics Ltd | Insulated gate field effect transistor |
| EP0583897A2 (en) * | 1992-08-03 | 1994-02-23 | Hughes Aircraft Company | Field-effect transistor with structure for suppressing hot-electron effects, and method of fabricating the transistor |
| EP0583897A3 (en) * | 1992-08-03 | 1994-08-17 | Hughes Aircraft Co | Field-effect transistor with structure for suppressing hot-electron effects, and method of fabricating the transistor |
| US5527721A (en) * | 1992-08-03 | 1996-06-18 | Hughes Aircraft Company | Method of making FET with two reverse biased junctions in drain region |
| WO2004070847A1 (en) * | 2003-02-07 | 2004-08-19 | Matsushita Electric Industrial Co., Ltd. | Field-effect transistor, its manufacturing method, and complementary field-effect transistor |
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