JP2933796B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an insulated gate field effect transistor and, more particularly, to a measure for improving an operation speed.

[0002]

2. Description of the Related Art Conventionally, especially in an N-channel MOS transistor, in order to provide high reliability, after a sidewall is provided on a gate electrode, a high-concentration source region and a drain region are implanted to thereby improve the channel of the drain region. LDD (Lightly Doped)
Drain) structures have been used. In this structure, since the low-concentration drain plays a role of relaxing the electric field near the drain, high reliability in drain withstand voltage and the like can be obtained. However, in these MOS transistors having the LDD structure, generally, most of the low-concentration drain is located outside the gate electrode. Therefore, the low-concentration drain located outside the gate is pinched off to form a high-resistance layer, and the driving current is reduced. It is easy to cause deterioration. In addition, hot carriers are generated immediately below the sidewalls, and the hot carriers are injected and captured by the sidewalls, so that the low-concentration drain is pinched off and the resistance is significantly increased. As a result, there is a problem that the drive current is rapidly deteriorated by hot carriers as compared with the single source and drain structure.

Therefore, as a modification of the above LDD structure, IE
As disclosed in DM TECHNICAL DIGEST, 1989, p777,
A so-called LATID (Large-Angle-
There is also a MOS transistor using a Tilt Implanted Drain) structure. That is, when forming the low-concentration source and drain, ion implantation is performed at an angle of about 45 ° instead of performing ion implantation at an angle close to parallel to the normal of the substrate surface (usually inclined at 7 ° to prevent channeling) as in the related art. By using the two-step implantation, the low-concentration source 4 and the low-concentration drain 5 are positively transferred from immediately below the sidewalls (spacers) 6 to below the gate electrode 3. Therefore, in the MOS transistor having the LATID structure, it is possible to prevent the resistance from being increased by pinch-off of the low-concentration drain. This has significantly higher driving power and reliability than the MOS transistor having the LDD structure.

FIGS. 14 (a) and 14 (b) show the above L
For a MOS transistor having an ATID structure or an LDD structure, a lateral electric field E // (MV / cm 2) and an electron concentration Ne (c
m ^-3 ), hot carrier pair generation degree Rg (cm ^-3 · s ^-1 )
2 shows a result of two-dimensional simulation of the vicinity of the drain.
The shaded region is a region where the hot carrier pair generation degree Rg is 1028 or more. The substrate impurity concentration is about 1 × 10 ¹⁷ cm ⁻³ .
Bias conditions are drain voltage Vd = 5V, gate voltage Vg = 2V
, The substrate voltage Vsub = 0 V, and drain avalanche hot carriers that degrade the NchMOS transistor the most are generated. When Vg <Vd, the drain region near the gate electrode is depleted. The current flows so as to bypass this depletion region. In the MOS transistor having the LATID structure, the current bypasses the depletion region, the current flows more deeply, the point where hot carriers are generated becomes deep, and the generated hot carriers are easily scattered and hardly injected into the gate oxide film. On the other hand, in the LDD structure, the depletion region is small, and is formed away from the point where the electric field is concentrated. Therefore, the current is hardly affected by the depletion region, flows near the surface, and hot carriers are also generated near the surface. This is LATID
This is one of the reasons why a MOS transistor having a structure has high reliability.

However, the LATID structure MO
In the S-type transistor, the low-concentration source and drain are formed to be shallower than the substrate surface as much as they are below the gate electrode, so that there is a problem that the above effects cannot be fully utilized. Also, the gate-drain overlap amount Lo
v increases, the gate-drain capacitance Cg
d has become large, and there has been a problem that the increased driving force cannot be fully utilized in the circuit operation speed.

On the other hand, as disclosed in US Pat. No. 4,746,624, a buried drain as a third region, which is based on an LDD structure and is thicker than a low-concentration drain and thinner than a high-concentration drain, has a predetermined depth from the substrate surface. The so-called BLDD (Buried LDD) is intended to reduce the probability that hot carriers are injected and trapped in the sidewalls, thereby preventing the drive current from deteriorating. US Pat. No. 4,746,6, which was made to improve the structure (see FIG. 13) and the short channel effect generated in the BLDD structure.
The method of the invention of 24, that is n a high resistance, which is the fourth region ^- there is a method of blocking regions of the (or a p or intrinsic) is provided at the boundary of the lightly doped drain and the heavily doped drain (Fig. 14 reference).

[0007]

However, the above B
In the structure of the LDD, when the channel length is shortened with the increase in the density of the semiconductor device, punch-through is likely to occur along the path indicated by the broken line arrow in FIG. 14, that is, the short channel effect increases. (See the same publication). In particular, in this structure, even if the buried drain is provided so as to overlap below the gate electrode in order to avoid an increase in resistance due to pinch-off, the gate-drain capacitance of the low-concentration source and drain becomes large, and the above L
As in the case of the ATID structure, there is also a problem that the operation speed cannot be improved.

Further, the invention of US Patent 4,746,624 is as follows:
In order to prevent the short channel effect, which is a drawback of the BLDD, in this method, a low-concentration source and a drain are formed after forming a gate electrode, a first side wall is formed, and then counter doping is performed. A complicated process of forming the blocking region B, forming the sidewall again, and forming the high-concentration source and drain must be performed, and the boundary between the low-concentration drain and the high-concentration drain is below the sidewall, No blocking region is formed below the gate electrode. For this reason, the current is deeply sunk under the sidewall where the influence of the gate voltage is not easily affected, so that the current driving force may be further reduced, and the operating speed is limited.

The present invention mainly relates to the LDD structure, L
In both the ATID structure and the BLDD structure, the gate-drain capacitance is formed because the effective impurity concentration is increased from the inside of the substrate toward the surface of the substrate at the surface portions of the low concentration source and drain regions. It has been made by focusing on the point that the operation speed of the semiconductor device cannot be reduced, and there is a limit in improving the operation speed of the semiconductor device. The purpose is based on the transistor having the LATID structure, By providing a concentration distribution in the source and drain regions such that the effective impurity concentration gradually decreases from the inside of the substrate toward the surface, the reliability can be improved and the transistor can be formed without causing the short channel effect. The purpose of the present invention is to increase the speed of the operation.

[0010]

Means for Solving the Problems In order to achieve the above object, a means according to the first aspect of the present invention is to form a semiconductor device functioning as an insulated gate field effect transistor on a semiconductor substrate of one conductivity type. The method for manufacturing a semiconductor device described above is assumed.

A step of forming the gate electrode on a gate insulating film formed on a portion of the surface of the semiconductor substrate which is to be the insulated gate field effect transistor region; and, using the gate electrode as a mask, Forming a low-concentration source region by performing ion implantation of a conductivity type opposite to that of the semiconductor substrate; and ion-implantation of a conductivity type opposite to that of the semiconductor substrate on the surface of the semiconductor substrate using the gate electrode as a mask. Implanting to form a low-concentration drain region, and at least one of the low-concentration source region and the low-concentration drain region,
Using the gate electrode as a mask, the semiconductor substrate is inclined at a large angle from the normal direction of the semiconductor substrate so that impurities are implanted from the surface of the semiconductor substrate to the surface of the substrate located below the gate electrode. Implanting impurities of the same conductivity type to form a counter-doped region on the surface near the end of the gate electrode in the region; and forming the counter-doped region on the low-concentration source region and the low-concentration drain region using the gate electrode as a mask. Forming the high-concentration source region and the high-concentration drain region by ion implantation at a higher concentration than ion implantation.

In this case, in the above-mentioned counter doping region, the manufacturing method is such that the effective impurity concentration at the surface of the substrate is lower than the effective impurity concentration inside the substrate.

[0013] means taken in the invention of claim 2, connected in the above-described method for manufacturing according to claim 1, the gate electrode as a mask, the channel from at least one region of the lightly doped source region and the lightly doped drain region The semiconductor substrate is further inclined at a large angle from the normal direction of the semiconductor substrate so that the impurity is implanted into the substrate surface portion of the portion to be implanted, and the impurity of the same conductivity type as the impurity of the semiconductor substrate and higher in concentration than the semiconductor substrate is implanted. The manufacturing method includes a step of forming a high threshold region having the same conductivity type as that of the semiconductor substrate in the region.

According to a third aspect of the present invention, in the manufacturing method of the first or second aspect , the impurity implantation angle in the step of forming the low-concentration source region or the low-concentration drain region is 10 ° to 45 °. This is a manufacturing method.

According to a fourth aspect of the present invention, in the manufacturing method of the third aspect , the impurity implantation angle in the impurity implantation step of the same conductivity type as that of the semiconductor substrate is set at 25 ° from the normal direction of the semiconductor substrate. This is a manufacturing method with an inclined angle .

[0016]

With the above arrangement, according to the first aspect of the present invention, the LA
Since a counter-doped region having a low effective impurity concentration is formed on a surface portion of a low-concentration source region or a low-concentration drain region of a transistor having a structure close to the TID structure, a low-concentration source region or a low-concentration drain region is formed. Injection conditions are relatively simple and manufacturing is easy.

According to the second aspect of the present invention, only by changing the concentration and implantation angle of the counter-doped impurity, the surface region is increased from the low-concentration source region or low-concentration drain region having a low effective impurity concentration to the region connected to the channel. Since the threshold region is formed, the semiconductor device can be miniaturized without causing a short channel effect.

According to the third aspect of the present invention, the impurity implantation angle into the low-concentration source region or the low-concentration drain region becomes appropriate, and the impurity concentration distribution in the region becomes particularly good.

According to the fourth aspect of the present invention, the implantation angle of the impurity for forming the high threshold region becomes appropriate, and the position of the high threshold region and the effective impurity concentration value become particularly good.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

[0021] (Example 1) or not a, a description will be given of the actual Example 1.

FIGS. 1A to 1D are cross-sectional views showing a semiconductor device and a manufacturing process of the semiconductor device in the first embodiment.

First, as shown in FIG. 1A, a gate oxide film 2 is formed to a thickness of 16 nm on the surface of a P-type Si semiconductor substrate 1 having, for example, an impurity concentration of 3 × 10 ¹⁶ cm ⁻³ , and then a polysilicon film is formed. The gate electrode 3 is formed by selectively performing anisotropic etching using a photoresist film or the like. (Gate length Lg = 0.8 μm) Next, as shown in FIG. 1B, phosphorus ions are implanted using the gate electrode 3 as a mask to form a low-concentration source 4 and a low-concentration drain 5. At this time, the ion implantation direction is the normal direction of the surface of the semiconductor substrate 1.
The injection direction is symmetrical when the lightly doped source 4 is formed and when the lightly doped drain 5 is formed. That is, implantation is performed first from the source side (broken arrow A) and then from the drain side (solid arrow B). At this time, since the phosphorus ions implanted obliquely have a predetermined energy, the impurity concentration in the low-concentration source 4 and the low-concentration drain region 5 below the vicinity of the end of the gate electrode 3 becomes lower at the substrate surface. very low concentrations the n ^-, and in yet site gets inside the substrate very low concentration n ^{- -,} the at sites containing a predetermined depth from the substrate surface highly concentrated n than is the surface portion is a low concentration becomes I have.

Next, as shown in FIG. 1C, after depositing a silicon oxide film by the CVD method, anisotropic etching is performed to form a sidewall 6 on the side of the gate electrode 3.

Further, as shown in FIG. 1D, high-concentration arsenic ions are implanted using the gate electrode 3 and the side wall 6 as a mask, so that the impurity concentration is lower than that of the low-concentration source 4 and the low-concentration drain 5. A high-concentration source 7 and a high-concentration drain 8 having a high concentration are formed, and finally heat treatment is performed at 900 ° C. for 90 minutes. At this time, although the impurities implanted in the above step diffuse, the effective impurity concentration in the low-concentration source 4 and low-concentration drain 5 near the end of the gate electrode 3 gradually decreases from the inside of the substrate toward the substrate surface. The density distribution is as follows. Then, a predetermined depth from the substrate surface (for example, 1 / １ ／ of the depth of the high concentration source 7 or the high concentration
The concentration distribution is such that a portion where impurities are relatively dense (for example, an effective impurity concentration of about 1.7 times the effective impurity concentration of the substrate surface portion) is present at a portion of about 2 to 1/4.

As described above, a MOS transistor according to an embodiment of the present invention is shown.
The type transistor is basically the same in manufacturing method as a conventional MOS transistor having a LATID structure. However, the ion implantation angle θ, the dose amount D,
By appropriately setting the energy Ei, a part or all of the low-concentration source 4 and the low-concentration drain 5 are formed under the gate electrode 3 after the process such as the heat treatment, and the impurity concentration is near the end of the gate electrode 3. An impurity profile having a peak value at a predetermined depth from the surface of the semiconductor substrate 1 can be obtained.

FIGS. 2A and 2B show the effective dose Neff.
[= D · COS θ] and gate-drain overlap
2 near the drain after the end of the process with equal Lov
Regarding the two-dimensional impurity profile, the MOS transistor (θ = 25 °, D = 2.3 × 10 ¹³ c) according to the embodiment of the present invention is used.
m ⁻² , Ei = 60 keV, Neff = 2.1 × 10 ¹³ cm ⁻² , Lov = 0.18 μm, and a MOS transistor having a conventional LATID structure (θ = 45
D, D = 3.0 × 10 ¹³ cm ^-2 , Ei = 50keV, Neff = 2.1 × 10 ¹³ c
m ^-2 , Lov = 0.18 μm), and FIG. 3C shows the profile of the impurity concentration in the depth direction at the gate electrode end of those transistors. As shown in the figure, in the MOS transistor according to the embodiment of the present invention, although the heat treatment is performed at 900 ° C. for 90 minutes after the ion implantation, the low-concentration source 4 near the end of the gate electrode 3 is lowered. It can be seen that the effective impurity concentration of the low-concentration drain 5 gradually decreases from the inside of the substrate toward the substrate surface, and that the impurity concentration has a peak at a depth of about 0.06 μm from the gate oxide film 2. That is,
The implantation angle θ is set to a large inclination angle but smaller than the impurity implantation angle for the conventional LATID structure,
By slightly increasing the implantation energy, even under the same heat treatment condition, unlike the LATID structure, the effective impurity concentration is distributed so as to gradually decrease from the inside of the substrate toward the substrate surface. However, depending on the heat treatment conditions, it is possible to form a concentration distribution such that the effective impurity concentration gradually decreases from the inside of the substrate toward the substrate surface even with a small implantation energy.

FIGS. 3A and 3B show a MOS transistor according to an embodiment of the present invention and a conventional LATI transistor, respectively.
For a MOS transistor having a D structure (both under the same conditions as shown in FIG. 2), a lateral electric field E // (MV / cm), an electron concentration Ne (cm ⁻³ ), and a hot carrier pair generation degree Rg ( cm
^-3 · s ^-1 ) is shown as a result of two-dimensional simulation near the drain. The figure below each figure shows the degree of hot carrier generation.
Hot carrier generation degree Rg at the point where Rg is maximum
FIG. 5 is a diagram showing a distribution in the horizontal direction. The impurity concentration of the substrate is about 1 × 10 ¹⁶ cm ⁻³ . The bias condition is the drain voltage Vd
= 7V, gate voltage Vg = 2V, and substrate voltage Vsub = -2V. Under this bias condition, drain avalanche hot carriers that cause the NchMOS transistor to deteriorate most are generated, and when Vg <Vd, the low-concentration drain 5 immediately below the gate electrode is depleted. The MOS type transistor according to the embodiment of the present invention (see FIG. 3A) has a lower substrate surface under the gate electrode near the gate electrode end than the conventional LATID structure MOS type transistor (see FIG. 3B). In the vicinity, the effective impurity concentration of the low-concentration drain 5 is kept low, so that this depletion layer further expands. Therefore, in addition to increasing the resistance due to the low impurity concentration of this region,
The resistance is further increased due to the depletion, and the current flowing position is further away from the substrate surface. Therefore, the position where hot carriers are generated is further away from the substrate surface, and the generated hot carriers (holes in this case) are hardly injected into the gate oxide film 2 and the like due to scattering, and the hot carrier resistance is improved. Specifically, the MOS transistor according to the embodiment of the present invention has the same hot carrier pair occurrence degree Rg as compared with the conventional LATID structure MOS transistor, but has the hot carrier pair occurrence degree Rg. The point at which the maximum is 0.053 μm for the distance from the substrate surface of 0.039 μm and 0.01
4 μm deeper. This difference is a sufficiently large value compared to the mean free path of holes in silicon (about 0.005 μm), and the probability that hot carriers are injected into the gate oxide film 2 or the like is increased by the mean free path of holes. Each time, the distance decreases by a factor of 1 / e (e is the base of natural logarithm), so by increasing the distance from the substrate surface by 0.014 μm,
The hot carrier injection probability is reduced to about 1/20.

FIG. 4 shows the hot carrier deterioration characteristics of the drain current (= Id) and the ratio of the substrate current to the source current (= Isub / Is) at various effective doses Neff. In this hot carrier deterioration characteristic of the drain current Id, stress conditions: Vd = 7V, Vg = 2V, Vsub = -2V, 3000sec, measurement conditions: Vd = 5V, Vg = 0.1V, Vsub = -2V, Isub / Is The measurement conditions are Vd = 7V, Vg = 2V, and Vsub = -2V. M of the embodiment of the present invention
It can be seen that the OS transistor has about 10% improvement in the hot carrier deterioration characteristic of the drain current Id, though the Isub / Is is larger than that of the conventional LATID MOS transistor. This improvement is 3
This is equivalent to about 4 times longer life.

FIGS. 5 and 6 show the short channel effect and the drain saturation current at various effective doses Neff. From these figures, the effective dose Ne
If ff is equal, the MOS transistor of the embodiment of the present invention has a short channel effect and a saturated current.
There is no difference from the conventional LATID MOS transistor. Therefore, there is no adverse effect on the current driving force due to the high resistance of the drain below the vicinity of the end of the gate electrode.

FIG. 7 shows the IV characteristics and the gate voltage Vg dependence of the gate-drain capacitance Cgd of the MOS transistor of the embodiment of the present invention and the MOS transistor of the conventional LATID structure. The lap amount Lov is made equal. For comparison, the LDD structure M
OS type transistors are also described. As shown in the figure, the MOS transistor of the embodiment of the present invention has the same driving force as the MOS transistor of the conventional LATID structure, but has a smaller gate-drain capacitance Cgd. This is probably because the effective impurity concentration in the surface region of the low-concentration drain 5 immediately below the gate electrode 3 of the MOS transistor according to the embodiment of the present invention is lower than that of the conventional LATID structure MOS transistor. As a result, as shown in FIG. 8, the operation speed when both are applied to the ring oscillator is M.
The OS transistor is a conventional MOS transistor having a LATID structure.
It can be seen that the operating speed of the ring oscillator is improved by about 10% as compared with the type transistor.

As described above, according to the first embodiment, the lightly doped source 4 and the lightly doped drain 5
Is formed, it is possible to maintain an excellent current drivability, which is a characteristic of the MOS transistor having the conventional LATID structure. Further, a distribution state of the effective impurity concentration is formed below the vicinity of the end of the gate electrode 3 so that the effective impurity concentration gradually decreases from the inside of the substrate toward the surface of the substrate. Expand
The gate-drain capacitance Cgd is reduced, and the operation speed is improved. Therefore, as compared with the conventional transistor having the LDD structure or the LATID structure, the hot carrier resistance and the operation speed can be improved without deteriorating the saturation current characteristics as shown in the above-described drawings.

On the other hand, the MOS transistor having the above BLDD structure is based on an LDD structure in which the effective impurity concentration increases from the inner side toward the surface, and a third region having an even higher impurity concentration is formed therein. However, with such a structure, a short channel effect such as punch-through may occur, and the effective impurity concentration at the surface of the substrate is high. Is relatively large, and there is a limit in improving the operation speed. On the other hand, the transistor of the present invention is based on a LATID structure in which the low-concentration source 4 and the low-concentration drain 5 in the LDD structure are provided in a region extending below the gate electrode 3, and the impurity concentration on the surface is reduced. In addition, since the gate-drain capacitance Cgd can be reduced and there is no buried drain having a relatively high effective impurity concentration, there is no problem that a short channel effect such as punch-through easily occurs.

In particular, a depth of 0.01 to 0.2 from the substrate surface
By forming a portion having a peak at which the effective impurity concentration becomes maximum at a portion of μm, injection of hot carriers into the insulating film can be reduced. That is, by making the mean free path of the hot carrier sufficiently deeper than 0.005 μm, the probability that the hot carrier reaches the gate oxide film 2 or the like on the substrate surface side can be reduced as much as possible, and the withstand voltage can be improved. Can be achieved.

In this case, in the manufacturing method as in the first embodiment, the number of times of implantation can be reduced only by changing the implantation conditions when forming the low-concentration source 4 and the low-concentration drain 5 as compared with the conventional LATID structure transistor. Without increasing, the impurity concentration distribution is such that the effective impurity concentration at the surface of the substrate after the heat treatment is lower than the effective impurity concentration inside the substrate, so that the process can be simplified without increasing the number of processes. Can be planned.

[0036] (Example 2) Next, a description will be given real施例2. In the second embodiment, a step shown in FIG. 9A is added between the steps shown in FIGS. 1B and 1C in the first embodiment. For example, BF2 + which is a p-type impurity is θ = 60 °, D = 2 × 10 ¹² cm ⁻² , Ei = 60k
A step of so-called counter doping in which implantation is performed at eV and Neff = 1 × 10 ¹² cm ⁻² is added. At this time, first, from the source side (broken arrow A) and then from the drain side (solid arrow B), drive into the low-concentration source 4 and the low-concentration drain 5 so that the source side and the drain side are symmetrical. The counter doped region 10 is formed.

Thus, in the low concentration source 4 and the low concentration drain 5 near the end of the gate electrode 3, the concentration of the n-type impurity in the counter-doped region 10 near the surface is further effectively reduced. An impurity concentration profile is obtained below the vicinity of the end of the gate electrode 3 such that the effective impurity concentration near the surface is lower than the internal effective impurity concentration.

Thereafter, a step similar to the step shown in FIG. 1C, that is, a step of forming the sidewall 6 is performed.

Thereafter, as shown in FIG. 9B, arsenic, which is a high-concentration n-type impurity, is ion-implanted using the gate electrode 3 and the side wall 6 as a mask to form a low-concentration source 4 and a low-concentration drain. A high concentration source 7 and a high concentration drain 8 having an impurity concentration higher than 5 are formed.
Heat treatment at 0 ℃ for 10 minutes.

FIG. 10A shows a two-dimensional impurity profile near the low-concentration drain 5 after the process is completed (the p-type impurity concentration of the substrate is about 1 × 10 ¹⁷ cm ⁻³ ). FIG.
FIG. 10B is a diagram for comparison with FIG.
FIG. 4 shows a two-dimensional impurity profile when the implantation of the type impurity BF2 + is not performed, that is, when the counter doping is not performed. Here, in FIGS. 10A and 10B, the solid line shows the concentration of phosphorus which is an n-type impurity which is effectively low, and the dotted line shows the concentration of arsenic which becomes effectively high. together, dark dashed line, the concentration of boron which is a p-type impurity is doped from the first semiconductor substrate 1, the sum of the concentration of boron by the counter-doped
Indicates the degree . 10 (a) and 10 (b), since the upper part of the lightly doped drain 5 into which the n-type impurity is implanted is counter-doped with the p-type impurity BF2 +, the n. It can be seen that the concentration of the type impurity is effectively reduced.

As described above, in the second embodiment, the counter-doped region 10 is formed, and the impurity concentration in the vicinity of the entire surface of the low-concentration source 4 and the low-concentration drain 5 is effectively reduced by implantation of the impurity of the opposite conductivity type. By doing so, the impurity concentration profile targeted by the present invention can be obtained. In this case, a more appropriate concentration distribution can be easily obtained as compared with the case where the impurity concentration distribution of the low-concentration source 4 and the low-concentration drain 5 is adjusted only by implanting one conductivity type impurity as in the first embodiment. . In particular, the effective impurity concentration at the surface of the low-concentration source 4 and low-concentration drain 5 can be further reduced, so that the gate-drain capacitance Cgd can be further reduced.

In the second embodiment, the low-density source 4
And when the low-concentration drain 5 is formed, a concentration distribution is formed in which the effective impurity concentration gradually decreases from the inside of the substrate toward the substrate surface, and then counter doping is performed to further reduce the concentration near the substrate surface. Although thinned, the present invention is not limited to such an embodiment.
Chi words, at the time of forming the lightly doped source 4 and the lightly doped drain 5, keep in a relatively high effective dopant concentration near the surface as normal LATID structure, then the counter doping, the effective near surface The impurity concentration may be reduced. In this case, there is an advantage that the step of forming the low concentration source 4 and the low concentration drain 5 can be performed more easily.

[0043] (Example 3) Next, a description will be given real施例3. In the third embodiment, instead of the injection step shown in FIG.
The step shown in FIG. 11A is performed. For example, in the low-concentration source 4 and the low-concentration drain 5, BF2 + as a p-type impurity is θ = 60 ° , D = 6 × 10 ¹² cm ⁻² , Ei = 60 keV, Neff = 3 × 10 ¹² cm
^By implanting under the condition of ^-2 , a high threshold region 11 is formed in the channel region of the low-concentration source 4 and the drain 5 into which a p-type impurity that is higher in concentration than the p-type impurity of the semiconductor substrate 1 is implanted.

Thereafter, a step of forming the side wall 6 is performed in the same manner as the step shown in FIG.

Thereafter, as shown in FIG. 11B, similarly to the step shown in FIG.
And a step of forming the high concentration drain 8.

FIG. 12A shows a two-dimensional impurity profile near the low-concentration drain 5 after the process is completed (substrate impurity concentration is about 1 × 10 ¹⁷ cm ⁻³ ). FIG.
FIG. 10B is a diagram for comparison with FIG.
FIG. 9 shows a two-dimensional impurity concentration profile in the low-concentration drain 5 when BF2 + which is a p-type impurity is not implanted. In each figure, the solid line, the dotted line, and the broken line indicate the same impurity concentrations as those in FIGS. 10A and 10B. 12A and 12B, since the upper part of the low-concentration drain 5 is counter-doped with BF2 + which is an impurity of the opposite conductivity type, the impurity concentration near the surface of the low-concentration drain 5 is effectively reduced. Since the counter-doped impurity concentration is higher than that of the semiconductor substrate 1, the p-type impurity concentration in the channel region of the low-concentration drain 5 is considerably higher.

As described above, in the third embodiment, the channel regions of the low-concentration source 4 and the low-concentration drain 5 are of a conductivity type opposite to that of the impurities of the regions 4 and 5 and are higher than the impurity concentration of the semiconductor substrate 1. High threshold region 11 into which impurities are implanted
To form That is, in addition to the effect similar to that of the second embodiment, the high-threshold region 11 formed in the channel region on the side of the high-concentration source 7 and the high-concentration drain 5 has a locally high threshold. As the length becomes shorter, the ratio of the high threshold region 11 to the channel becomes larger. Therefore, a short channel effect such as a decrease in threshold voltage due to a reduction in channel length accompanying miniaturization of a semiconductor device can be reduced.

In the first, second, and third embodiments, the NchMOS
Although the example in which the present invention is applied to the type transistor has been described, the present invention can be similarly applied to a PchMOS transistor. Further, the present invention is not limited to MOS transistors, and the insulating film may be a silicon nitride film. That is, the present invention can be applied to all insulated gate field effect transistors.

In each of the above embodiments, the low concentration source 4
And applying the present invention to both the low-concentration drain 5 and
Although an impurity concentration distribution is formed below the vicinity of the end of the gate electrode so that the impurity concentration near the surface is lower than that inside, the concentration distribution may be provided only in one of the regions.

In the first, second, and third embodiments, the impurity implantation into the low-concentration source 4 and the low-concentration drain 5 and the counter doping in the second and third embodiments take two steps in consideration of the symmetry between the source and the drain. Although implantation is used, in this case, if the number of processes is not increased, the direction of the gate must be set in one direction in the semiconductor device, which significantly restricts circuit design. Therefore, in order to enable the gate in both the vertical and horizontal directions, it is more preferable to perform four-step implantation in these implantation steps.

When a PchMOS transistor is simultaneously incorporated in the semiconductor device of the present invention, for example, when a CMOS circuit is used, the counter doping in the second and third embodiments is performed by using the LATID transistor for the PchMOS transistor.
When used together to form a low-concentration source and a low-concentration drain in the structure, it is preferable in that the masking step can be omitted.

[0052]

As described above, according to the first aspect of the present invention, as a method of manufacturing a semiconductor device functioning as an insulated gate type field effect transistor, a gate electrode is formed and a conductive property opposite to that of impurities in a semiconductor substrate is obtained. Forming a low-concentration source / drain region by injecting an impurity of a type, forming a counter-doped region by injecting an impurity of the same conductivity type as that of the semiconductor substrate by inclining the low-concentration source / drain region at a large inclination angle, After the high-concentration source and drain regions are formed, a heat treatment is performed so that the counter-doped region has an impurity distribution in which the effective impurity concentration on the substrate surface is lower than the effective impurity concentration inside the substrate. The implantation conditions for forming the concentration source and drain regions are relatively simple, and the manufacture is easy.

According to the second aspect of the present invention, in the manufacturing method of the first aspect , the semiconductor device is tilted at a larger tilt angle so that impurities are implanted from the low-concentration source / drain region to the substrate surface at a portion connected to the channel. Therefore, high-concentration impurities of the same conductivity type as the impurities in the semiconductor substrate are implanted to form a high threshold region. A region can be formed, and thus a semiconductor device can be miniaturized without causing a short channel effect.

According to the invention of claim 3 , according to claim 1 or
In the manufacturing method 2 , the impurity implantation angle in the step of forming the low-concentration source / drain regions is set to 10 ° to 4 °.
Since the angle is set to 5 °, by appropriately setting the angle of impurity implantation into the low-concentration source and drain regions, the impurity concentration distribution in the region can be particularly improved.

According to a fourth aspect of the present invention, in the manufacturing method of the third aspect , the impurity implantation angle in the high-concentration impurity implantation step of the same conductivity type as that of the semiconductor substrate is at least 25 ° from the normal direction of the semiconductor substrate. Therefore, by appropriately setting the implantation angle of the impurity for forming the high threshold region, the position of the high threshold region and the effective impurity concentration value can be particularly improved.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a MOS transistor according to a first embodiment.

FIG. 2 shows a two-dimensional profile of the impurity concentration near the drain after the process of the MOS transistor according to the first embodiment and the conventional LATID MOS transistor is completed, and a depth direction impurity concentration at the gate electrode end of the transistor. It is a diagram showing a profile.

FIG. 3 shows two-dimensional simulations of the MOS transistor according to the first embodiment and the MOS transistor having a conventional LATID structure in the vicinity of a drain in the horizontal direction with respect to an electric field, an electron concentration, and a hot carrier pair. 6 is a graph showing the distribution of the degree of occurrence in the horizontal direction.

FIG. 4 shows data for comparing the hot carrier deterioration characteristic of the drain current and the ratio of the substrate current to the source current of the MOS transistor according to the first embodiment and the conventional LATID MOS transistor.

FIG. 5 shows data for comparing the short channel effect between the MOS transistor according to the first embodiment and the conventional MOS transistor having a LATID structure.

FIG. 6 shows data for comparing drain saturation currents of the MOS transistor according to the first embodiment and a MOS transistor having a conventional LATID structure.

FIG. 7 shows a MOS transistor according to the first embodiment, a conventional L
This is data for comparing the IV characteristics and the gate voltage dependence of the gate-drain capacitance of the MOS transistor having the ATID structure and the conventional MOS transistor having the LDD structure.

FIG. 8 shows a MOS transistor according to the first embodiment, a conventional L
This is data for comparing the operating speed per stage of the ring oscillator of the MOS transistor having the ATID structure and the conventional MOS transistor having the LDD structure.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of the MOS transistor according to the second embodiment.

FIG. 10 is a diagram showing a two-dimensional profile of an impurity concentration in the vicinity of the drain after the process of the MOS transistor according to the second embodiment and the MOS transistor according to the second embodiment in which the BF2 + implantation is omitted.

FIG. 11 is a cross-sectional view showing a manufacturing process of the MOS transistor according to the third embodiment.

FIG. 12 is a diagram showing a two-dimensional impurity profile of the impurity concentration near the drain after the process is completed in the MOS transistor according to the third embodiment and the MOS transistor in which the BF 2+ implantation is omitted in the third embodiment.

FIG. 13 is a cross-sectional view of a conventional MOS transistor having a LATID structure.

FIG. 14 shows a conventional transistor having a LATID structure and L
FIG. 3 is a diagram of a two-dimensional simulation of a lateral electric field, electron concentration, and the degree of generation of hot carrier pairs in the vicinity of a drain in a MOS transistor having a DD structure.

FIG. 15 is a cross-sectional view of a conventional MOS transistor having a BLDD structure.

FIG. 16 is a sectional view of a MOS transistor having an improved BLDD structure according to the invention of the prior art US Pat.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate oxide film 3 Gate electrode 4 Low concentration source 5 Low concentration drain 6 Side wall 7 High concentration source 8 High concentration drain 10 Counter doping region 11 High threshold region

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/336

Claims (4)

(57) [Claims] 1. A method of manufacturing a semiconductor device, wherein a semiconductor device functioning as an insulated gate field effect transistor is formed on a semiconductor substrate of one conductivity type, wherein the insulated gate field effect on the surface of the semiconductor substrate is provided. Forming the gate electrode on a gate insulating film formed in a portion to be a transistor region; and performing ion implantation of a conductivity type opposite to that of the semiconductor substrate on the surface of the semiconductor substrate using the gate electrode as a mask. Forming a low-concentration source region, using the gate electrode as a mask, performing ion implantation of a conductivity type opposite to that of the semiconductor substrate on the surface of the semiconductor substrate to form a low-concentration drain region; In at least one of the concentration source region and the low concentration drain region, the semiconductor substrate is used with the gate electrode as a mask. Injecting impurities of the same conductivity type as the semiconductor substrate by inclining at a large angle from the normal direction of the semiconductor substrate so that the impurities are implanted from the surface side to the substrate surface portion located below the gate electrode, Forming a counter-doped region on the surface near the end of the gate electrode in the region, and ion implantation of a higher concentration than the ion implantation into the low-concentration source region and the low-concentration drain region using the gate electrode as a mask. Forming the high-concentration source region and the high-concentration drain region, wherein the counter-doped region is formed such that the effective impurity concentration at the surface of the substrate is lower than the effective impurity concentration inside the substrate. Semiconductor device manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein a portion of at least one of the low-concentration source region and the low-concentration drain region is connected to a channel using the gate electrode as a mask. The semiconductor substrate is further tilted from the normal direction of the semiconductor substrate to a larger inclination angle so that the impurity is implanted, and an impurity of the same conductivity type as the impurity of the semiconductor substrate and higher in concentration than the semiconductor substrate is implanted into the region. A method for manufacturing a semiconductor device, comprising a step of forming a high threshold region of the same conductivity type as a semiconductor substrate. 3. The method for manufacturing a semiconductor device according to claim 1 , wherein an impurity implantation angle in the step of forming the low concentration source region or the low concentration drain region is 10 ° to 45 °. Semiconductor device manufacturing method. 4. The method of manufacturing a semiconductor device according to claim 3 , wherein the impurity implantation angle in the impurity implantation step of the same conductivity type as that of the semiconductor substrate is an angle inclined at least 25 ° from the normal direction of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: