KR100587605B1 - High voltage transistor and method of fabricating the same - Google Patents

Abstract

The present invention discloses a high voltage transistor and a method of manufacturing the same. A high voltage transistor of the present invention includes: a first conductivity type substrate having an isolation layer defining an active region; A second conductivity type drift region formed in the active region spaced apart from a boundary of the active region; A gate electrode formed on the first conductive substrate to cross an upper portion of an active region including a second conductive drift region; A channel region formed in an active region under the gate electrode; And a source / drain region formed in an active region in which second conductive drift regions on both sides of the gate electrode are formed.

Description

High voltage transistor and manufacturing method thereof {HIGH VOLTAGE TRANSISTOR AND METHOD OF FABRICATING THE SAME}

1A and 1B are graphs for explaining a conventional problem.
2A is a plan view of a high voltage transistor according to a preferred embodiment of the present invention.

FIG. 2B is a cross-sectional view taken along line II ′ of FIG. 2A;

3 to 5 are process cross-sectional views illustrating a method of manufacturing a high voltage transistor according to a preferred embodiment of the present invention.
Explanation of symbols on the main parts of the drawings
10 substrate 12 device isolation film
14 active region 16 drift region
18 gate electrode 20 channel region
22: source / drain area

The present invention relates to a semiconductor device, and more particularly, to a high voltage transistor capable of increasing breakdown voltage while having a high breakdown voltage, and a method of manufacturing the same.

Transistors driving at high voltages are required to have a high transistor breakdown voltage, and for this purpose, it is necessary to lower the well concentration. This is because the junction breakdown voltage between the well and the source / drain is inversely proportional to the concentration of the junction interface. That is, there is a relationship of Wd ∝ (Nw = well concentration) ^-1/2 between the concentration of the junction interface and the width Wd of the depletion layer, and the junction breakdown voltage increases in proportion to the width of the depletion layer, so that a sufficient breakdown voltage can be obtained. In order to obtain the well concentration must be lowered.
In addition, in order to obtain a sufficiently high junction breakdown voltage, it is necessary to inject the dopants deep into the substrate, and for this purpose, the diffusion property of the dopants must be high during well-drive. Therefore, n-well is currently doped mainly with Phosphorous, and p-well is doped with Boron.
On the other hand, in order to implement an integrated circuit, a large number of active devices are positioned close to each other, so that an isolation layer made of an oxide film is formed by using LOCOS or shallow trench isolation (STI) technology for isolation between devices. Is common. At this time, in the well region in contact with the device isolation film, phosphorus is piled up to increase the interface concentration, while boron is separated to lower the interface concentration.
Thus, as shown in FIG. 1A, in the case of the high voltage PMOS formed on the n well, the Hump phenomenon of bending in the current-voltage curve IV does not appear, as shown in FIG. 1B. In the case of the high voltage NMOS formed on the p well, the hull phenomenon appears in the current-voltage curve due to the lower threshold voltage at the edge of the channel than the center of the channel due to the low interface concentration between the p well at the edge of the channel and the device isolation layer. .
As a result, in the conventional high voltage transistors, humps are generated due to the difference in threshold voltages between the center and the edge of the channel, and thus the device characteristics and reliability are not secured.

Accordingly, an object of the present invention is to provide a high voltage transistor and a method of manufacturing the same, which have been devised to solve a conventional problem and do not generate a hump in a current-voltage curve.

In order to achieve the above object, the present invention provides a high voltage transistor having an active region offset from the channel region and a method of manufacturing the same.

The high voltage transistor includes: a first conductivity type substrate having an isolation layer defining an active region; A second conductivity type drift region formed in the active region spaced apart from a boundary of the active region; A gate electrode formed on the first conductive substrate to cross an upper portion of an active region including a second conductive drift region; A channel region formed in an active region under the gate electrode; And a source / drain region formed in an active region in which second conductive drift regions on both sides of the gate electrode are formed.

In addition, the method of manufacturing the high voltage transistor may include forming a second conductivity type drift region on the first conductivity type substrate; Forming an isolation layer defining an active region including a second conductivity type drift region in the first conductivity type substrate, wherein the boundary of the active region is spaced apart from the boundary of the drift region; Forming a gate electrode across the top of the active region including a drift region on the first conductivity type substrate, and forming a channel region under the gate electrode; And forming a source / drain region on the substrate on which the drift regions on both sides of the gate electrode are formed.

(Example)
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The spirit of the invention is not limited to the embodiments described herein but may be embodied in other forms. Portions denoted by like reference numerals denote like elements throughout the specification.

2A is a plan view of a high voltage transistor according to a preferred embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along line II ′ of FIG. 2A.

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2A and 2B, an isolation layer 12 is formed on the first conductivity type substrate 10 to define the active region 14. A gate electrode 18 is formed across the top of the active region 14. A second conductivity type drift region 16 is formed in the active region 14 at predetermined intervals. The channel region 20 is formed between the drift regions 16. The second conductivity type drift region 16 is formed at a boundary of the active region 14, that is, spaced apart from the device isolation layer 12 by a predetermined distance. An impurity is implanted into a substrate on which the drift region 16 on both sides of the gate electrode 18 is formed to form a source / drain region 22.
Since the width A of the transistor is defined by the drift region 16, the channel region 20 may be formed to be spaced apart from the device isolation layer 12 by a predetermined distance r1. In addition, the distance between the drift region 16 and the device isolation layer 12 may be larger than the diffusion distance of the drift region 16.
In the present invention, the gate electrode 18 is similar to the conventional transistor structure in that it is disposed across the top of the active region 14. However, since the drift region 16 is formed to be spaced apart from the boundary of the active region 14 by a predetermined distance, no channel is formed at the boundary between the active region 14 and the device isolation layer 12. Therefore, in the present invention, the boundary portion of the active region 14 having a low impurity concentration is not used as the channel region of the transistor, and only the active region portion having a uniform impurity concentration is used as the channel region, so that the Hump can be effectively prevented from occurring in the current-voltage curve in the high voltage NMOS transistor formed on the p well.

3 to 5 are process cross-sectional views illustrating a method of manufacturing a high voltage transistor according to a preferred embodiment of the present invention.

Referring to FIG. 3, impurities are implanted into a substrate to form a first conductivity type well. Then, an impurity is implanted into the surface of the substrate on which the first conductivity type well is formed to form the second conductivity type drift region 16.

Referring to FIG. 4, an isolation layer 12 is formed on the substrate to define the active region 14. The device isolation layer 12 may be formed by applying a LOCOS or shallow trench device isolation technique. At this time, the active region 14 includes a second conductivity type drift region 16, and in one direction, is spaced apart from the diffusion boundary of the second conductivity type drift region 16 by a predetermined distance r1. The boundary is defined to be located.

Referring to FIG. 5, ion implantation is performed to adjust a threshold voltage on the substrate. A gate insulating film and a conductive film are sequentially formed on the active region 14, and then patterned to form a gate electrode 18 that crosses the upper portion of the active region 14 including the second conductive drift region 16. The source / drain region 22 is formed by implanting impurities into the substrate on which the second drift region 16 on both sides of the gate electrode 18 is formed. The source / drain regions 22 may be formed by forming sidewall spacers on both sidewalls of the gate electrode 18 and then implanting impurities to align the sidewall spacers.

As a result, the channel region 20 is not formed below the gate electrode 18 in the region adjacent to the isolation layer 12, but only in the drift region 16 spaced a predetermined distance from the isolation layer 12.

As described above, since the drift region is formed to be spaced a predetermined distance from the boundary of the active region, no channel is formed at the boundary between the active region and the device isolation layer. Therefore, in the present invention, the hump is generated in the current-voltage curve of the transistor by not using the active region boundary portion having the low impurity concentration as the channel region, but using only the active region portion having the uniform impurity concentration as the channel region. Can be effectively prevented.

Claims (6)

A first conductivity type substrate on which an isolation layer defining an active region is formed; A second conductivity type drift region formed in the active region spaced apart from a boundary of the active region; A gate electrode formed on the first conductive substrate to cross an upper portion of an active region including a second conductive drift region; A channel region formed in an active region under the gate electrode; And Source / drain regions formed in an active region in which second conductive drift regions are formed on both sides of the gate electrode; High voltage transistor comprising a. The high voltage transistor according to claim 1, wherein the boundary of the active region is located outside the diffusion boundary of the second conductivity type drift region. The high voltage transistor of claim 1, wherein the channel region is spaced apart from a boundary of the active region. Forming a second conductivity type drift region in the first conductivity type substrate; Forming an isolation layer defining an active region including a second conductivity type drift region in the first conductivity type substrate, wherein the boundary of the active region is spaced apart from the boundary of the drift region; Forming a gate electrode across the top of the active region including a drift region on the first conductivity type substrate, and forming a channel region under the gate electrode; And Forming a source / drain region on a substrate on which drift regions on both sides of the gate electrode are formed; Method of manufacturing a high voltage transistor comprising a. The method of claim 4, wherein the boundary of the active region is formed outside the diffusion boundary of the drift region. The method of claim 4, wherein the channel region is formed to be spaced apart from a boundary of the active region.

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