CN117954474A

CN117954474A - Anti-radiation field effect transistor device and application thereof in anti-radiation environment

Info

Publication number: CN117954474A
Application number: CN202211338864.5A
Authority: CN
Inventors: 王明湘; 许会芳; 周国澳; 张冬利; 王槐生
Original assignee: Suzhou University
Current assignee: Suzhou University
Priority date: 2022-10-28
Filing date: 2022-10-28
Publication date: 2024-04-30

Abstract

The application discloses an anti-radiation field effect transistor device and application thereof in an anti-radiation environment, which are used for solving the problem that an anti-radiation method of a field effect transistor in the prior art is limited, wherein the field effect transistor device comprises a substrate; a spacer disposed on the substrate; a semiconductor stack disposed on the spacer, the semiconductor stack comprising: an active layer disposed on the spacer, the active layer including a source region, a drain region, and a channel region between the source region and the drain region; and a gate structure cooperating with the active layer; wherein the spacer is disposed around the semiconductor stack in a direction perpendicular to the substrate, the spacer includes an electric field adjusting portion that intrudes into the channel region in an active layer thickness direction, and the electric field adjusting portion penetrates through the channel region in an active layer width direction.

Description

Anti-radiation field effect transistor device and application thereof in anti-radiation environment

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to an anti-radiation field effect transistor device and application thereof in an anti-radiation environment.

Background

Transistors are widely used in aerospace and electronic devices. These devices, upon exposure to high energy radiation and particles, generate corresponding trapped charges at the oxide layer and material interface. The accumulation of trapped charges at high irradiation doses can have a very serious impact on the lifetime, reliability in use, functionality, etc. of the device, and is a destructive effect that leads to degradation or even failure of the device.

As device process feature sizes decrease, the gate oxide layer becomes thinner and thinner. This results in an irradiation of a smaller and smaller amount of trapped charges generated in the gate oxide layer. When the thickness of the gate oxide layer is less than 10nm, the influence of gate oxide is not considered because the irradiation-induced trap charge is negligible. For buried oxide of SOI (silicon-on-insulator) devices, existing radiation-resistant reinforcement measures are buried oxide by high dose silicon ion implantation, which can create electron traps with large trapping cross-sections that can trap electrons to compensate for the trapping positive charges induced in the buried oxide by the total dose effect. For the field oxide of FDSOI (fully depleted SOI) devices, the structure of the gate is changed, such as an H-type gate, a ring gate, a P+ heavy doping isolation and a radiation-resistant reinforcing structure of a Z-type gate. These reinforcing structures are all essentially designed to reduce degradation of device characteristics caused by irradiation trapping charges by blocking the conduction of field oxide sidewall parasitic transistors under irradiation.

The information disclosed in this background section is only for enhancement of understanding of the general background of the application and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The application aims to provide an anti-radiation field effect transistor device which is used for solving the problem that an anti-radiation method of a field effect transistor in the prior art is limited.

To achieve the above object, the present application provides a radiation-resistant field effect transistor device comprising:

A substrate;

a spacer disposed on the substrate;

a semiconductor stack disposed on the spacer, the semiconductor stack comprising:

An active layer disposed on the spacer, the active layer including a source region, a drain region, and a channel region between the source region and the drain region; and

A gate structure cooperating with the active layer;

Wherein the spacer is disposed around the semiconductor stack in a direction perpendicular to the substrate, the spacer includes an electric field adjusting portion that intrudes into the channel region in the active layer thickness direction, and the electric field adjusting portion penetrates through the channel region in the active layer width direction.

In an embodiment, at least part of the interface normal electric field intensity between the electric field adjusting portion and the active layer is smaller than a reference electric field intensity, wherein the reference electric field intensity is the interface normal electric field intensity between the active layer and a part of the separator except for the electric field adjusting portion.

In an embodiment, the material of the electric field adjusting portion is one or a combination of SiO ₂、Si₃N₄、SiO_xN_y、HfO₂、Al₂O₃.

In an embodiment, the electric field adjusting part has a gradually decreasing cross-sectional area, a gradually increasing cross-sectional area, or a constant cross-sectional area in a direction away from the substrate.

In an embodiment, the gate structure may control the channel region and form a channel therein connecting the source region and the drain region, and the electric field adjusting part may have a space from the channel in a thickness direction.

In one embodiment, the length ratio of the electric field adjusting portion to the channel region is 1:1 to 1:3, preferably 1:1 to 1:2.5, more preferably 1:2.

In one embodiment, when the device is turned on, an effective channel and an equivalent source region and/or an equivalent drain region which are far away from the effective channel at least in the thickness direction of the channel region are formed in the channel region, and the field effect transistor device is communicated with the source region and the drain region through the effective channel and the equivalent source region and/or the equivalent drain region to contribute to working current; preferably, the method comprises the steps of,

And on a plane perpendicular to the length direction of the effective channel, the perpendicular projection of the equivalent source region and the equivalent drain region is positioned in the perpendicular projection of the electric field regulating part.

In one embodiment, a conductive region is formed in the channel region that does not communicate with the source region and the drain region; wherein,

When the conductive region is communicated with the source region, the conductive region forms the equivalent source region; and/or the number of the groups of groups,

When the conductive region communicates with the drain region, the conductive region constitutes the equivalent drain region.

In one embodiment, the gate structure and the vertical projection of the conductive region onto the channel region overlap; wherein,

The gate structure may control the channel region and form a channel therein, a portion of the channel that does not overlap between perpendicular projections of the conductive region on the channel region constituting the effective channel.

The application also provides an application of the field effect transistor device in an irradiation-resistant environment, wherein the field effect transistor device is the irradiation-resistant field effect transistor device.

Compared with the prior art, in the embodiment of the application, the electric field regulating part which invades the channel region in the thickness direction of the active layer is arranged in the isolator of the device, and penetrates through the channel region in the width direction of the active layer, so that the contact interface of the electric field regulating part and the active layer can be changed, and the electric field in the isolator is correspondingly partially isolated, so that the concentration of trapped charges at the interface of the electric field regulating part and the active layer is lower, the degradation of the device characteristic is small, and the anti-radiation characteristic of the device is enhanced.

Drawings

FIGS. 1-7 are schematic structural diagrams of various embodiments of a radiation-resistant field effect transistor device according to the present application;

Fig. 8-10 are schematic structural diagrams of a conductive region formed in a radiation-resistant field effect transistor device according to various embodiments of the present application;

FIGS. 11-14 are schematic structural diagrams of various embodiments of a radiation-resistant field effect transistor device according to the present application;

FIGS. 15-22 are schematic diagrams illustrating fabrication of conductive regions according to various embodiments of the present application;

FIGS. 23-25 are schematic diagrams of the structure of SOI devices to which the aspects of the present application are applied;

Fig. 26 is a schematic structural view of an embodiment of the present application having a space between the vertical projections of the active channel and the conductive region of the radiation-resistant field effect transistor device on the channel region;

FIGS. 27 to 31 are graphs showing transfer characteristics of the respective devices in simulation examples 1 to 5 of the present application, respectively;

FIGS. 32 to 33 are simulation diagrams showing lengths of the trap trapped charges and the normal electric field intensity of the interface along the channel direction of the first portion of the interface between the active layer and the spacer in simulation example 6 of the present application, respectively;

fig. 34 to 35 are simulation diagrams of lengths in the channel direction of the interface trap trapped charges and the interface normal electric field intensity of the second portions of the active layer and the spacer, respectively, in simulation example 6 of the present application.

Detailed Description

The present application will be described in detail below with reference to the embodiments shown in the drawings. The embodiments are not intended to limit the application, but structural, methodological, or functional modifications of the application from those skilled in the art are included within the scope of the application.

Referring to fig. 1, an embodiment of a radiation-hard field effect transistor device 100 of the present application is described. In the present embodiment, the irradiation-resistant field effect transistor device 100 includes a substrate 40, an isolation layer 30, and a semiconductor stack.

In some embodiments, substrate 40 may comprise an elemental semiconductor (including silicon or germanium in crystalline, polycrystalline, or amorphous structures); compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and indium antimonide); alloy semiconductors (including SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and GaInAsP); any other suitable material or combination thereof. In some embodiments, the substrate 40 may comprise a p-type material, and in other embodiments, the substrate 40 may comprise an n-type material.

The spacer 30 is disposed on the substrate 40, and the semiconductor stack is disposed on the spacer 30. In this embodiment, the semiconductor stack includes an active layer 10 and a gate structure 20. The spacer 30 is used at least to separate semiconductor stacks between different devices and is mated with the substrate 40 to form a semiconductor-on-insulator structure (SOI, i.e., a semiconductor stack fabricated on an insulating layer).

Specifically, the active layer 10 is disposed on the spacer 30, and the active layer 10 may be the same as or different from the material of the original substrate 40. The growth of the active layer 10 may be performed by a known semiconductor growth method, such as chemical vapor deposition, including epitaxial growth. Structurally, the active layer 10 includes a source region 101, a drain region 102, and a channel region 103. A source region 101 and a drain region 102 are located on both sides of the active layer 10, respectively, and a channel region 103 is located between the source region 101 and the drain region 102.

The gate structure 20 may control the formation of a channel in the channel region 103 of the field effect transistor device 100 connecting the source region 101 and the drain region 102, thereby causing the device to turn on. Specifically, the gate structure 20 includes a gate insulating layer 22 and a gate electrode 21 disposed on the gate insulating layer 22, and in some embodiments, the gate insulating layer 22 may be formed of a high-k material, such as zirconium dioxide (ZrO ₂), aluminum oxide (Al ₂O₃), hafnium oxide (HfO ₂), tantalum oxide (Ta ₂O₅), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium silicate, zirconium aluminate, silicon nitride, silicon oxynitride, titanium oxide, hafnium oxide-aluminum oxide (HfO ₂-Al₂O₃) alloy, combinations thereof, and the like. In some embodiments, the gate 21 may comprise a metal, such as aluminum, titanium, copper, tungsten, tantalum, etc., or doped polysilicon.

In the present embodiment, the spacer 30 is also disposed around the semiconductor stack in a direction perpendicular to the substrate 40 (i.e., a top view direction with respect to the substrate 40). Thus, the spacer 30 may be considered to isolate the semiconductor stack in at least two ways: in one aspect, the spacer 30 includes a first portion 301 between the substrate 40 and the semiconductor stack, thereby isolating the semiconductor stack from the substrate 30; on the other hand, the separator 30 further includes a second portion 302 and a third portion 303 disposed around the semiconductor stack, thereby separating the semiconductor stack from other semiconductor stacks on the side.

It should be noted that the first portion 301, the second portion 302, and the third portion 303 in the separator 30 do not mean that the separator is structurally or materially divided into different portions, but are merely for convenience of description. Illustratively, the second portion 302 and the third portion 303 of the separator 30 may be formed at one time in some embodiments and may be of the same material. Of course, in some embodiments, the first portion 301 of the separator 30 may also be a material different from the second and third portions 302, 303 and formed by different steps.

Referring to fig. 2 and 3 in particular, the first portion 301 of the separator 30 may be formed of, for example, siO ₂、HfO₂、Al₂O₃ or other suitable oxide material. Illustratively, in the silicon substrate 40, the first portion 301 may be a silicon oxide layer. For example, the first portion 301 may be formed by implanting oxygen ions through the top surface of the substrate 40 in the thickness direction of the silicon substrate 40, and then annealing the silicon substrate 40 with the implanted oxygen ions. The first portion 301 may be formed substantially parallel to a top surface of the substrate 40, at a distance from the top surface that is less than the thickness of the substrate 40. The first portion 301 may extend in at least one lateral direction (i.e., a direction parallel to the top surface of the substrate 40).

Further, the second and third portions 302 and 303 may be formed in the trench by depositing an insulating material filling the trench on the first portion 301 (e.g., using a CVD process or a spin-on-glass process), and performing a Chemical Mechanical Polishing (CMP) process to remove excess insulating material and/or planarize. The deposition process may be a Flowable CVD (FCVD) process, a high aspect ratio deposition (HARP) process, a High Density Plasma CVD (HDPCVD) process, other suitable deposition process, or a combination thereof.

In some embodiments, the second portion 302 and the third portion 303 of the spacer 30 may have a multi-layer structure, such as an oxide layer disposed over a silicon nitride liner. In some embodiments, the second portion 302 and the third portion 303 include a dielectric layer disposed over a doped liner including, for example, borosilicate glass (BSG) or phosphosilicate glass (PSG). In some embodiments, the second portion 302 and the third portion 303 include a bulk dielectric layer disposed over the dielectric liner. The second portion 302 and the third portion 303 comprise silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or combinations thereof. The second portion 302 and the third portion 303 may be configured as Shallow Trench Isolation (STI) structures, deep Trench Isolation (DTI) structures, local oxidation of silicon (LOCOS) structures, and/or other suitable isolation structures.

The spacer 30 includes an electric field adjusting portion 304 penetrating into the channel region 103 in the thickness direction of the active layer 10, and the electric field adjusting portion 304 penetrates through the channel region 103 in the width direction of the active layer 10. It will be appreciated that the penetration of the spacers 30 is not a penetration type penetration in the thickness direction of the active layer 10, and the penetration of the spacers 30 should not affect the formation of a channel when the device is turned on.

In each embodiment/example of the present application, the direction from the source region 101 to the drain region 102 of the active layer 10 is referred to as the longitudinal direction of the active layer 10, the direction perpendicular to the substrate 40 is also referred to as the thickness direction of the active layer 10, and the width direction of the active layer 10 is the direction perpendicular to the longitudinal direction of the active layer 10. Correspondingly, the electric field adjusting portion 304 penetrates the channel region 103 in the width direction of the active layer 10, that is, means: the electric field adjusting portion 304 communicates with the second portion 302.

In the embodiments of the present application, the specific shape of the electric field adjusting section 304 is not limited. The electric field adjusting portion 304 may have a regular shape as a whole, such as a rectangular parallelepiped shape shown in fig. 1, an inverted trapezoidal shape shown in fig. 4, and a regular trapezoidal shape shown in fig. 5, one "face" of the electric field adjusting portion 304 being in contact with the first portion 301 of the separator 30, and

In the embodiment shown in fig. 4, the electric field adjusting portion 304 has a gradually increasing cross-sectional area in a direction away from the substrate 40,

In the embodiment shown in fig. 5, the electric field adjusting portion 304 has a gradually decreasing cross-sectional area in a direction away from the substrate 40, whereas in the embodiment shown in fig. 1, the electric field adjusting portion 304 has a constant cross-sectional area in a direction away from the substrate 40; still alternatively, the electric field adjusting part 304 may be irregularly shaped, such as the embodiment shown in fig. 6.

Based on the above structure proposed by the embodiment of the present application, at least part of the interface normal electric field intensity between the electric field adjusting portion 304 and the active layer 10 is smaller than the reference electric field intensity, which is the interface normal electric field intensity between the active layer 10 and the part of the separator 30 other than the electric field adjusting portion 304. That is, the arrangement of the electric field adjusting portion 304 corresponds to changing the electric field in the corresponding portion of the separator 30 at the interface where it contacts the active layer 10, which results in a lower concentration of trapped charges at the interface of the electric field adjusting portion 304 and the active layer 10, thereby making the degradation of the device characteristics small and enhancing the anti-irradiation characteristics of the device. It will be appreciated that the interface trap trapping charges described herein originate from ionized charges excited by the irradiation of the separator 30.

In some embodiments, the material of the electric field adjusting portion 304 may be one or a combination of SiO ₂、Si₃N₄、SiO_xN_y、HfO₂、Al₂O₃. Dimensionally, the length ratio of the electric field adjusting portion 304 to the channel region 103 is 1:1 to 1:3, preferably 1:1 to 1:2.5, more preferably 1:2; the electric field adjusting portion 304 is spaced from the channel in the thickness direction, that is, when the gate structure 20 controls the channel region 103 and forms the channel 104 therein, the electric field adjusting portion 304 is preferably disposed so as not to affect the formation of the channel 104, and on the premise that the larger the thickness of the electric field adjusting portion 304, the better the radiation resistance of the device will be. Of course, in different embodiments, the material of the electric field adjusting portion 304 may be the same as or different from any one of the first portion 301, the second portion 302, and the third portion 303 of the spacer 30 according to the device requirement.

In some embodiments, the electric field regulating portion 304 of a suitable dielectric material may be formed on the substrate 40 by deposition and etching processes, etc., and the active region 10 of the device may be fabricated on the substrate 40 on which the electric field regulating portion 304 has been formed. In other embodiments, taking the silicon substrate 40 as an example, after the first portion 301 of the spacer 30 is formed by oxygen ion implantation, the first portion 301 of the spacer 30 with a partial thickness on a partial area may be removed by an etching process or the like, and the first portion 301 of the spacer 30 and the electric field adjusting portion 304 may be integrally formed.

Referring to fig. 7, another embodiment of the radiation-hard field effect transistor device 100 of the present application will be described. Unlike the previous embodiment, in the present embodiment, when the device is turned on, an effective channel 1041 and equivalent source and drain regions 1051 and 1052 distant to the effective channel 1041 in the thickness direction of the channel region 103 are formed in the channel region 103 of the field-effect transistor, and the field-effect transistor device 100 communicates the source and drain regions 101 and 102 through the effective channel 1041, the equivalent source region 1051, and the equivalent drain region 1052 to contribute an operating current.

In some embodiments of the application, the "distance" between the effective channel 1041 and the equivalent source and drain regions 1051, 1052 may include a distance in the length direction of the channel region in addition to the thickness direction of the channel region. In these embodiments, whether the channel region is distant in thickness or length, it is limited that the effective channel 1041, the equivalent source region 1051, and the equivalent drain region 1052 are not affected when the device is turned on, and the source region 101 and the drain region 102 are in communication.

In a typical field effect transistor device 100, a source region 101 in the active layer 10 is used to provide carriers when the device is on, and a drain region 102 is used to collect carriers provided by the source region 101. Correspondingly, in the present application, the mentioned equivalent source region 1051 refers to a structure in which part of carriers supplied from the source region 101 are directly injected into the effective channel 1041, and the equivalent drain region 1052 refers to a structure in which part of carriers are directly received from the effective channel 1041 and injected into the drain region 102.

The "effective channel 1041" referred to in the present application refers to a portion of a channel through which carriers, which are operating current, pass when the device is turned on. In this embodiment, the gate structure 20 may be controlled to have a channel 104 formed thereunder, and the channel 104 is structurally connected to the source region 101 and the drain region 102. However, from a functional point of view, only the portion of the channel 104 that does not overlap with the vertical projection of the equivalent source region 1051 and the equivalent drain region 1052 onto the channel region 103 is used to transmit the entire operating current, and therefore only this portion of the channel will be referred to as the "effective channel 1041" herein.

In this embodiment, the carrier path at device turn-on includes two main parts: one part is from the source region 101 into the equivalent source region 1051, the effective channel 1041, the equivalent drain region 1052, and the drain region 102 in order, and the other part is from the source region 101 directly into the drain region 102 through the channel 104. The remaining portions of the channel 104, excluding the effective channel 1041, are used to transmit only a portion of the operating current as seen in the carrier path.

It can be seen that the effective channel 1041 in the present application is not limited to having a different device structure or parameter set per se than the remainder of the channel 104. Indeed, in some embodiments, the channel 104 may be formed integrally in the channel region, and only through the arrangement of the equivalent source region 1051 and the equivalent drain region 1052, so that when the device is turned on, carriers provided by the source region 101 are not directly injected into the drain region 102 all through the channel 104. While the regulation of the channel, such as changing the work function of the gate structure of the corresponding portion of the effective channel, the thickness of the gate insulating layer, etc., which may be shown in some embodiments below, should not be considered as a necessary precondition for forming the effective channel.

The provision of the equivalent source region 1051 and the equivalent drain region 1052 corresponds to shortening the length of the portion of the channel 104 that can fully conduct the operating current, i.e., the effective channel 1041 is spaced from the source region 101 and the drain region 102. And, the equivalent drain region 1052 in communication with the drain region 102 is structurally far from the effective channel 1041, reducing the effect of the drain potential on the effective channel 1041; while the equivalent source region 1051 in communication with the source region 101 is structurally remote from the effective channel 1041, the potential of the equivalent source region 1051 remains coincident with the source region (typically zero potential) and the effect of the drain potential on the effective channel 1041 is likewise reduced to improve the short channel effect of the device.

Referring to fig. 8 in conjunction, in the specific preparation of the equivalent source region 1051 and the equivalent drain region 1052, by forming a conductive region a in the channel region 103 which does not communicate with the source region 101 and the drain region 102, when the conductive region a communicates with the source region 101, the portion of the conductive region a constitutes the equivalent source region 1051; when conductive region a communicates with drain region 102, this portion of conductive region a constitutes an equivalent drain region 1052.

When the device is turned on, the conductance of the conductive region a is set to be greater than the conductance of the remaining portion 1042 of the channel 104 excluding the effective channel 1041, so that carriers can be injected between the conductive region a and the effective channel 1041. In this way, carriers of the source region 101 are attracted by the more conductive equivalent source region 1051 and are not directly injected all the way into the channel 104 to the remainder 1042 of the channel 104 directly connected to the source region 101; also, carriers transported in the active channel 1041 will be attracted by the dummy drain 1052 and will not all be transported through the remainder 1042 of the channel 104.

To achieve the carrier injection arrangement herein between the equivalent source region 1051, the equivalent drain region 1052, and the effective channel 1041, the conductance of the conductive region a may be set to be at least three times greater than the conductance of the remainder 1042 of the channel 104 except for the effective channel 1041. Further, since carriers flow in the thickness direction of the channel region 103 during the above-described "injection", the interval between the conductive region a and the effective channel 1041 in the thickness direction of the channel region 103 in this embodiment may be set to 5nm to 10 μm, or more preferably 10nm to 1 μm, or more preferably 10nm to 100nm according to the specific design of the device, so as to ensure normal injection of carriers and performance of the device.

In various embodiments, the morphology and location of the conductive areas a may be set according to the application requirements of the device and are not limited to the form shown in fig. 3. For example, the conductive regions A1, A2 in the field effect transistor device 100 shown in fig. 9 may be of a region shape having a larger overall thickness and irregularities with respect to fig. 8. As another example, the conductive regions A1, A2 in the field effect transistor device 100 shown in fig. 10 are not located at the same height in the thickness direction of the channel region.

It should be noted that "carrier" mentioned in the present application refers to a charge particle capable of freely moving in the corresponding polar channel/conductive region a, and generally, we refer to an electron in an N-type channel or a hole in a P-type channel as "carrier" herein, and correspondingly, a hole in an N-type channel or an electron in a P-type channel is not referred to as "carrier" herein, so that the polarities of the effective channel 1041 and the conductive region a are set to be the same in the present application, so that the carrier interaction between the two channels can ultimately substantially contribute to the operation current of the device.

It can be seen that when the device is turned off, it is possible, for example, to control the channel 104 to be turned off by the gate structure 20, and the effective channel 1041 correspondingly "disappears". In these embodiments, the equivalent source region 1051 and the equivalent drain region 1052 may not disappear with the disappearance of the effective channel 1041, i.e., the equivalent source region 1051 and the equivalent drain region 1052 may still be present in the channel region 103 when the device is turned off.

Referring to fig. 11, a further embodiment of a field effect transistor device 200 of the present application is described.

Unlike the above-described embodiments, in the present embodiment, at the time of device on, an equivalent drain region is not formed in the channel region 103 at this time. The field effect transistor device 200 communicates with the source region 101 and the drain region 102 through the effective channel 1041, the equivalent source region 1051 to contribute to the operating current.

In this embodiment mode, the influence of the drain potential on the potential in the vicinity of the source of the channel region 103 is reduced by the arrangement of the equivalent source region 1051 alone, thereby improving the short channel effect of the device. Correspondingly, the effective channel 1041 is directly connected to the drain region 102.

When the device is turned on, in carrier transport, a carrier portion provided by the source region 101 enters the equivalent source region 1051, and is injected into the effective channel 1041 from an end of the equivalent source region 1051 remote from the source region 101; carriers flowing through the active channel 1041 are re-injected back into the drain region 102. That is, in this embodiment, only the conductive region unidirectionally injects carriers into the effective channel 1041.

Referring to fig. 12, a further embodiment of a field effect transistor device 300 of the present application is described.

Unlike the above embodiment, in this embodiment, at the time of device on, an equivalent source region is not formed in the channel region 103 at this time. The field effect transistor device 300 communicates with the source region 101 and the drain region 102 through the effective channel 1041, the equivalent drain region 1052 to contribute to the operating current.

In this embodiment mode, the influence of the drain potential on the effective channel 1041 is reduced by the arrangement of the equivalent drain region 1052 alone, thereby improving the short channel effect of the device. Correspondingly, the effective channel 1041 is directly connected to the source region.

When the device is turned on, in carrier transport, carriers provided by the source region 101 enter the effective channel 1041, and part of the carriers are injected into the equivalent drain region 1052 from an end of the effective channel 1041 away from the source region 101, and are re-injected back into the drain region 102. That is, in this embodiment, only the effective channel 1041 unidirectionally injects carriers into the conductive region.

In the above-described embodiment, a structure in which a part of a channel formed by gate structure control constitutes an effective channel has been shown. In such a structure, in order to further improve the ability of the device to suppress short channel effects, the conductance per unit length of the effective channel in the channel may be set smaller than the conductance per unit length of the rest of the channel except for the effective channel. Some corresponding embodiments are described below.

Referring to fig. 13, a further embodiment of a field effect transistor device 400 of the present application is described.

In this embodiment, the gate structure 20 includes the gate insulating layer 22 and the gate electrode 21, and the thickness of the gate insulating layer 222 corresponding to the effective channel 1041 is greater than the thickness of the remaining gate insulating layer 221. That is, the gate insulating layer 221 of the corresponding portions of the equivalent source region 1051 and the equivalent drain region 1052 is relatively thinned, so that the modulating capability of the corresponding gate of the channel 1042 except the effective channel 1041 to the corresponding partial channel 1042 can be enhanced, and the conductance of the corresponding partial channel 1042 can be increased.

In the present embodiment, the dielectric constant of the gate insulating layer 222 corresponding to the effective channel 1041 may be set smaller than that of the remaining gate insulating layer 221, so as to further increase the conductance of the channel 1042 other than the effective channel 1041.

Referring to fig. 14, a further embodiment of a field effect transistor device 500 of the present application is described.

In this embodiment, the gate structure 20 includes the gate insulating layer 22 and the gate 21, and the portion 211 and the remaining portion 212 corresponding to the effective channel 1041 in the gate 21 are made of different materials, so that the portion 211 and the remaining portion 212 corresponding to the effective channel 1041 in the gate 21 have different modulating capability on the correspondingly formed channel, and the conductance per unit length of the effective channel 1041 is smaller than the conductance of the remaining portion 1042 except for the effective channel 1041 in the channel 104.

In this embodiment, if the field effect transistor device 500 is an N-type device, the work function of the portion 211 of the gate 21 corresponding to the effective channel 1041 is set to be larger than the work function of the remaining portion 212 of the gate 21; correspondingly, if the field effect transistor device 500 is a P-type device, the work function of the portion 211 of the gate 21 corresponding to the effective channel 1041 is set to be smaller than the work function of the remaining portion 212 of the gate 21.

Specifically, in the case of an N-type device, the portion 211 of the gate 21 corresponding to the effective channel 1041 may employ a metal having a larger work function, such as gold, platinum, or P-type doped (p+) polysilicon, or ITO, ruO2, WN, moN, or the like having a larger work function obtained by adjusting the composition of the compound, as the gate material; the remainder 212 may employ a smaller work function metal such as aluminum, hafnium, titanium, or N-doped (n+) polysilicon, or a smaller work function Ru-Hf, WN, hfN, tiN, taN, taSiN, etc., obtained by tuning the composition of the compound, as the gate material. In the case of a P-type device, the portion 211 of the gate 21 corresponding to the effective channel 1041 may employ a metal with a smaller work function, such as aluminum, hafnium, titanium, or N-doped (n+) polysilicon, or Ru-Hf, WN, hfN, tiN, taN, taSiN, etc. with a smaller work function obtained by adjusting the composition of the compound, as the gate material; the remainder 212 may employ a larger work function metal such as gold, platinum, or P-doped (p+) polysilicon, or ITO, ruO ₂, WN, moN, etc. of larger work functions obtained by tuning the composition of the compound as the gate material.

The following description describes the formation of conductive regions in accordance with embodiments of the present application:

Example 1

The conductive region is formed by doping the channel region 103A with incoming carriers at a side surface remote from the effective channel 1041A.

Correspondingly, referring to fig. 15, in the case of an N-type silicon-based device 100A, the doping concentration of the interface may be varied by doping donor atoms, such as phosphorus, arsenic, etc., at the surface of the channel region 103A remote from the active channel 1041A; referring to fig. 16, in the case of a P-type silicon-based device 100A, the doping concentration of the interface may be varied by doping acceptor atoms, such as boron, at the surface of the channel region 103A remote from the active channel 1041A.

Example 2

Referring to fig. 17 and 18 in combination, the field effect transistor device 100B includes a first portion 301B of a spacer disposed on a side surface of the active layer 10B remote from the effective channel 1041B, and a conductive region a is formed on a side surface of the channel region by electrostatic induction from implanted charges in the first portion 301B.

Correspondingly, referring to fig. 17, in the case of an N-type device, this can be achieved by locally injecting positive charges, e.g., h+, holes, in the first portion 301B; referring to fig. 18, in the case of a P-type device, this may be achieved by locally implanting negative charges, such as F-, cl-, electrons, etc., in the first portion 301B. In this manner, a high density of fixed charges is formed in the first portion 301B, and carriers of the conductive region a are generated by electrostatic induction at the channel region 103B adjacent to the first portion 301B. Here, "local" refers to a partial region of the first portion 301B corresponding to the channel region where the conductive region a is to be formed.

In a specific charge implantation process, charges may be implanted in the first portion 301B at a position more adjacent to the channel region 103B, so that the conductive region a formed in the channel region 103B can store more carriers. Of course, in some other alternative embodiments, a "dual insulating layer" structure may be further used, specifically including a charge trapping layer disposed on the surface of the channel region 103B, and a conventional insulating layer covering the charge trapping layer, where the charge trapping layer may be made of a material that is easier to store charges, or nano-particles of metal or semiconductor are introduced therein, so as to store charges more stably, thereby ensuring stable and controllable carriers in the conductive region.

Example 3

Referring to fig. 19, the field effect transistor device 100C includes a semiconductor material layer 50C disposed on an active layer 10C, the semiconductor material layer 50C and the active layer 10C constituting a heterostructure, and a conductive region a formed of two-dimensional electron gas channels or two-dimensional hole gas channels distributed in the heterostructure.

Specifically, the semiconductor material layer 50C and the active layer 10C have different band gap widths, and the semiconductor material layer 50C may be divided into two parts connected to the source region 101C and the drain region 102C, respectively, so that the formed two-dimensional electron gas channel does not conduct the source and drain regions.

Of course, in some alternative embodiments, the channel region 103C may be further surface treated to form a two-dimensional electron gas channel or a two-dimensional hole gas channel, which are well known to those skilled in the art, and are within the scope of the present application. Also, the semiconductor material layer 50C may be a barrier layer, which may be doped or intrinsic.

Example 4

Referring to fig. 20, a field effect transistor device 100D is fabricated as a device including at least two gates. Specifically, the field effect transistor device 100D includes a first gate insulating layer 30D and a first gate electrode 20D sequentially disposed on one side surface of the active layer 10D, and a second gate insulating layer 40D and a second gate electrode 50D sequentially disposed on one side surface of the active layer 10D adjacent to the conductive region a.

The second gate 50D is correspondingly divided into two parts, one part of the vertical projection on the active layer 10D being connected to the source region 101D and the other part of the vertical projection on the active layer 10D being connected to the drain region 102D. Thus, when an appropriate bias is applied to the two portions of the second gate 50D, conductive regions a communicating with the source region 101D and communicating with the drain region 102D can be formed at corresponding positions in the channel region 103D, respectively.

In this embodiment, the absolute value of the bias voltage applied to the second gate 50D should be greater than the absolute value of the turn-on voltage applied to the device. Correspondingly, if an N-type device, a positive bias greater than the first gate 20D is applied to the second gate 50D; in the case of a P-type device, a negative bias voltage is applied to the second gate 50D that is greater in absolute value than the first gate 20D.

Example 5

Referring to fig. 21, a field effect transistor device 100E is fabricated to include at least two gates similar to embodiment 4. However, in this embodiment, in order to enable the conductance of the conductive region a to be larger than the conductance of the portion 1042E of the channel 104E other than the effective channel 1041E, the first gate 20E and the second gate 50E of different work function gate materials may be used. Namely: the work function difference between the first gate electrode 20E and the active layer 10E and the work function difference between the second gate electrode 50E and the active layer 10E are not equal.

Correspondingly, in the case of an N-type device, the first gate 20E may employ a metal with a larger work function, such as gold, platinum, or P-doped (p+) polysilicon, or ITO, ruO2, WN, moN, etc. with a larger work function obtained by adjusting the composition of the compound, as the gate material; the second gate 50E may employ a smaller work function metal such as aluminum, hafnium, titanium, or N-doped (n+) polysilicon, or Ru-Hf, WN, hfN, tiN, taN, taSiN, etc. with a smaller work function obtained by adjusting the composition of the compound, as the gate material. In the case of a P-type device, the first gate 20E may employ a metal with a smaller work function, such as aluminum, hafnium, titanium, or N-doped (n+) polysilicon, or Ru-Hf, WN, hfN, tiN, taN, taSiN, etc. with a smaller work function obtained by adjusting the composition of the compound, as the gate material; the second gate 50E may employ a metal with a larger work function such as gold, platinum, or P-doped (p+) polysilicon, or ITO, ruO2, WN, moN, etc. with a larger work function obtained by adjusting the composition of the compound, as the gate material.

In the N-type device, the difference between the work function of the first gate 20E and the work function of the active layer 10E may be greater than zero (Φms > 0V), so that the channel 104E is an enhanced channel; meanwhile, the work function difference between the second gate electrode 50E and the active layer 10E is set to be smaller than zero (Φms < 0V), so that the conductive region a can form a certain number of carriers under the bias applied thereto in the device off state. In a P-type device, the work function difference between the first gate 20E and the active layer may be set to be less than zero (Φms < 0V), so that the channel 104E is an enhanced channel; meanwhile, the work function difference between the second gate electrode 50E and the active layer 10E is set to be greater than zero (Φms > 0V), so that the conductive region a can form a certain number of carriers under the bias applied thereto in the device off state.

Example 6

Referring to fig. 22, a field effect transistor device 100F is fabricated to include at least two gates 20F, 50F similar to embodiment 4. However, in the present embodiment, in order to enable the conductance of the conductive region a to be larger than the conductance of the portion 1042F of the channel 104F other than the effective channel 1041F, the capacitance per unit area of the second gate insulating layer 40F may be set larger than the capacitance per unit area of the first gate insulating layer 30F.

Specifically, this can be achieved by adjusting the dielectric constants of the first gate insulating layer 30F and the second gate insulating layer 40F, or the thicknesses of the first gate insulating layer 30F and the second gate insulating layer 40F.

For example, when the thicknesses of the first gate insulating layer 30F and the second gate insulating layer 40F are equal, only the dielectric constant factor of the gate insulating layer may be considered, and the dielectric constant of the first gate insulating layer 30F higher than the dielectric constant of the second gate insulating layer 40F may be set. Illustratively, the first gate insulating layer 30F may employ silicon dioxide, and the second gate insulating layer 40F may employ a high-permittivity dielectric such as hafnium oxide, aluminum oxide, or the like.

For another example, when the first gate insulating layer 30F and the second gate insulating layer 40F are made of the same material, only the thickness of the gate insulating layer may be considered, and the thickness of the second gate insulating layer 40F may be set smaller than that of the first gate insulating layer 30F.

In a specific device application, the second gate in embodiments 4 to 6 may also be directly floating or grounded, so as to avoid excessive device connection terminals increasing the complexity of the device application.

In addition, the conductive regions may be formed by combining the conductive regions in the above embodiments, so as to achieve a better implementation effect.

Example 7

Referring to fig. 23, a field effect transistor device 100G is shown as a planar top gate structure TFT device and includes a light transmissive insulating substrate 40G formed with spacers 41G, and an active layer 10G, a gate dielectric layer 30G, and a gate electrode 20G sequentially disposed on the spacers 41G. The two sides of the active layer 10G are doped to form a source region 101G and a drain region 102G respectively, and are externally connected with a source electrode and a drain electrode respectively; the channel region 103G is located between the source region 101G and the drain region 102G.

Positive charge regions 60G are formed on the spacers 41G on both sides of the source region 101G and the drain region 102G by ion implantation or the like. The positive charge region 60G and the gate electrode 20G have an overlapping portion between the vertical projections of the channel region 103G, and correspondingly, the positive charge region of the overlapping portion may form a two-dimensional electron gas 70G in the channel region 103G connected to the source region 101G and the drain region 102G, respectively, where the two-dimensional electron gas 70G also forms a conductive region, and the carrier blocking region 80G is formed between the two-dimensional electron gas 70G connected to the source region 101G and the drain region 102G.

When the device is turned on, a channel is formed under the gate 20G, and the portion of the channel that is vertically projected between the conductive regions constitutes the actual effective channel.

Example 8

Referring to fig. 24, a TFT device 100H having a planar bottom gate structure includes a light-transmitting insulating substrate 40H formed with spacers 41H, and a gate electrode 20H, a gate dielectric layer 30H, and an active layer 10H sequentially provided on the spacers 41H. In this embodiment, the upper metal source electrode 501H and the metal drain electrode 502H are disposed on two sides of the active layer 10H, respectively, and the active layer 10H may be an amorphous IGZO metal oxide semiconductor layer, and ohmic contacts are formed between the source electrode 501H and the drain electrode 502H and the active layer 10H. The portions of the active layer under the source electrode 501H and the drain electrode 502H respectively form a source region and a drain region, and the channel region is located between the source region and the drain region.

Positive charge regions 60H respectively connecting the source electrode 501H and the drain electrode 502H are implanted by ions in a passivation layer overlying the device. The positive charge region 60H and the gate electrode 20H have an overlapping portion between the vertical projections of the channel region, and correspondingly, the positive charge region of the overlapping portion may form a two-dimensional electron gas 70H in the channel region connected to the source region and the drain region, respectively, where the two-dimensional electron gas 70H also constitutes a conductive region, and the carrier blocking region 80H is formed between the two-dimensional electron gas 70H connected to the source region and the drain region.

When the device is turned on, the gate 20H forms a channel over which the portion of the vertical projection that lies between the conductive regions 70H forms a virtually effective channel.

Example 9

Referring to fig. 25, the SOI device 100I is a vertical structure, and includes a substrate 60I, a spacer 50I and an active layer 10I sequentially provided on the substrate 60I, a gate insulating layer 30I provided on one side of the active layer 10I, and a gate electrode 20I. The source region 101I and the drain region 102I are located below and above the active layer 10I, respectively, in a direction away from the substrate 60I. The channel region 103I has an equivalent source region 1051I communicating with the source region 101I and an equivalent drain region 1052I communicating with the drain region 102I, and a carrier blocking region 106I is formed between the equivalent source region 1051I and the equivalent drain region 1052I.

When a bias is applied to the gate 20I of the device to turn the device on, the gate 20I controls the formation of a channel 104I connecting the source region 101I and the drain region 102I in the channel region 103I of the device, but only the portion of the channel 104I that does not overlap between the perpendicular projections of the equivalent source region 1051I and the equivalent drain region 1052I on the channel region 103I constitutes an effective channel 1041I for transmitting an operating current when the device is turned on, i.e., the remaining portion 1042I of the channel 104I is not for transmitting an operating current when the device is turned on.

In the foregoing embodiments/examples, the source region and the drain region in the device may be a common heavily doped semiconductor source/drain, or may be a schottky metal source/drain of a metal-semiconductor structure; the grid electrode can be a common metal-insulating layer-semiconductor MOS structure grid electrode or a Schottky junction grid electrode of a metal semiconductor structure; the active layer may be formed of a single semiconductor material or may include at least two semiconductor materials varying in a thickness direction or a plane extending direction thereof to form a composite channel.

And the equivalent source region and the equivalent drain region may be formed spontaneously or by gate control of corresponding structures.

In general, in the above-described embodiments, the vertical projection of the effective channel, the equivalent source region, and/or the equivalent drain region superimposed on the channel region communicates with the source region and the drain region, so as to ensure that carriers of the effective channel and the equivalent source region and/or the equivalent drain region can be injected unidirectionally or bidirectionally at least in the thickness direction, and construct a carrier path from the source region to the drain region. Of course, referring to fig. 26, the present application is not limited to the specific embodiments, and such embodiments are intended to be within the scope of the present application if the vertical projection of the effective channel, the equivalent source region, and the equivalent drain region superimposed on the channel region 103J does not allow the source region 101J and the drain region 102J of the device 100J to communicate, but rather has a "proper spacing" that does not completely shut off the passage of carriers from the equivalent source region 1051J to the effective channel 1041J and from the effective channel 1041J to the equivalent drain region 1052J, and the injection direction of carriers between the effective channel 1041J, the equivalent source region 1051J, and the equivalent drain region 1052J forms an angle with the thickness direction of the channel region 103J.

The following is the result of Sentaurus TCAD simulation verification of an SOI device to which the above-described embodiments/examples of the present application are applied.

Simulation example 1

In simulation example 1, an SOI device to which the above-described embodiments/examples of the present application are applied is referred to as an "SOI device of the present application". As a comparison, an SOI device having a similar structure to the SOI device of the present application was distinguished only in that an electric field adjusting portion was not provided in the SOI device as a comparison (referred to as a comparison SOI device in this simulation example), and the thickness of the active region of the comparison SOI device was equal to that of the SOI device of the present application.

Simulation parameters: the source and drain doping is of N type, the doping concentration is 1E21cm ^-3, the channel doping is of P type, the doping concentration is 1E17cm ^-3, the channel length Lg is 200nm, the thickness of the active layer is 50nm, the thickness of the gate insulating layer is 5nm, the thickness of the first part of the isolator is 100nm, and the width of the channel region is 200nm. The length of the electric field adjusting part is 60nm, the thickness is 25nm, and the width is 200nm.

Referring to fig. 27, taking 1Mrad (Si) as an example of the total dose of irradiation, pre_soi represents the characteristics before irradiation of the comparison SOI device, and post_soi represents the characteristics after irradiation of the comparison SOI device; pre_SOI_Barrier represents the Pre-irradiation characteristic of the SOI device of the present application, and post_SOI_Barrier represents the Post-irradiation characteristic of the SOI device of the present application. It can be seen that after irradiation, the performance of the comparison SOI device is seriously reduced and basically cannot work normally, but the off-state current of the comparison SOI device after irradiation is smaller than that of the comparison SOI device by approximately 4 orders of magnitude, and the offset of the threshold voltage is also smaller than that of the comparison SOI device.

Simulation example 2

In simulation example 2, an SOI device to which the above embodiments/examples of the present application are applied is referred to as an "SOI device of the present application". As a comparison, an SOI device having a similar structure to the SOI device of the present application was distinguished only in that an electric field adjusting portion was not provided in the SOI device as a comparison (referred to as a comparison SOI device in this simulation example), and the thickness of the active region of the comparison SOI device was equal to that of the SOI device of the present application.

Simulation parameters: the source and drain doping is of N type, the doping concentration is 1E21cm ^-3, the channel doping is of P type, the doping concentration is 1E17cm ^-3, the channel length Lg is 200nm, the thickness of the active layer is 50nm, the thickness of the gate insulating layer is 5nm, the thickness of the first part of the isolator is 100nm, and the width of the channel region is 200nm. The length of the electric field adjusting part is 60nm, the width is 200nm, and the thickness is 0 (namely, the comparison SOI device), 25nm and 40nm respectively.

Referring to fig. 28, taking an example that the total irradiation dose is 1Mrad (Si), the off-state current of the SOI device of the present application after irradiation is better than that of the comparative SOI device, and the smaller the off-state current is as the thickness of the electric field adjusting portion increases. The off-state current of the device is smaller than that of a comparison SOI device by 9 orders of magnitude when the thickness of the electric field regulating part is 40 nm. Moreover, compared with a comparative SOI device, the threshold voltage offset of the device after irradiation is not obvious under the condition that the electric field adjusting part has different thicknesses.

Simulation example 3

In simulation example 3, an SOI device to which the above-described embodiments/examples of the present application are applied is referred to as an "SOI device of the present application". As a comparison, an SOI device having a similar structure to the SOI device of the present application was distinguished only in that an electric field adjusting portion was not provided in the SOI device as a comparison (referred to as a comparison SOI device in this simulation example), and the thickness of the active region of the comparison SOI device was equal to that of the SOI device of the present application.

Simulation parameters: the source and drain doping is of N type, the doping concentration is 1E21cm ^-3, the channel doping is of P type, the doping concentration is 1E17cm ^-3, the channel length Lg is 200nm, the thickness of the active layer is 50nm, the thickness of the gate insulating layer is 5nm, the thickness of the first part of the isolator is 100nm, and the width of the channel region is 200nm. The thickness of the electric field adjusting part is 25nm, the width is 200nm, and the lengths are 0 (i.e. the comparison SOI device), 100nm and 180nm respectively.

Referring to fig. 29, taking an example that the total irradiation dose is 1Mrad (Si), the off-state current of the SOI device of the present application after irradiation is superior to that of the comparative SOI device, and the shift amount of the threshold voltage is minimized when the length of the electric field adjusting portion is 100 nm.

Simulation example 4

In simulation example 4, an SOI device to which the above-described embodiments/examples of the present application are applied is referred to as an "SOI device of the present application".

Simulation parameters: the source and drain doping is of N type, the doping concentration is 1E21cm ^-3, the channel doping is of P type, the doping concentration is 1E17cm ^-3, the channel length Lg is 200nm, the thickness of the active layer is 50nm, the thickness of the gate insulating layer is 5nm, the thickness of the first part of the isolator is 100nm, and the width of the channel region is 200nm. The electric field adjusting parts are respectively ① rectangular parallelepiped: a thickness of 25nm and a length of 100nm; ② trapezium: the bottom is 100nm long, the top is 30nm long, the height is 25nm, and the width is 200nm; ③ Inverted trapezoid: the bottom length is 30nm, the top length is 100nm, the height is 25nm, and the width is 200nm.

Referring to fig. 30, taking total irradiation dose of 1Mrad (Si) as an example, it can be seen that the threshold voltage shift of the inverted trapezoid is smaller than that of the rectangle (cuboid) and trapezoid, and the off-state current is minimum, which indicates that the characteristics after irradiation are the best when the electric field adjusting part is the inverted trapezoid in the SOI device of the present application.

Simulation example 5

In simulation example 5, an SOI device to which the above-described embodiments/examples of the present application are applied is referred to as an "SOI device of the present application". As a comparison, an SOI device having a similar structure to the SOI device of the present application was distinguished only in that an electric field adjusting portion was not provided in the SOI device as a comparison (referred to as a comparison SOI device in this simulation example), and the thickness of the active region of the comparison SOI device was not equal to that of the SOI device of the present application.

Simulation parameters: the source and drain doping is of N type, the doping concentration is 1E21cm ^-3, the channel doping is of P type, the doping concentration is 1E17cm ^-3, the channel length Lg is 200nm, the active layer thickness is 50nm (SOI device of the application) and 25nm (contrast SOI device) respectively, the thickness of the gate insulating layer is 5nm, the thickness of the first part of the isolator is 100nm, and the width of the channel region is 200nm. The thickness of the electric field adjusting part is 25nm, the length is 60nm, and the width is 200nm.

In simulation example 5, the thickness of the active layer in the SOI device of the present application was removed and the thickness of the electric field adjusting portion was then identical to that of the comparative SOI device. Referring to fig. 31, taking a total dose of 1Mrad (Si) as an example, it can be seen that the irradiated characteristics of the SOI device of the present application are still better than those of the comparative SOI device.

Simulation example 6

In simulation example 6, an SOI device to which the above-described embodiment/example of the present application is applied is referred to as an "SOI device of the present application". As a comparison, an SOI device having a similar structure to the SOI device of the present application was distinguished only in that an electric field adjusting portion was not provided in the SOI device as a comparison (referred to as a comparison SOI device in this simulation example).

Simulation parameters: the source and drain doping is of N type, the doping concentration is 1E21cm ^-3, the channel doping is of P type, the doping concentration is 1E17cm ^-3, the channel length Lg is 200nm, the thickness of the active layer is 50nm, the thickness of the gate insulating layer is 5nm, the thickness of the first part of the isolator is 100nm, and the width of the channel region is 200nm. The thickness of the electric field adjusting part is 25nm, the length is 60nm, and the width is 200nm.

As can be seen from fig. 32 to 35, taking an example of the total dose of irradiation of 1Mrad (Si), at the interface between the first portion of the spacer and the active layer and the interface between the second portion of the spacer and the active layer, the SOI device of the present application has at least a portion of the apparent attenuation of the field intensity normal to the interface at the position corresponding to the electric field adjusting portion along the length of the channel direction, and correspondingly, the concentration of trapped charges is also significantly reduced. Meanwhile, although the normal electric field intensity of the interface at the position corresponding to the electric field adjusting part is higher, compared with a comparative SOI device, the concentration of trap trapped charges is still an order of magnitude different, and the SOI device of the application keeps a better irradiation resistance level as a whole.

The radiation-resistant field effect transistor device provided by the embodiment mode/example of the application can be applied to a radiation-resistant environment.

The detailed description set forth above in connection with the appended drawings describes exemplary embodiments, but does not represent all embodiments that may be implemented or fall within the scope of the claims. The term "exemplary" used throughout this specification means "serving as an example, instance, or illustration," and does not mean "preferred" or "advantageous over other embodiments. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described embodiments.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A radiation-resistant field effect transistor device, comprising:

A substrate;

a spacer disposed on the substrate;

A gate structure cooperating with the active layer;

2. The radiation-resistant field effect transistor device of claim 1, wherein at least a portion of an interface normal electric field strength of the electric field adjusting portion and the active layer is less than a reference electric field strength, wherein the reference electric field strength is an interface normal electric field strength of the portion of the spacer other than the electric field adjusting portion and the active layer.

3. The radiation-resistant field effect transistor device of claim 1, wherein the electric field adjusting portion is one of SiO ₂、Si₃N₄、SiO_xN_y、HfO₂、Al₂O₃ or a combination thereof.

4. The radiation-resistant field effect transistor device of claim 1, wherein the electric field adjusting portion has a gradually smaller cross-sectional area, a gradually larger cross-sectional area, or a constant cross-sectional area in a direction away from the substrate.

5. The radiation-resistant field effect transistor device of claim 1, wherein the gate structure controls the channel region and forms a channel therein connecting the source region and the drain region, the electric field adjusting portion being spaced apart from the channel in a thickness direction.

6. The radiation-resistant field effect transistor device of claim 1, wherein the length ratio of the electric field adjusting portion to the channel region is 1:1 to 1:3, preferably 1:1 to 1:2.5, more preferably 1:2.

7. The radiation-resistant field effect transistor device of claim 1, wherein an effective channel and an equivalent source region and/or an equivalent drain region distant to the effective channel at least in a thickness direction of the channel region are formed in the channel region when the device is turned on, the field effect transistor device communicating the source region and the drain region through the effective channel and the equivalent source region and/or the equivalent drain region to contribute an operating current; preferably, the method comprises the steps of,

8. The radiation-resistant field effect transistor device of claim 7, wherein a conductive region is formed in the channel region that does not communicate with the source and drain regions; wherein,

9. The radiation-resistant field effect transistor device of claim 8, wherein the gate structure and the vertical projection of the conductive region onto the channel region overlap; wherein,

10. Use of a field effect transistor device in a radiation-proof environment, characterized in that the field effect transistor is a radiation-proof field effect transistor device according to any of claims 1 to 9.