CN114171579A - Shielding gate groove type field effect transistor of groove type source electrode and preparation method thereof - Google Patents
Shielding gate groove type field effect transistor of groove type source electrode and preparation method thereof Download PDFInfo
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Abstract
The application relates to a shielded gate trench field effect transistor of a trench source, comprising: the device comprises a substrate region, a drift region, a base region, an N-type source region, a shielding gate, a control gate, an insulating layer, a groove-shaped source electrode, a drain electrode and a metal gate; the drift region is connected with the substrate region, and the base region and the N-type source region are sequentially arranged above the drift region; the control grid and the shielding grid are sequentially arranged on the side of the drift region from top to bottom and are respectively connected with the drift region, the substrate region and the N-type source region through insulating layers; the groove-shaped source electrode comprises a horizontal source electrode part and a vertical source electrode part, and the vertical source electrode part is connected to one end of the horizontal source electrode part to form a source electrode with an L-shaped longitudinal section; the horizontal source part is arranged above the N-type source region, and the vertical source part is connected with the N-type source region and the side face of the substrate region, so that the corner of the N-type source region is attached to the corner of the groove-shaped source electrode; the drain electrode is arranged below the substrate region; the metal gate is disposed over the control gate. The scheme provided by the application can improve the avalanche capability of the device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a shielded gate trench type field effect transistor with a trench type source electrode and a preparation method thereof.
Background
Shielded gate trench field effect transistors SGT have been widely used in important low voltage areas such as power management. This is because the SGT has a high channel density and a good charge compensation effect. In addition, the shielding gate structure effectively isolates the coupling between the metal gate and the drain, thereby remarkably reducing the transmission capacitance. This enables the SGT to have lower specific on-resistance, less conduction and switching losses, and higher operating frequency.
In the related art, in order to suppress the floating effect of the substrate region, the substrate region needs to be shorted with the N-type source region connected to the channel through the heavily doped P-type source region. The P-type source region and the N-type source region in the traditional structure are both manufactured on the surface of a silicon wafer in a transistor, and the structure has two problems:
firstly, the structure consumes a certain silicon chip area, and in order to ensure that the P-type source region has enough area for short circuit, the area of the P-type source region is inevitably introduced; or in order to ensure the areas of the P-type source region and the N-type source region, the area of the required silicon wafer is larger, and the cost of the device is correspondingly increased; secondly, under the structure, when the transistor is in forward high-voltage blocking or forward high-voltage conduction, a hole is generated due to an avalanche effect, the hole can flow through the channel of the substrate area to form a hole current which is enough to turn on the parasitic triode, the triode is triggered to be turned on, and the avalanche capability of the device is limited.
Disclosure of Invention
In order to overcome the problems in the related art, the present application provides a trench source shielded gate trench field effect transistor, which can simplify the structure of a P-type source region and ensure the avalanche capability of the transistor.
The present application provides in a first aspect a shielded gate trench field effect transistor having a trench source, comprising:
the transistor comprises a substrate region 1, a drift region 2, a base region 3, an N-type source region 4, a shielding gate 5, a control gate 6, an insulating layer 7, a groove-shaped source electrode 8, a drain electrode 9 and a metal gate electrode 10;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction, and the base region 3 and the N-type source region 4 are sequentially arranged above the drift region 2; the control grid 6 and the shielding grid 5 are sequentially arranged on the side of the drift region 2 from top to bottom and are respectively connected with the drift region 2, the substrate region 3 and the N-type source region 4 through the insulating layer 7;
the groove-shaped source electrode 8 comprises a horizontal source electrode part and a vertical source electrode part, and the vertical source electrode part is connected to one end of the horizontal source electrode part to form a source electrode with an L-shaped longitudinal section; the horizontal source part is arranged above the N-type source region 4, and the vertical source part is connected with the side faces of the N-type source region 4 and the base region 3, so that the corner of the N-type source region 4 is attached to the corner of the groove-shaped source electrode 8;
the drain electrode 9 is arranged below the substrate region; the metal gate 10 is disposed over the control gate.
In one embodiment, the trench source shielded gate trench field effect transistor further comprises: an N-type compensation region 11;
the N-type compensation region 11 is arranged between the groove-type source electrode 8 and the drift region 2, the top surface of the N-type compensation region 11 is connected with the vertical source electrode part, the bottom surface of the N-type compensation region 11 is connected with the drift region, and one side surface of the N-type compensation region 11 is connected with the base region 3.
In one embodiment, the doping concentration of the N-type compensation region 11 is a medium doping concentration.
In one embodiment, the doping concentration of the N-type source region 4 is a heavy doping concentration.
In one embodiment, the lateral width of the N-type source region 4 is greater than or equal to 0.2 μm.
In one embodiment, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavily doped concentration;
the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is light doping concentration;
the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration;
the doping types of the shielding gate 5 and the control gate 6 are both P-type doping; the doping concentration of the shielding gate 5 and the control gate 6 is heavy doping concentration.
A second aspect of the present application provides a method for manufacturing a trench source shielded gate trench field effect transistor, which is used for manufacturing the trench source shielded gate trench field effect transistor as described in any one of the above embodiments, and includes:
preparing a substrate region with a semiconductor material;
epitaxially forming a drift region on the substrate region;
forming a base region on the drift region in an ion implantation or diffusion mode;
etching a groove on one side of the drift region;
depositing an oxide, polysilicon, an oxide and polysilicon in the groove in sequence to form a shielding gate, an insulating layer and a control gate;
forming an N-type source region on the base region by using an N-type doped semiconductor material;
etching part of the N-type source region and part of the base region to form a metal electrode groove;
manufacturing a metal source electrode above the N-type source region and in the metal electrode groove to form a groove-type source electrode;
forming a metal gate over the trench;
a drain is formed under the substrate region.
In one embodiment, the etching a portion of the N-type source region and a portion of the body region to form a metal electrode trench includes:
and depositing an N-type doped semiconductor material in the metal electrode groove to form an N-type compensation area.
In one embodiment, the N-type source region is formed on the base region by using an N-type doped semiconductor material, and the N-type doped semiconductor material is an N-type heavily doped semiconductor material.
In one embodiment, the oxide, the polysilicon, the oxide and the polysilicon are sequentially deposited in the trench to form the shield gate, the insulating layer and the control gate, and the polysilicon is heavily doped polysilicon.
The technical scheme provided by the application can comprise the following beneficial effects:
in the shielded gate trench type field effect transistor with the groove-type source electrode, a P-type source region in a traditional source electrode structure is removed, the groove-type source electrode with a horizontal source electrode part and a vertical source electrode part is combined with an N-type source region to form a groove-type Schottky source region structure, in the groove-type Schottky source region structure, the horizontal source electrode part is arranged above the N-type source region, and the vertical source electrode part is connected with the N-type source region and the side face of a base region, so that the corner of the N-type source region is attached to the corner of the groove-type source electrode, the source region is closer to a drift region, and avalanche current can be collected by the source region more quickly; because the original P-type source region is removed, the area of a silicon wafer can be reduced under the condition that the occupied area of the N-type source region is ensured to be constant by the shielded gate trench type field effect transistor of the trench-type source electrode, and therefore the device cost is saved; or under a certain silicon chip area, the channel density is as large as possible, so that the conductive capacity of the device is improved;
on the premise that the structure of the P-type source region is simplified, the groove-type source electrode and the base region form P-type Schottky contact, when the device is in an avalanche state, injected hole current can be injected into holes after reaching the starting voltage of the P-type Schottky junction, and avalanche hole current is collected by the groove-type source electrode in advance before reaching the base region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application, as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.
Fig. 1 is a schematic structural diagram of a shielded gate trench field effect transistor with a trench-type source according to an embodiment of the present application;
fig. 2 is another schematic structural diagram of a trench source shielded gate trench field effect transistor according to an embodiment of the present application;
fig. 3 is a schematic flow chart illustrating a method for manufacturing a trench source shielded gate trench field effect transistor according to an embodiment of the present application;
fig. 4 is another schematic flow chart of a method for manufacturing a trench source shielded gate trench field effect transistor according to an embodiment of the present application.
Detailed Description
Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Example one
The P-type source region and the N-type source region in the traditional structure are both manufactured on the surface of a silicon wafer in a transistor, and the structure has two problems:
firstly, the structure consumes a certain silicon chip area, and in order to ensure that the P-type source region has enough area for short circuit, the area of the N-type source region is inevitably sacrificed; or in order to ensure the areas of the P-type source region and the N-type source region, the area of the required silicon wafer is larger, and the cost of the device is correspondingly increased; in the structure, when the transistor is in forward high-voltage blocking or forward high-voltage conduction, a cavity is generated due to an avalanche effect, and the cavity can flow through the substrate area channel to form a cavity current which is enough to turn on the parasitic triode, so that the triode is triggered to be turned on.
In view of the foregoing problems, embodiments of the present application provide a shielded gate trench field effect transistor with a trench source, which can simplify a P-type source region without affecting avalanche capability of the transistor.
The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a shielded gate trench field effect transistor with a trench-type source according to an embodiment of the present application.
Referring to fig. 1, the shielded gate trench field effect transistor with a trench type source includes:
the transistor comprises a substrate region 1, a drift region 2, a base region 3, an N-type source region 4, a shielding gate 5, a control gate 6, an insulating layer 7, a groove-shaped source electrode 8, a drain electrode 9 and a metal gate electrode 10;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction, and the base region 3 and the N-type source region 4 are sequentially arranged above the drift region 2; the control grid 6 and the shielding grid 5 are sequentially arranged on the side of the drift region 2 from top to bottom and are respectively connected with the drift region 2, the substrate region 3 and the N-type source region 4 through the insulating layer 7;
the drain electrode 9 is arranged below the substrate region 1; the metal gate 10 is arranged above the control gate 6;
the groove-shaped source electrode 8 comprises a horizontal source electrode part and a vertical source electrode part, and the vertical source electrode part is connected to one end of the horizontal source electrode part to form a source electrode with an L-shaped longitudinal section; the horizontal source part is arranged above the N-type source region 4, and the vertical source part is connected with the side faces of the N-type source region 4 and the base region 3, so that the corner of the N-type source region 4 is attached to the corner of the groove-shaped source electrode 8;
in this application embodiment, it is vertical to use the direction in the directional substrate district 1 of drift region 2, vertical source portion connect in the one end of control gate is kept away from to horizontal source portion, makes the longitudinal section of cell type source 8 is the L type, and wherein, the medial surface laminating of vertical source portion meets with N type source region and base member district in the side of transistor, and the laminating of horizontal source portion is at the top surface in N type source region.
Compared with the traditional shielding gate groove type field effect transistor with the P type heavily doped source region, the embodiment of the application utilizes the groove type source electrode to replace the P type source region, releases a considerable part of silicon area, provides enough silicon area for the N type source region, and can save the material cost of the transistor.
And the vertical source part of the groove-shaped source electrode is utilized, and the groove-shaped source electrode is closer to the drift region, so that the avalanche current can be collected more quickly, the body diode of the transistor can conduct electricity through multi-sub current when being started, the reverse recovery time is shortened, and the quick switching capability of the transistor is improved.
In the embodiment of the present application, the doping concentration of the N-type source region 4 is a heavy doping concentration; the lateral width of the N-type source region 4 is greater than or equal to 0.2 μm.
Further, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is heavy doping concentration; the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is light doping concentration; the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration; the doping types of the shielding gate 5 and the control gate 6 are both P-type doping; the doping concentration of the shielding gate 5 and the control gate 6 is heavy doping concentration.
In practical application, the doping types of the shielding gate 5 and the control gate 6 may also be N-type doping.
Wherein the value range of the light doping concentration is 1 multiplied by 1015cm-3To 5X 1016cm-3(ii) a The value range of the medium doping concentration is 1 multiplied by 1017cm-3To 5X 1018cm-3(ii) a The value range of the heavy doping concentration is 1 multiplied by 1019cm-3To 5X 1020cm-3。
In the shielded gate trench field effect transistor with the groove-type source electrode provided by the embodiment of the application, a P-type source region in a traditional source electrode structure is removed, and the groove-type source electrode with a horizontal source electrode part and a vertical source electrode part is combined with an N-type source region to form a groove-type Schottky source region structure; because the original P-type source region is removed, the area of a silicon wafer can be reduced under the condition that the occupied area of the N-type source region is ensured to be constant by the shielded gate trench type field effect transistor of the trench-type source electrode, and therefore the device cost is saved; or under a certain silicon chip area, the channel density is as large as possible, so that the conductive capacity of the device is improved;
on the premise that the structure of the P-type source region is simplified, the groove-type source electrode and the base region form P-type Schottky contact, when the device is in an avalanche state, injected hole current can be injected into holes after reaching the starting voltage of the P-type Schottky junction, and avalanche hole current is collected by the groove-type source electrode in advance before reaching the base region.
Example two
Based on the shielded gate trench field effect transistor with a trench-type source shown in the first embodiment, the present application provides another structure of a shielded gate trench field effect transistor with a trench-type source, which can perform impurity compensation with a body region to improve avalanche capability of the transistor.
The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 2 is another schematic structural diagram of a trench source shielded gate trench field effect transistor according to an embodiment of the present application.
Referring to fig. 2, the trench source shielded gate trench field effect transistor includes:
the transistor comprises a substrate region 1, a drift region 2, a base region 3, an N-type source region 4, a shielding gate 5, a control gate 6, an insulating layer 7, a groove-shaped source electrode 8, a drain electrode 9, a metal gate electrode 10 and an N-type compensation region 11;
the N-type compensation region 11 is arranged between the groove-type source electrode 8 and the drift region 2, the top surface of the N-type compensation region 11 is connected with the vertical source electrode part, the bottom surface of the N-type compensation region 11 is connected with the drift region 2, and one side surface of the N-type compensation region 11 is connected with the base region 3;
further, the doping concentration of the N-type compensation region 11 is a medium doping concentration.
In the embodiment of the application, a trench is etched on the side of the N-type source region 4 and the side of the base region 3 through an etching process, then an N-type doped semiconductor material with doping concentration is injected to form the N-type compensation region 11, because the doping concentration of the N-type compensation region 11 is close to that of the base region 3 and the doping types of the N-type doped semiconductor material are opposite, the N-type compensation region 11 can compensate impurities for the base region 3, the groove-type source electrode 8 formed after metal deposition and the base region 3 form a P-type schottky contact, when the transistor is in an avalanche state, a hole can be injected only after the injected hole current reaches the starting voltage of a P-type schottky junction, which is equivalent to improving the threshold of the hole current flowing into the source electrode, so that the capability of the avalanche hole current flowing into the source electrode is inhibited, and the avalanche capability of the transistor is improved.
In practical applications, the doping concentrations of the N-type compensation region and the body region may be set to be the same, for example: 5X 1017cm-3。
It should be noted that the above description of the doping concentration of the N-type compensation region is only an example given in the embodiments of the present application, and does not constitute the only limitation to the present application.
The drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction, and the base region 3 and the N-type source region 4 are sequentially arranged above the drift region 2; the control grid 6 and the shielding grid 5 are sequentially arranged on the side of the drift region 2 from top to bottom and are respectively connected with the drift region 2, the substrate region 3 and the N-type source region 4 through the insulating layer 7;
the groove-shaped source electrode 8 comprises a horizontal source electrode part and a vertical source electrode part, and the vertical source electrode part is connected to one end of the horizontal source electrode part to form a source electrode with an L-shaped longitudinal section; the horizontal source part is arranged above the N-type source region 4, and the vertical source part is connected with the side faces of the N-type source region 4 and the base region 3, so that the corner of the N-type source region 4 is attached to the corner of the groove-shaped source electrode 8; the drain electrode 9 is arranged below the substrate region; the metal gate 10 is disposed over the control gate.
The embodiment of the application provides another shielded gate trench field effect transistor with a trench-type source electrode, wherein an N-type compensation region is arranged between the trench-type source electrode and a drift region, the N-type compensation region is connected with a substrate region, impurity compensation is carried out on the substrate region through the N-type compensation region, namely an N-type drift region with medium doping concentration is formed, the trench-type source electrode and the substrate region form a P-type Schottky contact, when the transistor is in an avalanche state, holes can be injected after injected hole current reaches the starting voltage of a P-type Schottky junction, therefore, the capability of the avalanche hole current flowing into the trench-type source electrode through the substrate region is inhibited, and the avalanche capability of the transistor is improved; on the other hand, when the transistor is in reverse conduction of the body diode, the P-type Schottky diode is in a reverse bias state, and the groove-type source electrode and the N-type drift region form a forward biased N-type Schottky junction, so that the conduction of the body diode is mainly performed by multi-photon conduction, the reverse recovery time of the transistor is reduced, and the switching speed of the transistor is improved.
EXAMPLE III
Corresponding to the shielded gate trench field effect transistor with a trench source described in the first embodiment, the present application also provides a method for manufacturing a shielded gate trench field effect transistor with a trench source and a corresponding embodiment.
Fig. 3 is a schematic flow chart illustrating a method for manufacturing a trench source shielded gate trench field effect transistor according to an embodiment of the present application.
Referring to fig. 3, the method for manufacturing the shielded gate trench field effect transistor with the trench-type source includes:
301. preparing a substrate region with a semiconductor material;
in the embodiment of the present application, the semiconductor material used is an N-type heavily doped semiconductor material.
302. Epitaxially forming a drift region on the substrate region;
in the embodiment of the present application, different epitaxy processes may be adopted according to actual requirements, including but not limited to: vapor Phase Epitaxy (VPE) or Chemical Vapor Deposition (CVD).
303. Forming a base region on the drift region in an ion implantation or diffusion mode;
the ion implantation process is a process of doping silicon materials, in the practical application process, a power device product is placed at one end of an ion implanter, and a doping ion source is arranged at the other end of the ion implanter. At one end of the doping ion source, doping body atoms are ionized to carry certain charges, the charges are added to the super high speed by an electric field, penetrate through the surface layer of a product, and the doping atoms are injected into a power device by utilizing the momentum of the atoms to form a doping area.
The diffusion process is a process of doping pure impurity atoms on the surface of the silicon material, and in the practical application process, diborane or phosphine is usually used as an ion source, and the pure impurity atoms are doped on the surface of the silicon material by adopting an intermittent diffusion or displacement diffusion mode.
It should be noted that, in the embodiment of the present application, the preparation method adopted for the substrate region is not strictly limited, and in an actual process, the different processes may be selected according to actual requirements to complete the preparation of the substrate region.
304. Etching a groove on one side of the drift region;
in the embodiment of the application, a trench is etched on one side of the drift region through a photoetching process, and the residual photoresist is removed through wet etching or dry etching.
305. Depositing an oxide, polysilicon, an oxide and polysilicon in the trench in sequence to form a shield gate, an insulating layer and a control gate;
in the embodiment of the application, the polysilicon is heavily doped polysilicon of N type or P type.
Preferably, in the practical application process, oxide, P-type middle doped polysilicon, oxide and P-type heavily doped polysilicon may be sequentially deposited in the trench to form the shield gate, the insulating layer and the control gate.
306. Forming an N-type source region on the substrate region by using an N-type doped semiconductor material;
in the embodiment of the present application, the N-type doped semiconductor material is a heavily N-type doped semiconductor material.
307. Etching part of the N-type source region and part of the base region to form a metal electrode groove;
in the embodiment of the present application, the etching process adopted is the same as that in step 304, and is not described herein again.
308. Manufacturing a metal source electrode above the N-type source region and in the metal electrode groove to form a groove-type source electrode;
specifically, the method comprises the following steps: and after the metal electrode groove is etched, metal deposition is carried out in the metal electrode groove to form a vertical source electrode part of the groove-type source electrode, and then a horizontal source electrode part is deposited on the top surface of the residual N-type source region which is not etched and removed by utilizing a metal deposition process to obtain the groove-type source electrode.
309. Forming a metal gate over the trench;
310. a drain is formed under the substrate region.
The embodiment of the application provides a preparation method of a shielded gate trench type field effect transistor of a trench source electrode, the shielded gate trench type field effect transistor of the trench source electrode prepared by the method has a trench source electrode structure, and a P-type source region in a traditional source electrode structure is replaced by the trench source electrode, so that the source region is closer to a drift region, and avalanche current can be collected by the source region more quickly; because the original P-type source region is removed, the area of a silicon wafer can be reduced under the condition that the occupied area of the N-type source region is ensured to be constant by the shielded gate trench type field effect transistor of the trench-type source electrode, and therefore the device cost is saved; or under a certain silicon chip area, the channel density is as large as possible, so that the conductive capacity of the device is improved;
on the premise that the structure of the P-type source region is simplified, the groove-type source electrode and the base region form P-type Schottky contact, when the device is in an avalanche state, injected hole current can be injected into holes after reaching the starting voltage of the P-type Schottky junction, and avalanche hole current is collected by the groove-type source electrode in advance before reaching the base region.
Example four
Corresponding to the shielded gate trench field effect transistor with a trench source described in the second embodiment, the present application also provides a method for manufacturing a shielded gate trench field effect transistor with a trench source and a corresponding embodiment.
Fig. 4 is another schematic flow chart of a method for manufacturing a trench source shielded gate trench field effect transistor according to an embodiment of the present application.
Referring to fig. 4, the method for manufacturing the shielded gate trench field effect transistor with the trench-type source includes:
401. preparing a substrate region with a semiconductor material;
in this embodiment of the application, the content of step 401 is the same as that of step 301 in the third embodiment, and is not described herein again.
402. Epitaxially forming a drift region on the substrate region;
in this embodiment of the application, the content of step 402 is the same as that of step 302 in the third embodiment, and is not described herein again.
403. Forming a base region on the drift region in an ion implantation or diffusion mode;
in this embodiment, the content of step 403 is the same as that of step 303 in the third embodiment, and details are not described here.
404. Etching a groove on one side of the drift region;
in this embodiment, the content of step 404 is the same as that of step 304 in the third embodiment, and is not described herein again.
405. Depositing an oxide, polysilicon, an oxide and polysilicon in the trench in sequence to form a shield gate, an insulating layer and a control gate;
in the embodiment of the present application, the content of step 405 is the same as that of step 305 in the third embodiment, and is not described herein again.
406. Forming an N-type source region on the substrate region by using an N-type doped semiconductor material;
in the embodiment of the present application, the content of step 406 is the same as that of step 306 in the third embodiment, and details are not described here.
407. Etching part of the N-type source region and part of the base region to form a metal electrode groove;
in the embodiment of the present application, the content of step 407 is consistent with that of step 307 in the third embodiment, and details are not described here.
408. Depositing an N-type doped semiconductor material in the metal electrode groove to form an N-type compensation area;
in the embodiment of the application, an N-type medium doped semiconductor material is deposited in the metal electrode trench to form an N-type compensation region, which is equivalent to adjusting the doping concentration of a region where a part of the drift region, which is connected with the source, is located, namely, a region close to the body region, to a medium doping concentration to form impurity compensation and suppress avalanche hole current.
409. Manufacturing a metal source electrode above the N-type source region and in the metal electrode groove to form a groove-type source electrode;
in the metal electrode groove, after metal deposition is carried out above the N-type compensation region to obtain a groove-type source electrode, the source electrode and the base region form a P-type Schottky contact, when the transistor is in an avalanche state, injected hole current can be injected into a hole only after the injected hole current reaches the starting voltage of a P-type Schottky junction, and therefore the capability of the avalanche hole current flowing into the groove-type source electrode through the base region is restrained; in addition, when the device is in reverse conduction of the body diode, because the P-type schottky diode is in a reverse bias state, and the drift region of doping concentration in the groove-shaped source electrode and the N-type below the groove-shaped source electrode, namely the N-type compensation region in the step 408, forms a forward biased N-type schottky junction, the conduction of the body diode is mainly performed by multi-photon conduction, the reverse recovery time of the transistor is reduced, and the switching speed of the transistor is improved.
410. Forming a metal gate over the trench;
411. a drain is formed under the substrate region.
The embodiment of the application provides another preparation method of a shielded gate trench type field effect transistor with a groove-shaped source electrode, wherein an N-type compensation region is arranged between the groove-shaped source electrode and a drift region of the shielded gate trench type field effect transistor with the groove-shaped source electrode, the N-type compensation region is connected with a substrate region, impurity compensation is carried out on the substrate region through the N-type compensation region, namely an N-type drift region with medium doping concentration is formed, the groove-shaped source electrode is in P-type Schottky contact with the substrate region, when the transistor is in an avalanche state, holes can be injected when hole current injected firstly reaches the starting voltage of a P-type Schottky junction, the capability of the avalanche hole current flowing into the groove-shaped source electrode through the substrate region is inhibited, and the avalanche capability of the transistor is improved; on the other hand, when the transistor is in reverse conduction of the body diode, the P-type Schottky diode is in a reverse bias state, and the groove-type source electrode and the N-type drift region form a forward biased N-type Schottky junction, so that the conduction of the body diode is mainly performed by multi-photon conduction, the reverse recovery time of the transistor is reduced, and the switching speed of the transistor is improved.
The aspects of the present application have been described in detail hereinabove with reference to the accompanying drawings. In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. Those skilled in the art should also appreciate that the acts and modules referred to in the specification are not necessarily required in the present application. In addition, it can be understood that the steps in the method of the embodiment of the present application may be sequentially adjusted, combined, and deleted according to actual needs, and the modules in the device of the embodiment of the present application may be combined, divided, and deleted according to actual needs.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. A shielded gate trench field effect transistor having a trench source, comprising:
the transistor comprises a substrate region (1), a drift region (2), a base region (3), an N-type source region (4), a shielding gate (5), a control gate (6), an insulating layer (7), a groove-shaped source electrode (8), a drain electrode (9) and a metal gate electrode (10);
the drift region (2) is connected with the substrate region (1), the direction of the substrate region (1) pointing to the drift region (2) is taken as the upper direction, and the base region (3) and the N-type source region (4) are sequentially arranged above the drift region (2); the control grid (6) and the shielding grid (5) are sequentially arranged on the side of the drift region (2) from top to bottom and are respectively connected with the drift region (2), the substrate region (3) and the N-type source region (4) through the insulating layer (7);
the groove-shaped source electrode (8) comprises a horizontal source electrode part and a vertical source electrode part, and the vertical source electrode part is connected to one end of the horizontal source electrode part to form a source electrode with an L-shaped longitudinal section; the horizontal source part is arranged above the N-type source region (4), and the vertical source part is connected with the N-type source region (4) and the side face of the base region (3) so that the corner of the N-type source region (4) is attached to the corner of the groove-shaped source electrode (8);
the drain (9) is arranged below the substrate region; the metal gate (10) is arranged above the control gate.
2. The trench source shielded gate trench field effect transistor as claimed in claim 1 further comprising: an N-type compensation region (11);
the N-type compensation region (11) is arranged between the groove-type source electrode (8) and the drift region (2), the top surface of the N-type compensation region (11) is connected with the vertical source electrode part, the bottom surface of the N-type compensation region (11) is connected with the drift region, and one side surface of the N-type compensation region (11) is connected with the base region (3).
3. The trench source shielded gate trench field effect transistor as claimed in claim 2,
the doping concentration of the N-type compensation region (11) is medium doping concentration.
4. The trench source shielded gate trench field effect transistor as claimed in claim 1,
the doping concentration of the N-type source region (4) is heavy doping concentration.
5. The trench source shielded gate trench field effect transistor as claimed in claim 1,
the lateral width of the N-type source region (4) is greater than or equal to 0.2 mu m.
6. The trench source shielded gate trench field effect transistor as claimed in claim 1,
the doping type of the substrate region (1) is N-type doping, and the doping concentration of the substrate region (1) is heavy doping concentration;
the doping type of the drift region (2) is N-type doping, and the doping concentration of the drift region (2) is light doping concentration;
the doping type of the substrate region (3) is P-type doping, and the doping concentration of the substrate region (3) is medium doping concentration;
the doping types of the shielding grid (5) and the control grid (6) are both P-type doping; the doping concentration of the shielding grid (5) and the control grid (6) is heavy doping concentration.
7. A method for preparing a shielded gate trench field effect transistor with a trench source, which is used for preparing the shielded gate trench field effect transistor with the trench source as claimed in any one of claims 1 to 6, and comprises the following steps:
preparing a substrate region with a semiconductor material;
epitaxially forming a drift region on the substrate region;
forming a base region on the drift region in an ion implantation or diffusion mode;
etching a groove on one side of the drift region;
depositing an oxide, polysilicon, an oxide and polysilicon in the groove in sequence to form a shielding gate, an insulating layer and a control gate;
forming an N-type source region on the base region by using an N-type doped semiconductor material;
etching part of the N-type source region and part of the base region to form a metal electrode groove;
manufacturing a metal source electrode above the N-type source region and in the metal electrode groove to form a groove-type source electrode;
forming a metal gate over the trench;
a drain is formed under the substrate region.
8. The method for manufacturing a trench source shielded gate trench field effect transistor as claimed in claim 7, wherein said etching a portion of said N-type source region and a portion of said body region to form a metal electrode trench comprises:
and depositing an N-type doped semiconductor material in the metal electrode groove to form an N-type compensation area.
9. The method for manufacturing a trench type source shielded gate trench field effect transistor as claimed in claim 7,
and an N-type doped semiconductor material is formed in the N-type source region on the substrate region, wherein the N-type doped semiconductor material is an N-type heavily doped semiconductor material.
10. The method for manufacturing a trench type source shielded gate trench field effect transistor as claimed in claim 7,
and depositing an oxide, polysilicon, an oxide and polysilicon in the groove in sequence to form a shielding gate, an insulating layer and a control gate, wherein the polysilicon is heavily doped polysilicon.
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