CN114171580A - Groove type power semiconductor device with surrounding type source region and preparation method thereof - Google Patents
Groove type power semiconductor device with surrounding type source region and preparation method thereof Download PDFInfo
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Abstract
The application relates to a trench type power semiconductor device with a surrounding type source region, which comprises: the transistor comprises a substrate region, a drift region, a base region, a source region, a shielding grid, a control grid, an insulating layer, a source electrode, a drain electrode and a metal grid; the drift region is connected with the substrate region, the direction of the substrate region pointing to the drift region is taken as the upper part, and the base region and the source region are sequentially arranged above the drift region; the control grid and the shielding grid are sequentially arranged on the side of the drift region from top to bottom and are respectively connected with the drift region, the substrate region and the source region through insulating layers; the source region comprises a P-type source region and an N-type source region; the P-type source region is arranged above the substrate region, the N-type source region is arranged at the joint of the side surface of the P-type source region and the insulating layer, and one side of the N-type source region is connected with the insulating layer, so that the N-type source region is semi-surrounded by the P-type source region; the source electrode is arranged above the source region; the drain electrode is arranged below the substrate region; the metal gate is disposed over the control gate. The scheme provided by the application can enlarge the interface of the avalanche current channel and improve the maximum avalanche tolerance.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a trench type power semiconductor device with a surrounding type source region and a preparation method thereof.
Background
Shielded gate trench field effect transistors SGT have been widely used in important low voltage areas such as power management. This is because the SGT has a high channel density and a good charge compensation effect. In addition, the shielding gate structure effectively isolates the coupling between the metal gate and the drain, thereby remarkably reducing the transmission capacitance. This enables the SGT to have lower specific on-resistance, less conduction and switching losses, and higher operating frequency.
In the related art, a source structure having a composite P-type source region and N-type source region is adopted in a transistor, wherein the P-type source region short-circuits a body region and a source of the transistor. The source region structure usually adopts an interdigital strip structure, namely a P-type source region and an N-type source region are arranged on a substrate region in parallel, and the P-type source region and the N-type source region are both divided into the connection area of the source region and the substrate region.
The source region structure leads to the limitation of the area of the source region for receiving avalanche current, and the maximum avalanche tolerance of the transistor is limited.
Disclosure of Invention
In order to overcome the problems in the related art, the application provides a trench type power semiconductor device with a surrounding type source region and a preparation method thereof, which can enlarge the interface of an avalanche current channel, reduce the avalanche current density and further improve the maximum avalanche tolerance.
A first aspect of the present application provides a trench power semiconductor device having a surrounding source region, comprising:
the transistor comprises a substrate region 1, a drift region 2, a base region 3, a source region 4, a shielding grid 5, a control grid 6, an insulating layer 7, a source electrode, a drain electrode 8 and a metal grid electrode;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region pointing to the drift region is taken as the upper direction, and the base region 3 and the source region 4 are sequentially arranged above the drift region 2; the control grid 6 and the shielding grid 5 are sequentially arranged on the side of the drift region 2 from top to bottom and are respectively connected with the drift region 2, the substrate region 3 and the source region 4 through the insulating layer 7;
the source region 4 comprises a P-type source region 41 and an N-type source region 42; the P-type source region 41 is arranged above the body region 3, the N-type source region 42 is arranged at the junction of the side surface of the P-type source region 41 and the insulating layer 7, and one side of the N-type source region 42 is connected with the insulating layer 7, so that the N-type source region 42 is half-surrounded by the P-type source region 41;
the source electrode is arranged above the source region 4; the drain electrode 8 is arranged below the substrate region 1; the metal gate is provided above the control gate 6.
In one embodiment, the drift region 2 has a first top surface 21, a second top surface 22 and a third top surface 23; wherein the first top surface 21, the second top surface 22 and the third top surface 23 are at increasing distances from the substrate region 1;
the first top surface 21 is connected with the bottom surface of the shielding grid 5 through the insulating layer 7; the second top surface 22 is connected with the bottom of the base region 3; the third top surface 23 is flush with the top surface of the source region 4, so that the body region 3 and the source region 4 are both disposed in the drift region 2 in a recess formed by the second top surface 22 and the third top surface 23.
In one embodiment, the width ratio and the length ratio of the P-type source region 41 and the N-type source region 42 are both 2: 1.
In one embodiment, the area ratio of the second top surface 22 to the third top surface 23 is 1: 1.
In one embodiment, the doping concentrations of the P-type source region 41 and the N-type source region 42 are both heavily doped.
In one embodiment, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavily doped concentration;
the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is light doping concentration;
the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration;
the doping types of the shielding gate 5 and the control gate 6 are both P-type doping; the doping concentration of the shielding gate 5 and the control gate 6 is heavy doping concentration.
A second aspect of the present application provides a method for manufacturing a trench power semiconductor device having a surrounding source region, the method being used for manufacturing a trench power semiconductor device having a surrounding source region as described in any one of the above embodiments, and comprising:
manufacturing a substrate region by using a semiconductor material;
epitaxially forming a drift region on the substrate region;
forming a base region on the drift region in an ion implantation or diffusion mode;
etching a groove on one side of the drift region;
depositing an oxide, polysilicon, an oxide and polysilicon in the groove in sequence to form an insulating layer, a shielding gate and a control gate;
locally doping the position, which is attached to the insulating layer, on the substrate region to form an N-type source region, and doping the periphery of the N-type source region to form a P-type source region, so that the N-type source region is semi-surrounded by the P-type source region;
manufacturing a source electrode above the P-type source region and the N-type source region;
forming a metal gate over the trench;
and manufacturing a drain electrode at the bottom of the substrate region.
In one embodiment, the forming a base region on the drift region by ion implantation or diffusion comprises:
locally doping on the first region of the drift region in an ion implantation or diffusion mode to form the base region; and forming a third top surface of the drift region on the second region of the drift region by doping the same semiconductor material as the drift region.
In one embodiment, after the epitaxially forming a drift region on the substrate region, the method includes:
etching the drift region to form a second top surface of the drift region;
the forming of the base region on the drift region by means of ion implantation or diffusion comprises:
and forming the base region on the second top surface by ion implantation or diffusion.
In one embodiment, the oxide, the polysilicon, the oxide and the polysilicon are sequentially deposited in the trench to form the insulating layer, the shielding gate and the control gate, and the polysilicon is heavily doped polysilicon.
The technical scheme provided by the application can comprise the following beneficial effects:
the application provides a trench type power semiconductor device with a surrounding source region, wherein a source region comprises a P-type source region and an N-type source region, and is different from the existing source region structure, namely the P-type source region and the N-type source region are arranged on a substrate region in parallel and are of an interdigital strip structure with the connecting area of the source region and the substrate region, in the application, the P-type source region and the N-type source region form the surrounding source region structure, the interface of an avalanche current channel is enlarged, namely, the avalanche current is dispersed to flow to the enlarged PN junction surface, so that when the device is blocked or conducted in the forward direction, the avalanche current density is reduced, the flow direction of the avalanche current when the power semiconductor device is blocked or conducted is effectively improved, the voltage drop flowing through the P-type source region is reduced under the condition that the total avalanche current is fixed, namely, the parallel resistance of PN junctions of the source region is reduced, the starting of a parasitic triode is restrained, the maximum avalanche tolerance is further improved, and the reliability of the power semiconductor device is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application, as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.
Fig. 1 is a schematic structural diagram of a trench power semiconductor device having a surrounding source region according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an interdigital strip structure shown in the embodiments of the present application;
fig. 3 is another schematic structural diagram of a trench power semiconductor device having a surrounding source region according to an embodiment of the present application;
fig. 4 is a schematic flow chart illustrating a method for manufacturing a trench type power semiconductor device having a surrounding source region according to an embodiment of the present application;
fig. 5 is another schematic flow chart of a method for manufacturing a trench type power semiconductor device having a surrounding source region according to an embodiment of the present application.
Detailed Description
Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Example one
In the related art, the source region structure usually adopts an interdigital strip structure, that is, the P-type source region and the N-type source region are arranged on the substrate region in parallel, and the P-type source region and the N-type source region are both divided into the connection area of the source region and the substrate region. The source region structure leads to the limitation of the area of the source region for receiving avalanche current, and the maximum avalanche tolerance of the transistor is limited.
In view of the above problems, embodiments of the present application provide a trench power semiconductor device having a surrounding source region, which can enlarge an interface of an avalanche current channel, reduce avalanche current density, and further improve maximum avalanche resistance.
The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a trench power semiconductor device having a surrounding source region according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of an interdigital strip structure shown in the embodiments of the present application.
Referring to fig. 1, the trench type power semiconductor device having a surrounding type source region includes:
the transistor comprises a substrate region 1, a drift region 2, a base region 3, a source region 4, a shielding grid 5, a control grid 6, an insulating layer 7, a source electrode, a drain electrode 8 and a metal grid electrode;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region pointing to the drift region is taken as the upper direction, and the base region 3 and the source region 4 are sequentially arranged above the drift region 2; the control grid 6 and the shielding grid 5 are sequentially arranged on the side of the drift region 2 from top to bottom and are respectively connected with the drift region 2, the substrate region 3 and the source region 4 through the insulating layer 7;
the source region 4 comprises a P-type source region 41 and an N-type source region 42; the P-type source region 41 is arranged above the body region 3, the N-type source region 42 is arranged at the junction of the side surface of the P-type source region 41 and the insulating layer 7, and one side of the N-type source region 42 is connected with the insulating layer 7, so that the N-type source region 42 is half-surrounded by the P-type source region 41;
referring to fig. 2, in the conventional source region structure, the P-type source region 41 and the N-type source region 42 are of an interdigital structure, that is, the P-type source region 41 and the N-type source region 42 are arranged in parallel on the body region 3, but in the embodiment of the present application, the P-type source region 41 is not of a long strip structure in the conventional source region structure, but is arranged in a rectangular structure having an inward recess facing the control gate 6, and the N-type source region 42 is arranged in the inward recess, so that one side of the N-type source region 42 is connected to the insulating layer 7, and the other side is connected to the P-type source region 41, thereby forming a source region structure in which the N-type source region 42 is half-surrounded by the P-type source region 41.
In the embodiment of the present application, preferably, the width ratio and the length ratio of the P-type source region 41 and the N-type source region 42 are both 2: 1; referring to fig. 1, the width ratio of the P-type source region 41 to the N-type source region 42 is 2:1, that is, a: b is 2: 1; the length ratio of the P-type source region 41 to the N-type source region 42 is 2:1, i.e., c: d is 2:1 in the figure.
It should be noted that the above description of the width ratio and the length ratio of the P-type source region 41 and the N-type source region 42 is only an example given in the embodiments of the present application, and is not intended to be the only limitation of the present application, and in the practical application process, the width ratio and the length ratio may be adjusted according to the practical situation.
The source electrode is arranged above the source region 4; the drain electrode 8 is arranged below the substrate region 1; the metal gate is provided above the control gate 6.
In the embodiment of the present application, the doping concentrations of the P-type source region 41 and the N-type source region 42 are both heavy doping concentrations;
the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is heavy doping concentration;
the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is light doping concentration;
the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration;
the doping types of the shielding gate 5 and the control gate 6 are both P-type doping; the doping concentration of the shielding gate 5 and the control gate 6 is heavy doping concentration.
It should be noted that, in an actual application process, the doping types of the shielding gate 5 and the control gate 6 may also be N-type doping.
In the embodiment of the present application, the value range of the lightly doped concentration is 1 × 1015cm-3To 5X 1016cm-3(ii) a The value range of the medium doping concentration is 1 multiplied by 1017cm-3To 5X 1018cm-3(ii) a The value range of the heavy doping concentration is 1 multiplied by 1019cm-3To 5X 1020cm-3。
The embodiment of the application provides a trench type power semiconductor device with a surrounding type source region, wherein the source region comprises a P-type source region and an N-type source region, and the trench type power semiconductor device is different from the existing source region structure, namely the P-type source region and the N-type source region are arranged on a substrate region in parallel and are respectively of an interdigital strip structure with the connecting area of the source region and the substrate region, in the application, the P-type source region semi-surrounds the N-type source region to form the surrounding type source region structure, the interface of an avalanche current channel is enlarged, namely avalanche current is dispersed to flow to the enlarged PN junction surface, so that when the device is blocked or conducted in the forward direction, the avalanche current density is reduced, the flow direction of the current when the power semiconductor device is blocked or conducted in avalanche is effectively improved, therefore, under the condition that the total current is fixed, the voltage drop flowing through the P-type source region is reduced, namely the parallel resistance of PN junctions of the source region is reduced, the starting of a parasitic triode is restrained, the maximum avalanche tolerance is further improved, and the reliability of the power semiconductor device is improved.
Example two
Based on the trench type power semiconductor device with the surrounding source region shown in the first embodiment, the present application provides another trench type power semiconductor device with the surrounding source region, in which a part of the body region is replaced by the drift region, so that a part of the avalanche current can also flow directly from the drift region to the P-type source region.
The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 3 is another schematic structural diagram of a trench power semiconductor device having a surrounding source region according to an embodiment of the present application.
Referring to fig. 3, the trench type power semiconductor device having a surrounding type source region includes:
the transistor comprises a substrate region 1, a drift region 2, a base region 3, a source region 4, a shielding grid 5, a control grid 6, an insulating layer 7, a source electrode, a drain electrode 8 and a metal grid electrode;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region pointing to the drift region is taken as the upper direction, and the base region 3 and the source region 4 are sequentially arranged above the drift region 2; the control grid 6 and the shielding grid 5 are sequentially arranged on the side of the drift region 2 from top to bottom and are respectively connected with the drift region 2, the substrate region 3 and the source region 4 through the insulating layer 7;
the source region 4 comprises a P-type source region 41 and an N-type source region 42; the P-type source region 41 is arranged above the body region 3, the N-type source region 42 is arranged at the junction of the side surface of the P-type source region 41 and the insulating layer 7, and one side of the N-type source region 42 is connected with the insulating layer 7, so that the N-type source region 42 is half-surrounded by the P-type source region 41;
the drift region 2 has a first top surface 21, a second top surface 22 and a third top surface 23; wherein the first top surface 21, the second top surface 22 and the third top surface 23 are at increasing distances from the substrate region 1;
the first top surface 21 is connected with the bottom surface of the shielding grid 5 through the insulating layer 7; the second top surface 22 is connected with the bottom of the base region 3; the third top surface 23 is flush with the top surface of the source region 4, so that the body region 3 and the source region 4 are both disposed in the drift region 2 in a recess formed by the second top surface 22 and the third top surface 23.
In the conventional trench power semiconductor device, the widths of the source region and the body region are the same as the width of the trench power semiconductor device, but in the embodiment of the present application, the widths of the source region 4 and the body region 3 are both smaller than the width of the trench power semiconductor device, that is, the source region 4 and the body region 3 only cover a part of the drift region 2, so that a part of the drift region 2 at the top of the trench power semiconductor device is directly connected with the P-type source region 41.
Preferably, the area ratio of the second top surface 22 to the third top surface 23 is 1:1, that is, in this scheme, the widths of the source region 4 and the body region 3 are half of the width of the trench type power semiconductor device.
It should be noted that the above description of the area ratio of the second top surface 22 to the third top surface 23 is only an example given in the embodiments of the present application, and does not constitute the only limitation to the present application.
The embodiment of the application provides a trench type power semiconductor device with a surrounding type source region, wherein a P type source region in a source region structure of the trench type power semiconductor device semi-surrounds an N type source region, avalanche current is dispersed to flow through the junction surface of the enlarged P type source region and the enlarged N type source region, the parallel resistance of a PN junction is reduced, and the avalanche tolerance is improved by inhibiting the opening of a parasitic transistor; the drift region is used for replacing part of the base region, total avalanche current is further directly flowed from the drift region to the P-type source region through shunting, and the parasitic triode is more difficult to start by reducing the conduction voltage drop of the PN junction, so that the maximum avalanche tolerance of the device is fundamentally improved.
EXAMPLE III
Corresponding to the structural embodiment of the trench type power semiconductor device, the application also provides a preparation method of the trench type power semiconductor device with the surrounding type source region and a corresponding embodiment.
Fig. 4 is a schematic flowchart of a method for manufacturing a trench power semiconductor device having a surrounding source region according to an embodiment of the present application.
Referring to fig. 4, the method for manufacturing the trench type power semiconductor device having the surrounding source region includes:
301. manufacturing a substrate region by using a semiconductor material;
in the embodiment of the present application, the substrate region is made of an N-type heavily doped semiconductor material, that is, the doping type of the substrate region is N-type doping, and the doping concentration of the substrate region is a heavily doped concentration.
302. Epitaxially forming a drift region on the substrate region;
in the embodiment of the present application, different epitaxy processes may be adopted according to actual requirements, including but not limited to: vapor Phase Epitaxy (VPE) or Chemical Vapor Deposition (CVD).
303. Forming a base region on the drift region in an ion implantation or diffusion mode;
the ion implantation process is a process of doping silicon materials, in the practical application process, a power device product is placed at one end of an ion implanter, and a doping ion source is arranged at the other end of the ion implanter. At one end of the doping ion source, doping body atoms are ionized to carry certain charges, the charges are added to the super high speed by an electric field, penetrate through the surface layer of a product, and the doping atoms are injected into a power device by utilizing the momentum of the atoms to form a doping area.
The diffusion process is a process of doping pure impurity atoms on the surface of the silicon material, and in the practical application process, diborane or phosphine is usually used as an ion source, and the pure impurity atoms are doped on the surface of the silicon material by adopting an intermittent diffusion or displacement diffusion mode.
It should be noted that, in the embodiment of the present application, the preparation method adopted for the substrate region is not strictly limited, and in an actual process, the different processes may be selected according to actual requirements to complete the preparation of the substrate region.
304. Etching a groove on one side of the drift region;
in the embodiment of the application, a trench is etched on one side of the drift region through a photoetching process, and the residual photoresist is removed through wet etching or dry etching.
305. Depositing an oxide, polysilicon, an oxide and polysilicon in the groove in sequence to form an insulating layer, a shielding gate and a control gate;
in the embodiment of the application, the polysilicon is P-type or N-type heavily doped polysilicon.
306. Locally doping the position, which is attached to the insulating layer, on the substrate region to form an N-type source region, and doping the periphery of the N-type source region to form a P-type source region, so that the N-type source region is semi-surrounded by the P-type source region;
in the embodiment of the application, an N-type source region and a P-type source region are respectively prepared on the base region by using an N-type heavily doped semiconductor material and a P-type heavily doped semiconductor material.
307. Manufacturing a source electrode above the P-type source region and the N-type source region;
308. forming a metal gate over the trench;
309. and manufacturing a drain electrode at the bottom of the substrate region.
The application provides a method for preparing a trench type power semiconductor device with a surrounding type source region, doping the position of the substrate region, which is jointed with the insulating layer, locally to form an N-type source region, doping the periphery of the N-type source region to form a P-type source region, so that the N-type source region is semi-surrounded by the P-type source region, thereby enlarging the interface of the avalanche current channel, i.e. the distributed avalanche current flows to the enlarged PN junction, so that when the device is in forward blocking or forward conducting, the avalanche current density is reduced, the flow direction of the avalanche current when the power semiconductor device is blocked or conducted is effectively improved, and therefore, the voltage drop flowing through the P-type source region is reduced under the condition that the total avalanche current is fixed, the parallel resistance of the PN junction of the source region is reduced, the parasitic triode is restrained from being started, the maximum avalanche tolerance is further improved, and the reliability of the power semiconductor device is improved.
Example four
Corresponding to the second embodiment, the application further provides a manufacturing method of the trench type power semiconductor device with the surrounding type source region and a corresponding embodiment.
Fig. 5 is another schematic flow chart of a method for manufacturing a trench type power semiconductor device having a surrounding source region according to an embodiment of the present application.
Referring to fig. 5, the method for manufacturing the trench type power semiconductor device having the surrounding source region includes:
401. manufacturing a substrate region by using a semiconductor material;
in this embodiment of the application, the content of step 401 is the same as that of step 301 in the third embodiment, and is not described herein again.
402. Epitaxially forming a drift region on the substrate region;
in this embodiment of the application, the content of step 402 is the same as that of step 302 in the third embodiment, and is not described herein again.
403. Locally doping on the first region of the drift region in an ion implantation or diffusion mode to form the base region;
in an embodiment of the present application, a width of the first region is smaller than a width of the drift region.
404. Doping the second region of the drift region with the same semiconductor material as the drift region to form a third top surface of the drift region;
in the embodiment of the present application, the long side of the second region is aligned with the long side of the first region, so that the first region and the second region jointly cover one wide side of the drift region, and preferably, the size ratio of the first region to the second region is 1: 1.
In the embodiment of the present application, steps 403 and 404 may be replaced by the following steps:
etching the drift region to form a second top surface of the drift region;
and forming the base region on the second top surface by ion implantation or diffusion.
405. Locally doping the position, which is attached to the insulating layer, on the substrate region to form an N-type source region, and doping the periphery of the N-type source region to form a P-type source region, so that the N-type source region is semi-surrounded by the P-type source region;
406. etching a groove on one side of the drift region;
in the embodiment of the present application, the content of step 406 is the same as that of step 304 in the third embodiment, and is not described herein again.
407. Depositing an oxide, polysilicon, an oxide and polysilicon in the groove in sequence to form an insulating layer, a shielding gate and a control gate;
in the embodiment of the present application, the content of step 407 is the same as that of step 305 in the third embodiment, and details are not described here.
408. Manufacturing a source electrode above the P-type source region and the N-type source region;
409. forming a metal gate over the trench;
410. and manufacturing a drain electrode at the bottom of the substrate region.
In the embodiment of the present application, the contents of steps 408 to 410 are the same as those of steps 307 to 309 in the third embodiment, and are not described herein again.
The application provides a preparation method of a trench type power semiconductor device with an enclosing type source region, wherein an N-type source region is formed by locally doping a position, which is attached with an insulating layer, on a substrate region, and a P-type source region is formed by doping the periphery of the N-type source region, so that the N-type source region is semi-enclosed by the P-type source region, the interface of an avalanche current channel is enlarged, the density of avalanche current is reduced when the device is forwardly blocked or forwardly conducted, the flow direction of the avalanche current when the power semiconductor device is blocked or conducted is improved, and the voltage drop flowing through the P-type source region is reduced under the condition that the total avalanche current is fixed, namely the parallel resistance of a PN junction of the source region is reduced, the starting of a parasitic triode is inhibited, and the maximum avalanche tolerance is improved;
in addition, the drift region is used for replacing part of the base region, the total avalanche current is further directly flowed from the drift region to the P-type source region through shunting, and the parasitic triode is more difficult to turn on by reducing the conduction voltage drop of the PN junction, so that the maximum avalanche tolerance of the device is fundamentally improved.
The aspects of the present application have been described in detail hereinabove with reference to the accompanying drawings. In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. Those skilled in the art should also appreciate that the acts and modules referred to in the specification are not necessarily required in the present application. In addition, it can be understood that the steps in the method of the embodiment of the present application may be sequentially adjusted, combined, and deleted according to actual needs, and the modules in the device of the embodiment of the present application may be combined, divided, and deleted according to actual needs.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. A trench power semiconductor device having a surrounding source region, comprising:
the transistor comprises a substrate region (1), a drift region (2), a base region (3), a source region (4), a shielding gate (5), a control gate (6), an insulating layer (7), a source electrode, a drain electrode (8) and a metal gate;
the drift region (2) is connected with the substrate region (1), the direction of the substrate region pointing to the drift region is taken as the upper direction, and the base region (3) and the source region (4) are sequentially arranged above the drift region (2); the control grid (6) and the shielding grid (5) are sequentially arranged on the side of the drift region (2) from top to bottom and are respectively connected with the drift region (2), the substrate region (3) and the source region (4) through the insulating layer (7);
the source region (4) comprises a P-type source region (41) and an N-type source region (42); the P-type source region (41) is arranged above the base region (3), the N-type source region (42) is arranged at the joint of the side face of the P-type source region (41) and the insulating layer (7), and one side of the N-type source region (42) is connected with the insulating layer (7), so that the N-type source region (42) is half surrounded by the P-type source region (41);
the source is arranged above the source region (4); the drain (8) is arranged below the substrate region (1); the metal gate is arranged above the control gate (6).
2. The trench power semiconductor device of claim 1 having a surrounding source region,
the drift region (2) has a first top surface (21), a second top surface (22) and a third top surface (23); wherein the first top surface (21), the second top surface (22) and the third top surface (23) are at increasing distances from the substrate region (1);
the first top surface (21) is connected with the bottom surface of the shielding grid (5) through the insulating layer (7); the second top surface (22) is connected with the bottom of the base area (3); the third top surface (23) is flush with the top surface of the source region (4), so that the base region (3) and the source region (4) are both arranged in the drift region (2) in a recess formed by the second top surface (22) and the third top surface (23).
3. The trench power semiconductor device of claim 1 having a surrounding source region,
the width ratio and the length ratio of the P-type source region (41) to the N-type source region (42) are both 2: 1.
4. The trench power semiconductor device of claim 2 having a surrounding source region,
the area ratio of the second top surface (22) to the third top surface (23) is 1: 1.
5. The trench power semiconductor device of claim 1 having a surrounding source region,
the doping concentration of the P-type source region (41) and the doping concentration of the N-type source region (42) are heavy doping concentration.
6. The trench power semiconductor device of claim 5 having a surrounding source region,
the doping type of the substrate region (1) is N-type doping, and the doping concentration of the substrate region (1) is heavy doping concentration;
the doping type of the drift region (2) is N-type doping, and the doping concentration of the drift region (2) is light doping concentration;
the doping type of the substrate region (3) is P-type doping, and the doping concentration of the substrate region (3) is medium doping concentration;
the doping types of the shielding grid (5) and the control grid (6) are both P-type doping; the doping concentration of the shielding grid (5) and the control grid (6) is heavy doping concentration.
7. A method of manufacturing a trench power semiconductor device having a surrounding source region, for manufacturing a trench power semiconductor device having a surrounding source region according to any of claims 1 to 6, comprising:
manufacturing a substrate region by using a semiconductor material;
epitaxially forming a drift region on the substrate region;
forming a base region on the drift region in an ion implantation or diffusion mode;
etching a groove on one side of the drift region;
depositing an oxide, polysilicon, an oxide and polysilicon in the groove in sequence to form an insulating layer, a shielding gate and a control gate;
locally doping the position, which is attached to the insulating layer, on the substrate region to form an N-type source region, and doping the periphery of the N-type source region to form a P-type source region, so that the N-type source region is semi-surrounded by the P-type source region;
manufacturing a source electrode above the P-type source region and the N-type source region;
forming a metal gate over the trench;
and manufacturing a drain electrode at the bottom of the substrate region.
8. The method of manufacturing a trench power semiconductor device having a surrounding source region according to claim 7,
the forming of the base region on the drift region by means of ion implantation or diffusion comprises:
locally doping on the first region of the drift region in an ion implantation or diffusion mode to form the base region; and forming a third top surface of the drift region on the second region of the drift region by doping the same semiconductor material as the drift region.
9. The method of manufacturing a trench power semiconductor device having a surrounding source region according to claim 7,
after the drift region is epitaxially formed on the substrate region, the method includes:
etching the drift region to form a second top surface of the drift region;
the forming of the base region on the drift region by means of ion implantation or diffusion comprises:
and forming the base region on the second top surface by ion implantation or diffusion.
10. The method of manufacturing a trench power semiconductor device having a surrounding source region according to claim 7,
and depositing an oxide, polysilicon, an oxide and polysilicon in the groove in sequence to form an insulating layer, a shielding gate and a control gate, wherein the polysilicon is heavily doped polysilicon.
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