CN114335181A - Shielded gate trench type field effect transistor, transistor module and preparation method thereof - Google Patents

Abstract

The present application relates to a shielded gate trench field effect transistor, comprising: the transistor comprises a substrate region, a drift region, a base region, a source region, a groove region, a drain electrode and a source electrode; the source region consists of a first N-type source region, a second N-type source region and a P-type source region; the P-type source region is arranged at one corner of the source region, which is far away from the groove region, and the first N-type source region and the second N-type source region are respectively arranged and connected on two adjacent side surfaces of the P-type source region; the trench region is arranged in a region surrounded by the side faces of the first N-type source region and the second N-type source region. The channel in the body region is formed along the side face of the connection of the trench region and the source region, so that the channel area is increased, and the channel resistance of the device is reduced. The improvement of the channel area can reduce the hole current density below the N-type source region, reduce the voltage drop of the emitter junction of the parasitic triode, inhibit the starting of the parasitic triode and improve the avalanche resistance of the transistor.

Description

Shielded gate trench type field effect transistor, transistor module and preparation method thereof

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a shielded gate trench field effect transistor, a transistor module, and a method for manufacturing the same.

Background

Shielded Gate Trench field effect transistors (SGTs) have been widely used in important low voltage fields such as power management. SGT has high channel density and simultaneously has better charge compensation effect. In addition, the shielding gate structure effectively isolates the coupling between the control gate and the drain, thereby remarkably reducing the transmission capacitance.

Therefore, the SGT has lower specific on resistance, smaller on loss and switching loss and higher operating frequency.

However, the avalanche tolerance in the conventional SGT device limits the maximum current of the device in inductive load applications, and since the body region is shorted to the N-type source region connected to the channel through the heavily doped P-type source region, when the transistor generates holes due to the avalanche effect, a hole current can be formed through the channel of the body region to drive the parasitic transistor to turn on. The hole current flows through the body region channel, causing the parasitic triode to turn on, which causes the transistor to avalanche fail.

Therefore, in order to suppress the turn-on of the parasitic triode in the SGT before the SGT is avalanche failed, it is necessary to design a novel shielded gate trench field effect transistor.

Disclosure of Invention

To overcome the problems in the related art, the present application provides a shielded gate trench field effect transistor, including:

the transistor comprises a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a drain electrode 6 and a source electrode;

the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction,

the base region 3 and the source region 4 are sequentially arranged above the drift region 2;

the groove region 5 is arranged on the side of the substrate region 3 and is respectively connected with the drift region 2, the substrate region 3 and the source region 4;

the source region 4 is composed of a first N-type source region 41, a second N-type source region 42 and a P-type source region 43;

on the cross section of the source region 4, the P-type source region 43 is disposed at a corner of the source region 4 away from the trench region 5, and two adjacent sides of the P-type source region 43 are respectively connected to the first N-type source region 41 and the second N-type source region 42;

the trench region 5 is arranged in a region surrounded by the side surfaces of the first N-type source region 41 and the second N-type source region 42;

the trench region 5 comprises a shielding gate 51, a control gate 52, an insulating layer 53 and a metal gate; the control gate 52 and the shielding gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the body region 3 and the source region 4 through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;

the source electrode is arranged above the source region 4; the drain electrode 6 is arranged below the substrate region 1; the metal gate is disposed over the control gate 52.

In one embodiment, the trench region 5 is provided with land regions 54:

the mesa region 54 is disposed at the side of the first N-type source region 41, the body region 3, and the drift region 2;

on the first N-type source region 41, the other side surface opposite to the side surface connected to the P-type source region 43 is connected to the land region 54 of the trench region 5.

In one embodiment, the doping concentrations of the P-type source region 43, the first N-type source region 41 and the second N-type source region 42 are all heavily doped concentrations.

In one embodiment, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavily doped concentration;

the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is light doping concentration;

the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration;

the doping concentration of the source region 4 is heavy doping concentration; the doping concentration of the control gate 52 is a heavy doping concentration.

A second aspect of the present application provides a method for manufacturing a shielded gate trench field effect transistor, for manufacturing the shielded gate trench field effect transistor according to any one of the first aspects of the present application, including:

preparing a substrate region with a semiconductor material;

epitaxially forming a drift region on the substrate region;

forming a base region on the drift region in an ion implantation or diffusion mode;

forming a source region on the base region by using a P-type doped semiconductor material and an N-type doped semiconductor material respectively; the source region comprises a first N-type source region, a second N-type source region and a P-type source region;

etching a groove on one side of the drift region, the base region and the source region;

depositing an oxide, polysilicon, an oxide and polysilicon in the groove in sequence to form a shielding gate, an insulating layer and a control gate;

forming a source electrode above the source region; forming a metal gate over the trench;

a drain is formed under the substrate region.

In one embodiment, the etching a trench in one side of the drift region, the body region and the source region includes:

etching the groove at a first depth on one side of the first N-type source region; and etching the groove at a second depth on one side of the second N-type source region.

In one embodiment, the forming a source region on the base region with a P-type doped semiconductor material and an N-type doped semiconductor material, respectively, includes:

the P-type source region is arranged at one corner of the source region far away from the groove, and the two adjacent side edges of the P-type source region are respectively connected with the first N-type source region and the second N-type source region.

The third aspect of the present application provides a shielded gate trench field effect transistor module, which is composed of the shielded gate trench field effect transistor of any one of the first aspect of the present application:

in the transistor module, transistors are arranged and combined in a 2 x 2 mode to form a transistor module; the P-type source regions of different transistors are arranged in the center of the top surface of the transistor module in a 2 x 2 mode.

The fourth aspect of the present application provides a method for manufacturing a shielded gate trench type field effect transistor module, for manufacturing the shielded gate trench type field effect transistor module of the third aspect of the present application, comprising:

arranging and combining the transistors in a 2 × 2 manner; the P-type source regions of different transistors are arranged in the center above the transistor module, and the P-type source regions are arranged in a 2 x 2 mode;

and packaging the arranged transistors to form a transistor module.

The technical scheme provided by the application can comprise the following beneficial effects:

the application provides a shielded gate trench field effect transistor, wherein a source region of the shielded gate trench field effect transistor consists of a first N-type source region, a second N-type source region and a P-type source region; the P-type source region is arranged at one corner of the source region, which is far away from the groove region, and a first N-type source region and a second N-type source region are respectively arranged and connected on two adjacent side surfaces of the P-type source region; a groove region is arranged in a region surrounded by the side faces of the first N-type source region and the second N-type source region; when the drift region is conducted in the forward direction, channels are formed in the corresponding body regions below the first N-type source region and the second N-type source region, and electrons reach the drift region through the channels. The trench region is surrounded by the first N-type source region and the second N-type source region, so that correspondingly, when the substrate is conducted in the forward direction, a trench in the substrate region is formed along the side face of the connection between the trench region and the source region, the area of the trench is increased, and the resistance of the trench of the device is reduced; meanwhile, under the same current condition, the increase of the channel area can reduce the hole current density below the N-type source region, thereby reducing the voltage drop of the emitter junction of the parasitic triode, effectively inhibiting the starting of the parasitic triode and improving the avalanche capability during forward blocking or forward conduction.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application, as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.

Fig. 1 is a schematic structural diagram of a shielded gate trench field effect transistor according to an embodiment of the present application;

fig. 2 is a schematic flow chart illustrating a method for manufacturing a shielded gate trench field effect transistor according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a shielded gate trench field effect transistor module according to a third embodiment;

fig. 4 is a schematic flow chart of a manufacturing method of the shielded gate trench field effect transistor module according to the fourth embodiment.

Detailed Description

Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Example one

When the traditional SGT is blocked at a forward high voltage or is conducted at a forward high voltage, the SGT easily generates hole current due to an avalanche effect, the hole current flows through a channel of a base region to cause a parasitic triode to be started, and the transistor is subjected to avalanche failure due to the starting of the parasitic triode.

In view of the above problem, embodiments of the present application provide a shielded gate trench field effect transistor, and the following describes technical solutions of embodiments of the present application in detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a shielded gate trench field effect transistor according to an embodiment of the present application.

Referring to fig. 1, comprising: the transistor comprises a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a drain electrode 6 and a source electrode;

the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction,

the base region 3 and the source region 4 are sequentially arranged above the drift region 2;

the groove region 5 is arranged on the side of the substrate region 3 and is respectively connected with the drift region 2, the substrate region 3 and the source region 4;

the source region 4 is composed of a first N-type source region 41, a second N-type source region 42 and a P-type source region 43;

on the cross section of the source region 4, the P-type source region 43 is disposed at a corner of the source region 4 away from the trench region 5, and two adjacent sides of the P-type source region 43 are respectively connected to the first N-type source region 41 and the second N-type source region 42;

the trench region 5 is arranged in a region surrounded by the side surfaces of the first N-type source region 41 and the second N-type source region 42;

the trench region 5 comprises a shielding gate 51, a control gate 52, an insulating layer 53 and a metal gate; the control gate 52 and the shielding gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the body region 3 and the source region 4 through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;

the source electrode is arranged above the source region 4; the drain electrode 6 is arranged below the substrate region 1; the metal gate is disposed over the control gate 52.

In the embodiment of the present application, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavy doping concentration; the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is light doping concentration; the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration; the doping concentration of the source region 4 is heavy doping concentration; the doping concentration of the control gate 52 is a heavy doping concentration.

In the embodiment of the present application, the value range of the light doping concentration is 1 × 10¹⁵cm^-3To 5X 10¹⁶cm^-3(ii) a The value range of the medium doping concentration is 1 multiplied by 10¹⁷cm^-3To 5X 10¹⁸cm^-3(ii) a The value range of the heavy doping concentration is 1 multiplied by 10¹⁹cm^-3To 5X 10²⁰cm^-3。

In the embodiment of the present application, the doping type of the P-type source region 43 is P-type doping, and the doping concentration of the P-type source region is medium doping concentration or heavy doping concentration.

Further, the doping concentration of the doping type of the shielding gate 51 may be a heavily doped concentration or a medium doped concentration.

Preferably, the P-type source region 43, the first N-type source region 41 and the second N-type source region 42 are all set to the same doping concentration. For example, the P-type source regions 43 are all of medium doping concentration or are all of heavy doping concentration, so that the P-type source regions 43 can more easily receive hole current, and a better shunting effect is achieved.

In the shielded gate trench field effect transistor according to the embodiment of the present application, the source region 4 is composed of a first N-type source region 41, a second N-type source region 42, and a P-type source region 43; the P-type source region 43 is disposed at a corner of the source region 4 away from the trench region 5, and the first N-type source region 41 and the second N-type source region 42 are disposed and connected to two adjacent side surfaces of the P-type source region 43, respectively; the trench region 5 is arranged in a region surrounded by the side surfaces of the first N-type source region 41 and the second N-type source region 42; when conducting in the forward direction, channels are formed in the body region 3 corresponding to the lower portions of the first N-type source region 41 and the second N-type source region 42, and electrons reach the drift region 2 through the channels. Since the trench region 5 is surrounded by the first N-type source region 41 and the second N-type source region 42, accordingly, when conducting in the forward direction, a channel in the body region 3 is formed along the side of the connection of the trench region 5 and the source region 4, increasing the channel area, thereby reducing the channel resistance of the device; meanwhile, under the same current condition, the increase of the channel area can reduce the hole current density below the N-type source region, thereby reducing the voltage drop of the emitter junction of the parasitic triode, effectively inhibiting the starting of the parasitic triode and improving the avalanche capability during forward blocking or forward conduction.

Example two

According to the first embodiment, when the transistor is in forward conduction, the control gate applies a forward voltage to attract electrons in the body region to drift towards the control gate and form a P-type channel, and the transistor is conducted. Therefore, increasing the contact area between the control gate and the body region can effectively increase the channel area.

Since the increase of the channel area can reduce the channel resistance of the transistor, the embodiment of the present application further provides a shielded gate trench field effect transistor, which can further increase the channel area of the transistor, as shown in fig. 1, including:

the transistor comprises a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a drain electrode 6 and a source electrode;

the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction,

the base region 3 and the source region 4 are sequentially arranged above the drift region 2;

the groove region 5 is arranged on the side of the substrate region 3 and is respectively connected with the drift region 2, the substrate region 3 and the source region 4;

the source region 4 is composed of a first N-type source region 41, a second N-type source region 42 and a P-type source region 43;

on the cross section of the source region 4, the P-type source region 43 is disposed at a corner of the source region 4 away from the trench region 5, and two adjacent sides of the P-type source region 43 are respectively connected to the first N-type source region 41 and the second N-type source region 42;

the trench region 5 is arranged in a region surrounded by the side surfaces of the first N-type source region 41 and the second N-type source region 42;

the trench region 5 comprises a shielding gate 51, a control gate 52, an insulating layer 53 and a metal gate; the control gate 52 and the shielding gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the body region 3 and the source region 4 through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;

the source electrode is arranged above the source region 4; the drain electrode 6 is arranged below the substrate region 1; the metal gate is disposed over the control gate 52.

In the embodiment of the present application, the groove region 5 is provided with a boss region 54:

the mesa region 54 is disposed at the side of the first N-type source region 41, the body region 3, and the drift region 2; on the first N-type source region 41, the other side surface opposite to the side surface connected to the P-type source region 43 is connected to the land region 54 of the trench region 5.

As shown in fig. 1, in the length direction of the first N-type source region 41, one end is connected to the P-type source region, and the other end is connected to the mesa region of the trench region. Correspondingly, on the cross section of the transistor, the side surface of the base body region is also connected with the boss region of the groove region, when the transistor is conducted in the forward direction, a P-type channel is formed in the base body region below the first N-type source region and the second N-type source region, and electrons drift to the base body region adjacent to the boss region of the groove region, so that the area of the P-type channel is increased, and the channel resistance of the device is reduced; meanwhile, under the same current condition, the increase of the channel area can reduce the hole current density below the N-type source region, thereby reducing the voltage drop of the emitter junction of the parasitic triode, effectively inhibiting the starting of the parasitic triode and improving the avalanche capability of the transistor during forward blocking or forward conduction.

EXAMPLE III

Corresponding to the shielded gate trench field effect transistor and the embodiment thereof, the application also provides a preparation method of the shielded gate trench field effect transistor and the corresponding embodiment.

Fig. 2 is a schematic flow chart illustrating a method for manufacturing a shielded gate trench field effect transistor according to an embodiment of the present application.

Referring to fig. 2, the method for manufacturing the shielded gate trench field effect transistor, as shown in fig. 2, includes:

201. preparing a substrate region with a semiconductor material;

202. epitaxially forming a drift region on the substrate region;

in the embodiment of the present application, different epitaxy processes may be adopted according to actual requirements, including but not limited to: vapor Phase Epitaxy (VPE) or Chemical Vapor Deposition (CVD).

203. Forming a base region on the drift region in an ion implantation or diffusion mode;

the ion implantation process is a process of doping silicon materials, in the practical application process, a power device product is placed at one end of an ion implanter, and a doping ion source is arranged at the other end of the ion implanter. At one end of the doping ion source, doping body atoms are ionized to carry certain charges, the charges are added to the super high speed by an electric field, penetrate through the surface layer of a product, and the doping atoms are injected into a power device by utilizing the momentum of the atoms to form a doping area.

The diffusion process is a process of doping pure impurity atoms on the surface of the silicon material, and in the practical application process, diborane or phosphine is usually used as an ion source, and the pure impurity atoms are doped on the surface of the silicon material by adopting an intermittent diffusion or displacement diffusion mode.

It should be noted that, in the embodiment of the present application, the preparation method adopted for the substrate region is not strictly limited, and in an actual process, the different processes may be selected according to actual requirements to complete the preparation of the substrate region.

204. Forming a source region on the base region by using a P-type doped semiconductor material and an N-type doped semiconductor material respectively;

further, the source region comprises a first N-type source region, a second N-type source region and a P-type source region;

in the embodiment of the present application, the P-type source region and the N-type source region are connected. And doping the P-type doped semiconductor material and the N-type doped semiconductor material above the base region to form an N-type source region, a second N-type source region and a P-type source region. The base region and the N-type source region connected with the groove region are in short circuit through the P-type source region, so that the substrate floating effect of the power semiconductor device is inhibited, and the stability of the performance of the device is ensured.

Above the body region, as shown in fig. 1, the P-type source region is disposed at one corner of the source region away from the trench, and two adjacent sides of the P-type source region are respectively connected to the first N-type source region and the second N-type source region.

In the embodiment of the present application, preferably, the doping concentrations of the P-type doped semiconductor material and the N-type doped semiconductor material are both heavily doped to form an ohmic contact, so as to ensure that no significant additional impedance is generated in the device.

205. Etching a groove on one side of the drift region, the base region and the source region;

further, etching the groove at a first depth on one side of the first N-type source region; etching the groove at a second depth on one side of the second N-type source region;

further, the direction of the first depth and the direction of the second depth are etching directions.

Specifically, the first depth is smaller than the second depth.

In this embodiment, trenches are etched at a first depth on one side of the first N-type source region, the drift region, and the body region to form a mesa region of the trench region. The boss region is arranged on the side faces of the first N-type source region, the base region and the drift region; and on the first N-type source region, the other side surface opposite to the side surface connected with the P-type source region is connected with the boss region of the groove.

In the embodiment of the application, in the length direction of the first N-type source region, one end is connected with the first N-type source region, and the other end is connected with the boss region of the groove. Correspondingly, on the cross section of the transistor, the side face of the base region is also connected with the boss region of the groove, when the transistor is in forward conduction, a P-type channel is formed in the base region below the first N-type source region and the second N-type source region, and electrons drift to the base region adjacent to the boss region of the groove, so that the area of the P-type channel is increased.

206. Depositing a P-type doped semiconductor material, polysilicon, an oxide and polysilicon in the trench in sequence to form a shield gate, an insulating layer and a control gate;

preferably, in this embodiment of the present application, an oxide, a polysilicon, and an oxide and a heavily doped polysilicon are sequentially deposited in the trench to form the shield gate, the insulating layer, and the control gate.

207. Forming a source electrode above the source region;

208. forming a metal gate over the trench;

209. a drain is formed under the substrate region.

When the substrate is conducted in the forward direction, channels are formed in the substrate regions corresponding to the lower portions of the first N-type source region and the second N-type source region, and electrons reach the drift region through the channels. The trench region is surrounded by the first N-type source region and the second N-type source region, accordingly, when the semiconductor device is conducted in the forward direction, a channel in the base region is formed along the side face of the connection between the trench region and the source region, the channel area is increased, and therefore the channel resistance of the semiconductor device is reduced; meanwhile, under the same current condition, the increase of the channel area can reduce the hole current density below the N-type source region, thereby reducing the voltage drop of the emitter junction of the parasitic triode, effectively inhibiting the starting of the parasitic triode and improving the avalanche capability during forward blocking or forward conduction.

Example four

Based on the shielded gate trench field effect transistor described in the first embodiment or the second embodiment of the present application, the transistor is better protected when a hole current occurs. The embodiment of the present application further provides a shielded gate trench type field effect transistor module, as shown in fig. 3, including: the transistor described in embodiment one or embodiment two;

in the transistor module, transistors are arranged and combined in a 2 × 2 manner to form a transistor module.

Further, the P-type source regions of different transistors are arranged in a 2 × 2 manner at the center of the top surface of the transistor module.

In the transistor module, when a hole current occurs, the hole current is generated in the drift region and flows to the source region along an interface of the trench region and the body region. Because the P-type source region is arranged in the center of the cross section of the transistor module and is formed by splicing the P-type source regions of the four transistors, the P-type source region can better receive hole current, and the avalanche tolerance of the shielded gate trench type field effect transistor is improved.

EXAMPLE five

Corresponding to the shielded gate trench type field effect transistor module and the embodiment thereof, the application also provides a preparation method of the shielded gate trench type field effect transistor module and a corresponding embodiment.

Fig. 4 is a schematic flow chart of a method for manufacturing a shielded gate trench field effect transistor module according to an embodiment of the present application.

Referring to fig. 4, the method comprises the following steps:

401. arranging and combining the transistors in a 2 × 2 manner;

further, the P-type source regions of different transistors are arranged in a 2 × 2 manner at the center of the top surface of the transistor module.

402. And packaging the arranged transistors to form a transistor module.

In the embodiment of the present application, the transistor module is manufactured by assembling and combining the transistors described in the first embodiment or the second embodiment. The transistor module has larger area of the P-type source region, so that the P-type source region can better receive hole current, and the avalanche tolerance of the shielded gate trench field effect transistor is improved.

With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.

The aspects of the present application have been described in detail hereinabove with reference to the accompanying drawings. In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. Those skilled in the art should also appreciate that the acts and modules referred to in the specification are not necessarily required in the present application. In addition, it can be understood that the steps in the method of the embodiment of the present application may be sequentially adjusted, combined, and deleted according to actual needs, and the modules in the device of the embodiment of the present application may be combined, divided, and deleted according to actual needs.

Furthermore, the method according to the present application may also be implemented as a computer program or computer program product comprising computer program code instructions for performing some or all of the steps of the above-described method of the present application.

Alternatively, the present application may also be embodied as a non-transitory machine-readable or computer-readable storage medium or machine-readable storage medium having stored thereon executable code or a computer program, or computer instruction code, which, when executed by a processor of an electronic device or electronic device, server, or the like, causes the processor to perform some or all of the various steps of the above-described methods in accordance with the present application.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the applications disclosed herein may be implemented as electronic hardware, computer software, or combinations of both.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (9)

1. A shielded gate trench field effect transistor comprising:

the transistor comprises a substrate region (1), a drift region (2), a base region (3), a source region (4), a trench region (5), a drain electrode (6) and a source electrode;

the drift region (2) is connected with the substrate region (1), the direction of the substrate region (1) pointing to the drift region (2) is taken as the upper direction, and the base region (3) and the source region (4) are sequentially arranged above the drift region (2);

the groove region (5) is arranged on the side of the substrate region (3) and is respectively connected with the drift region (2), the substrate region (3) and the source region (4);

the source region (4) is composed of a first N-type source region (41), a second N-type source region (42) and a P-type source region (43);

on the cross section of the source region (4), the P-type source region (43) is arranged at one corner of the source region (4) far away from the trench region (5), and two adjacent side edges of the P-type source region (43) are respectively connected with the first N-type source region (41) and the second N-type source region (42);

the trench region (5) is arranged in a region surrounded by the side faces of the first N-type source region (41) and the second N-type source region (42);

the trench region (5) comprises a shielding gate (51), a control gate (52), an insulating layer (53) and a metal gate; the control grid (52) and the shielding grid (51) are sequentially arranged in the trench region (5) from top to bottom and are separated by the insulating layer (53); the control grid (52) is respectively connected with the base region (3) and the source region (4) through the insulating layer (53), and the shielding grid (51) is connected with the drift region (2) through the insulating layer (53);

the source is arranged above the source region (4); the drain (6) is arranged below the substrate region (1); the metal gate is disposed over the control gate (52).

2. The shielded gate trench field effect transistor according to claim 1, wherein the trench region (5) is provided with a mesa region (54):

the boss region (54) is arranged on the side faces of the first N-type source region (41), the base region (3) and the drift region (2);

and the other side surface opposite to the side surface connected with the P-type source region (43) on the first N-type source region (41) is connected with a boss region (54) of the groove region (5).

3. The shielded gate trench field effect transistor of claim 1, wherein the doping concentrations of the P-type source region (43), the first N-type source region (41) and the second N-type source region (42) are all heavily doped.

4. The shielded gate trench field effect transistor according to claim 1, wherein the doping type of the substrate region (1) is N-type doping and the doping concentration of the substrate region (1) is a heavily doped concentration;

the doping type of the drift region (2) is N-type doping, and the doping concentration of the drift region (2) is light doping concentration;

the doping type of the substrate region (3) is P-type doping, and the doping concentration of the substrate region (3) is medium doping concentration;

the doping concentration of the source region (4) is heavy doping concentration; the doping concentration of the control gate (52) is a heavy doping concentration.

5. A method of manufacturing a shielded gate trench field effect transistor, for use in manufacturing a shielded gate trench field effect transistor according to any one of claims 1 to 4, comprising:

preparing a substrate region with a semiconductor material;

epitaxially forming a drift region on the substrate region;

forming a base region on the drift region in an ion implantation or diffusion mode;

forming a source region on the base region by using a P-type doped semiconductor material and an N-type doped semiconductor material respectively; the source region comprises a first N-type source region, a second N-type source region and a P-type source region;

etching a groove on one side of the drift region, the base region and the source region;

depositing an oxide, polysilicon, an oxide and polysilicon in the groove in sequence to form a shielding gate, an insulating layer and a control gate;

forming a source electrode above the source region; forming a metal gate over the trench;

a drain is formed under the substrate region.

6. The method of claim 5, wherein etching a trench in one side of the drift region, the body region and the source region comprises:

etching the groove at a first depth on one side of the first N-type source region;

and etching the groove at a second depth on one side of the second N-type source region.

7. The method of claim 5, wherein forming a source region of P-type and N-type doped semiconductor material on the body region comprises:

the P-type source region is arranged at one corner of the source region far away from the groove, and the two adjacent side edges of the P-type source region are respectively connected with the first N-type source region and the second N-type source region.

8. A shielded gate trench field effect transistor module comprising the shielded gate trench field effect transistor of any of claims 1-4:

in the transistor module, transistors are arranged and combined in a 2 x 2 mode to form a transistor module; the P-type source regions of different transistors are arranged in the center of the top surface of the transistor module in a 2 × 2 manner.

9. A method for manufacturing a shielded gate trench field effect transistor module according to claim 8, comprising:

arranging and combining the transistors in a 2 × 2 manner; the P-type source regions of different transistors are arranged in the center above the transistor module, and the P-type source regions are arranged in a 2 x 2 mode;

and packaging the arranged transistors to form a transistor module.

Images