CN114141861A - Shielded gate trench field effect transistor and method of making the same - Google Patents

Shielded gate trench field effect transistor and method of making the same Download PDF

Info

Publication number
CN114141861A
CN114141861A CN202111449785.7A CN202111449785A CN114141861A CN 114141861 A CN114141861 A CN 114141861A CN 202111449785 A CN202111449785 A CN 202111449785A CN 114141861 A CN114141861 A CN 114141861A
Authority
CN
China
Prior art keywords
region
type
source region
substrate
drift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111449785.7A
Other languages
Chinese (zh)
Inventor
张子敏
王宇澄
虞国新
吴飞
钟军满
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Xianpupil Semiconductor Technology Co ltd
Original Assignee
Wuxi Xianpupil Semiconductor Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Xianpupil Semiconductor Technology Co ltd filed Critical Wuxi Xianpupil Semiconductor Technology Co ltd
Priority to CN202111449785.7A priority Critical patent/CN114141861A/en
Publication of CN114141861A publication Critical patent/CN114141861A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

The present application relates to a shielded gate trench field effect transistor, comprising: the transistor comprises a substrate region, a drift region, a base region, a source region, a groove region, a drain electrode and a source electrode; the drift region is connected with the substrate region, the direction of the substrate region pointing to the drift region is taken as the upper direction, and the base region and the source region are sequentially arranged above the drift region; the groove region is arranged on the side of the substrate region and is respectively connected with the drift region, the substrate region and the source region; the groove region comprises a shielding grid, a control grid, an insulating layer and a metal grid; the source region consists of a P-type source region and an N-type source region, and the P-type source region and the N-type source region are arranged in parallel and are respectively connected with the groove region; the shielding grid is connected with the drift region. When avalanche breakdown occurs, the hole current can be directly injected into the P-type source region along the side edge of the groove region, the moving path of the hole current is shortened, the starting of a parasitic triode is restrained, and the avalanche tolerance is improved.

Description

Shielded gate trench field effect transistor and method of making the same
Technical Field
The application relates to the technical field of semiconductors, in particular to a shielded gate trench type field effect transistor and a preparation method thereof.
Background
Shielded Gate Trench field effect transistors (SGTs) have been widely used in important low voltage fields such as power management. SGT has high channel density and simultaneously has better charge compensation effect. In addition, the shielding gate structure effectively isolates the coupling between the control gate and the drain, thereby remarkably reducing the transmission capacitance.
Therefore, the SGT has lower specific on resistance, smaller on loss and switching loss and higher operating frequency.
However, when the conventional SGT is blocked in the forward high voltage or turned on in the forward high voltage, the SGT is prone to generate a hole current due to an avalanche effect, the hole current flows through the body region channel, which causes a parasitic transistor to turn on, and the switching on of the parasitic transistor causes the transistor to have an avalanche failure.
Therefore, in order to suppress the turn-on of the parasitic triode in the SGT before the SGT is avalanche failed, it is necessary to design a novel shielded gate trench field effect transistor.
Disclosure of Invention
To overcome the problems in the related art, the present application provides a shielded gate trench field effect transistor, comprising:
the transistor comprises a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a source electrode 7 and a drain electrode 6;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction,
the base region 3 and the source region 4 are sequentially arranged above the drift region 2;
the groove region 5 is arranged on the side of the substrate region 3 and is respectively connected with the drift region 2, the substrate region 3 and the source region 4;
the source region 4 consists of a P-type source region 41 and an N-type source region 42, the P-type source region 41 and the N-type source region 42 are arranged in parallel along the top surface of the substrate region 3 and are respectively connected to the trench region 5;
the trench region 5 comprises a shielding gate 51, a control gate 52, an insulating layer 53 and a metal gate; the control gate 52 and the shielding gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the body region 3 and the source region 4 through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;
the source electrode 7 is arranged above the source region 4; the drain electrode 6 is arranged below the substrate region 1; the metal gate is disposed over the control gate 52.
In one embodiment, at least two P-type source regions 41 and at least two N-type source regions 42 are alternately arranged in a longitudinal cross section of the source region 4, and the P-type source regions 41 are connected to the trench region 5, so that the distance between the P-type source regions 41 and the trench region 5 is reduced.
In one embodiment, the shielded gate trench type field effect transistor further includes a barrier buffer region 8:
the barrier buffer region 8 is disposed between the drift region 2 and the body region 3.
In one embodiment, a metal layer is disposed between the drift region 2 and the body region 3, and the interface between the metal layer and the drift region 2 forms the barrier buffer region 8.
In one embodiment, the barrier buffer region 8 is a schottky junction between the body region 3 and the drift region 2.
In one embodiment, the doping concentrations of the P-type source region 41 and the N-type source region 42 are both heavily doped.
In one embodiment, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavily doped concentration;
the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is light doping concentration;
the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration;
the doping concentration of the source region 4 is heavy doping concentration; the doping concentration of the control gate 52 is a heavy doping concentration and the doping type of the control gate 52 is P-type doping.
A second aspect of the present application provides a method for manufacturing a shielded gate trench field effect transistor, for manufacturing the shielded gate trench field effect transistor according to the first aspect of the present application, including:
preparing a substrate region with a semiconductor material;
epitaxially forming a drift region on the substrate region;
forming a base region on the drift region in an ion implantation or diffusion mode;
etching a groove on one side of the drift region;
depositing a P-type doped semiconductor material, polysilicon, an oxide and polysilicon in the trench in sequence to form a shield gate, an insulating layer and a control gate;
forming the P-type source region and the N-type source region on the substrate region by using a P-type doped semiconductor material and an N-type doped semiconductor material respectively;
forming a source electrode above the source region;
forming a metal gate over the trench;
a drain is formed under the substrate region.
In one embodiment, before forming the base region on the drift region by ion implantation or diffusion, the method includes:
and depositing metal on the drift region to form a barrier buffer region.
In one embodiment, the doping on the substrate region to form a source region includes:
and forming a P-type source region and an N-type source region on the substrate region by using a P-type doped semiconductor material and an N-type doped semiconductor material respectively, so that the P-type source region is connected with the N-type source region.
The technical scheme provided by the application can comprise the following beneficial effects:
when the avalanche transistor is in an avalanche state, the drift region is in a forward blocking state and serves as a reverse bias voltage-withstanding region, hole current generated in the reverse bias voltage-withstanding region due to impact ionization can be shunted to the P-type source region, and the hole current flows into the P-type source region after passing through the base region along the interface due to the fact that the hole current is generated at the junction of the trench region and the drift region.
The application provides a shielded gate trench field effect transistor, a source region of the shielded gate trench field effect transistor consists of a P-type source region and an N-type source region, the P-type source region and the N-type source region are arranged alternately, and the P-type source region is connected with a trench region. Therefore, when avalanche breakdown occurs, hole current can be directly injected into the P-type source region along the side edge of the trench region, the moving path of the holes is shortened, the parasitic triode is restrained from being turned on corresponding to lower forward bias voltage, and the avalanche tolerance of the shielded gate trench field effect transistor is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application, as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.
Fig. 1 is a schematic structural diagram of a shielded gate trench field effect transistor according to an embodiment of the present application;
FIG. 2 is a cross-sectional view of the shielded gate trench field effect transistor A-A' shown in FIG. 1;
FIG. 3 is a schematic diagram of a prior art shielded gate trench field effect transistor;
fig. 4 is a schematic flow chart illustrating a method for manufacturing a shielded gate trench field effect transistor according to an embodiment of the present application;
fig. 5 is another schematic flow chart of a method for manufacturing a shielded gate trench field effect transistor according to an embodiment of the present application.
Detailed Description
Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Example one
When the conventional SGT is blocked in a forward high voltage or conducted in a forward high voltage, the SGT is easy to generate hole current due to avalanche effect, and the hole current flows through a channel of a base region to cause a parasitic triode to be turned on. The turning on of the parasitic transistor will cause the transistor to avalanche fail.
In view of the above problems, embodiments of the present application provide a shielded gate trench field effect transistor, which can suppress the turn-on of a parasitic triode in an SGT before the SGT fails in avalanche.
The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a shielded gate trench field effect transistor according to an embodiment of the present application;
FIG. 2 is a cross-sectional view of the shielded gate trench field effect transistor A-A' shown in FIG. 1;
referring to fig. 1 and 2, the shielded gate trench field effect transistor includes: the transistor comprises a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a source electrode 7 and a drain electrode 6;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction,
the base region 3 and the source region 4 are sequentially arranged above the drift region 2;
the groove region 5 is arranged on the side of the substrate region 3 and is respectively connected with the drift region 2, the substrate region 3 and the source region 4;
the source region 4 consists of a P-type source region 41 and an N-type source region 42, the P-type source region 41 and the N-type source region 42 are arranged in parallel along the top surface of the substrate region 3 and are respectively connected to the trench region 5;
the trench region 5 comprises a shielding gate 51, a control gate 52, an insulating layer 53 and a metal gate; the control gate 52 and the shielding gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the body region 3 and the source region 4 through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;
the source electrode 7 is arranged above the source region 4; the drain electrode 6 is arranged below the substrate region 1; the metal gate is disposed over the control gate 52.
In the embodiment of the present application, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavy doping concentration; the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is light doping concentration; the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration; the doping concentration of the source region 4 is heavy doping concentration; the doping concentration of the control gate 52 is a heavy doping concentration and the doping type of the control gate 52 is P-type doping.
In the embodiment of the present application, the value range of the light doping concentration is 1 × 1015cm-3To 5X 1016cm-3(ii) a The value range of the medium doping concentration is 1 multiplied by 1017cm-3To 5X 1018cm-3(ii) a The value range of the heavy doping concentration is 1 multiplied by 1019cm-3To 5X 1020cm-3。
In the embodiment of the present application, the doping type of the shielding gate 51 is P-type doping, the doping type of the P-type source region 41 is P-type doping, and the doping concentration of the P-type source region 41 is medium doping concentration or heavy doping concentration.
Further, the doping concentration of the doping type of the shielding gate 51 may be a heavily doped concentration or a medium doped concentration.
Preferably, the P-type source region 41 and the N-type source region 42 are both set to the same doping concentration. For example, both of them are medium doping concentration or both of them are heavily doping concentration, so that the P-type source region 41 can more easily receive the hole current, and a better shunting effect is achieved.
When the avalanche state is present, the drift region 2 is in a forward blocking state, the drift region 2 serves as a reverse bias voltage-withstanding region, hole current generated in the reverse bias voltage-withstanding region due to impact ionization can be shunted to the P-type source region 41, and the hole current is generated at the interface between the trench region 5 and the drift region 2, passes through the base region 3 along the interface and then flows into the P-type source region 41.
FIG. 3 is a schematic diagram of a prior art shielded gate trench FET;
as shown in fig. 3, when the avalanche effect-induced hole current occurs, the hole current needs to bypass the N-type source region 42 to reach the moving path of the P-type source region 41, and thus the moving path of the hole current is longer.
As shown in fig. 2, in the shielded gate trench field effect transistor in the embodiment of the present application, when a hole current occurs, the hole current is directly injected into the P-type source region 41, and thus the moving path of the hole current is shorter.
The application provides a shielded gate trench field effect transistor, wherein a source region 4 of the shielded gate trench field effect transistor consists of a P-type source region 41 and an N-type source region 42, the P-type source region 41 and the N-type source region 42 are alternately arranged, and the P-type source region 41 is connected with a trench region 5 and a substrate region 3 at the same time. Therefore, when avalanche breakdown occurs, the hole current can be directly injected into the P-type source region 41 along the side edge of the trench region 5, the moving path of the hole current is shortened, the parasitic triode is restrained from being turned on corresponding to lower forward bias voltage, and the avalanche tolerance of the shielded gate trench field effect transistor is improved.
Preferably, M P-type source regions 41 and M N-type source regions 42 are alternately arranged, where M is an integer greater than 1. The projection areas of the P-type source region 41 and the N-type source region 42 on the placement plane are equal, so that a hole current can flow in by selecting one of the P-type source regions 41 closest to the placement plane, and a better shunting effect is achieved.
Example two
Based on the first embodiment, the present application provides another shielded gate trench field effect transistor, which can effectively guide the hole current to enter the body region more uniformly and flow into the P-type source region 41 when avalanche occurs.
The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Referring to fig. 1 and 2, the shielded gate trench field effect transistor includes:
the transistor comprises a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a source electrode 7 and a drain electrode 6;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction,
the base region 3 and the source region 4 are sequentially arranged above the drift region 2;
the groove region 5 is arranged on the side of the substrate region 3 and is respectively connected with the drift region 2, the substrate region 3 and the source region 4;
the source region 4 is composed of a P-type source region 41 and an N-type source region 42, the P-type source region 41 and the N-type source region 42 are arranged in parallel along the top surface of the substrate region 3 and are respectively connected to the trench region 5
The trench region 5 comprises a shielding gate 51, a control gate 52, an insulating layer 53 and a metal gate; the control gate 52 and the shielding gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the body region 3 and the source region 4 through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;
the source electrode 7 is arranged above the source region 4; the drain electrode 6 is arranged below the substrate region 1; the metal gate is disposed over the control gate 52.
Further, the barrier buffer region 8 is disposed between the drift region 2 and the base region 3.
In the embodiment of the present application, a metal layer is disposed between the drift region 2 and the body region 3, and an interface between the metal layer and the drift region 2 forms the barrier buffer region 8. The barrier buffer region 8 is a schottky junction between the base region 3 and the drift region 2.
The schottky junction has a nonlinear impedance characteristic, that is, a rectifying characteristic, similar to the PN junction. In the Schottky junction, the drift of majority carriers plays a main role, and carriers are basically not stored, so when the transistor is reversely conducted, the reverse recovery time of the Schottky junction is short, the reverse recovery time of the transistor can be effectively reduced, and the switching speed of the transistor is improved.
Meanwhile, in the embodiment of the present application, compared with the PN junction formed between the base region 3 and the drift region 2, when avalanche hole current occurs, the schottky junction disposed between the base region 3 and the drift region 2 can effectively guide the hole current to enter the base region 3 more uniformly after entering the metal layer, so that the hole current is uniformly shunted to each P-type source region 41, and the shunting capability of the P-type source region 41 to the hole current is improved.
In the embodiment of the present application, the doping concentrations of the P-type source region 41 and the N-type source region 42 are both heavily doped concentrations.
Because the doping concentrations of the P-type source region 41 and the N-type source region 42 are heavy doping concentrations, ohmic contact is formed, so that the resistance value of the contact surface of the P-type source region and the N-type source region is far smaller than the resistance of the semiconductor, most of the voltage drops in the active region but not in the contact surface, that is, the ohmic contact does not generate obvious additional impedance in the device, and the concentration of balanced carriers in the device is not obviously changed, which is beneficial to maintaining the performance of the device.
EXAMPLE III
Corresponding to the shielded gate trench field effect transistor and the embodiment thereof, the application also provides a preparation method of the shielded gate trench field effect transistor and the corresponding embodiment.
Fig. 4 is a schematic flow chart illustrating a method for manufacturing a shielded gate trench field effect transistor according to an embodiment of the present application.
Referring to fig. 4, the method for manufacturing the shielded gate trench field effect transistor includes:
401. preparing a substrate region with a semiconductor material;
in the embodiment of the present application, the substrate region is made of an N-type heavily doped semiconductor material, that is, the doping type of the substrate region is N-type doping, and the doping concentration of the substrate region is a heavily doped concentration.
In the embodiment of the present application, the semiconductor material is a silicon material or a silicon carbide material.
402. Epitaxially forming a drift region on the substrate region;
in the embodiment of the present application, different epitaxy processes may be adopted according to actual requirements, including but not limited to: vapor Phase Epitaxy (VPE) or Chemical Vapor Deposition (CVD).
403. Forming a base region on the drift region in an ion implantation or diffusion mode;
the ion implantation process is a process of doping silicon materials, in the practical application process, a power device product is placed at one end of an ion implanter, and a doping ion source is arranged at the other end of the ion implanter. At one end of the doping ion source, doping body atoms are ionized to carry certain charges, the charges are added to the super high speed by an electric field, penetrate through the surface layer of a product, and the doping atoms are injected into a power device by utilizing the momentum of the atoms to form a doping area.
The diffusion process is a process of doping pure impurity atoms on the surface of the silicon material, and in the practical application process, diborane or phosphine is usually used as an ion source, and the pure impurity atoms are doped on the surface of the silicon material by adopting an intermittent diffusion or displacement diffusion mode.
It should be noted that, in the embodiment of the present application, the preparation method adopted for the substrate region is not strictly limited, and in an actual process, the different processes may be selected according to actual requirements to complete the preparation of the substrate region.
404. Etching a groove on one side of the drift region;
in the embodiment of the application, a trench is etched on one side of the drift region through a photoetching process, and the residual photoresist is removed through wet etching or dry etching.
405. Depositing a P-type doped semiconductor material, polysilicon, an oxide and polysilicon in the trench in sequence to form a shield gate, an insulating layer and a control gate;
preferably, in this embodiment of the application, a P-type doped semiconductor material, a P-type doped polysilicon, an oxide, and a heavily doped polysilicon are sequentially deposited in the trench to form the shield gate, the insulating layer, and the control gate.
406. Forming the P-type source region and the N-type source region on the substrate region by using a P-type doped semiconductor material and an N-type doped semiconductor material respectively;
further, the P-type source region is connected with the N-type source region.
In the embodiment of the application, the P-type doped semiconductor material and the N-type doped semiconductor material are doped on the base region to form the P-type source region and the N-type source region, and the base region is in short circuit with the N-type source region connected with the groove region through the P-type source region, so that the substrate floating effect of the power semiconductor device is inhibited, and the stability of the performance of the device is ensured.
In the embodiment of the present application, preferably, the doping concentrations of the P-type doped semiconductor material and the N-type doped semiconductor material are both heavily doped to form an ohmic contact, so as to ensure that no significant additional impedance is generated in the device.
407. Forming a source electrode above the source region;
408. forming a metal gate over the trench;
409. a drain is formed under the substrate region.
The embodiment of the application provides a preparation method of a shielded gate trench field effect transistor, wherein a P-type source region and an N-type source region are respectively formed by a P-type doped semiconductor material and an N-type doped semiconductor material above a substrate region, and are arranged in parallel and respectively connected with the trench region, so that the interface of the trench region and the substrate region is simultaneously in short circuit with the P-type source region and the N-type source region.
When hole current occurs, the hole current is generated in the drift region and flows to the source region along the interface of the groove region and the body region, and the hole current can be directly injected into the nearest P-type source region without bypassing the N-type source region and injecting the hole current into the P-type source region.
Compared with the traditional SGT, the arrangement structure of a P-type source region and an N-type source region is changed when a source region is formed; the P-type source region and the N-type source region are arranged in parallel above the substrate region and are connected with the groove region at the same time, so that the P-type source region is directly in short circuit with the groove region, the path length of hole current is reduced, the parasitic triode can be effectively inhibited from being started corresponding to lower forward bias voltage, and the avalanche tolerance of the shielded gate groove type field effect transistor is improved.
Example four
Based on the preparation method of the shielded gate trench field effect transistor shown in the third embodiment, the embodiment of the present application provides a preparation method of a shielded gate trench field effect transistor provided with a schottky junction.
The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 5 is another schematic flow chart of a method for manufacturing a shielded gate trench field effect transistor according to an embodiment of the present application.
Referring to fig. 5, the method for manufacturing the shielded gate trench field effect transistor includes:
501. preparing a substrate region with a semiconductor material;
502. epitaxially forming a drift region on the substrate region;
503. forming the barrier buffer region on the drift region by depositing a metal;
504. forming a base region above the barrier buffer region in an ion implantation or diffusion mode;
in the embodiment of the present application, a metal layer is disposed between the drift region and the base region, and an interface between the metal layer and the drift region forms the barrier buffer region. The barrier buffer region is a Schottky junction between the base region and the drift region.
The schottky junction has a nonlinear impedance characteristic, that is, a rectifying characteristic, similar to the PN junction. In the Schottky junction, the drift of majority carriers plays a main role, and carriers are basically not stored, so when the transistor is reversely conducted, the reverse recovery time of the Schottky junction is short, the reverse recovery time of the transistor can be effectively reduced, and the switching speed of the transistor is improved.
505. Etching a groove on one side of the drift region;
506. depositing a P-type doped semiconductor material, polysilicon, an oxide and polysilicon in the trench in sequence to form a shield gate, an insulating layer and a control gate;
507. forming the P-type source region and the N-type source region on the substrate region by using a P-type doped semiconductor material and an N-type doped semiconductor material respectively;
508. forming a source electrode above the source region;
509. forming a metal gate over the trench;
510. a drain is formed under the substrate region.
In this embodiment, the above steps 501 to 510 are the step 503 added to the steps 401 to 409 in the third embodiment, and therefore, except for the step 503, the two other steps are the same, and are not described herein again.
Compared with the prior art in which a PN junction is formed between a base region and a drift region, the Schottky junction formed between the base region and the drift region can effectively improve the uniformity of hole current.
When avalanche hole current occurs, the Schottky junction arranged between the base region and the drift region can effectively guide the hole current to enter the base region more uniformly after entering the metal layer, so that the hole current is uniformly shunted to each P-type source region, and the shunting capability of the P-type source region to the hole current is improved.
Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. A shielded gate trench field effect transistor comprising:
the transistor comprises a substrate region (1), a drift region (2), a base region (3), a source region (4), a trench region (5), a drain electrode (6) and a source electrode (7);
the drift region (2) is connected with the substrate region (1) and takes the direction of the substrate region (1) pointing to the drift region (2) as the upper part,
the base region (3) and the source region (4) are sequentially arranged above the drift region (2);
the groove region (5) is arranged on the side of the substrate region (3) and is respectively connected with the drift region (2), the substrate region (3) and the source region (4);
the source region (4) consists of a P-type source region (41) and an N-type source region (42), and the P-type source region (41) and the N-type source region (42) are arranged in parallel along the top surface of the substrate region (3) and are respectively connected with the trench region (5);
the trench region (5) comprises a shielding gate (51), a control gate (52), an insulating layer (53) and a metal gate; the control grid (52) and the shielding grid (51) are sequentially arranged in the trench region (5) from top to bottom and are separated by the insulating layer (53); the control grid (52) is respectively connected with the base region (3) and the source region (4) through the insulating layer (53), and the shielding grid (51) is connected with the drift region (2) through the insulating layer (53);
the source (7) is arranged above the source region (4); the drain (6) is arranged below the substrate region (1); the metal gate is disposed over the control gate (52).
2. The shielded gate trench field effect transistor of claim 1,
on the longitudinal section of the source region (4), at least two P-type source regions (41) and at least two N-type source regions (42) are alternately arranged, and the P-type source regions (41) are connected with the trench region (5) so that the distance between the P-type source regions (41) and the trench region (5) is reduced.
3. A shielded gate trench field effect transistor according to claim 1 further comprising a barrier buffer (8):
the barrier buffer region (8) is arranged between the drift region (2) and the base region (3).
4. A shielded gate trench field effect transistor according to claim 3 wherein a metal layer is provided between the drift region (2) and the body region (3), the interface between the metal layer and the drift region (2) forming the barrier buffer region (8).
5. The shielded gate trench field effect transistor of claim 4,
the barrier buffer region (8) is a Schottky junction between the base region (3) and the drift region (2).
6. The shielded gate trench field effect transistor of claim 1,
the doping concentration of the P-type source region (41) and the doping concentration of the N-type source region (42) are heavy doping concentration.
7. The shielded gate trench field effect transistor of claim 1,
the doping type of the substrate region (1) is N-type doping, and the doping concentration of the substrate region (1) is heavy doping concentration;
the doping type of the drift region (2) is N-type doping, and the doping concentration of the drift region (2) is light doping concentration;
the doping type of the substrate region (3) is P-type doping, and the doping concentration of the substrate region (3) is medium doping concentration;
the doping concentration of the source region (4) is heavy doping concentration; the doping concentration of the control gate (52) is heavily doped concentration and the doping type of the control gate (52) is P-type doping.
8. A method for manufacturing a shielded gate trench field effect transistor, for manufacturing the shielded gate structure trench power semiconductor device according to any one of claims 1 to 7, comprising:
preparing a substrate region with a semiconductor material;
epitaxially forming a drift region on the substrate region;
forming a base region on the drift region in an ion implantation or diffusion mode;
etching a groove on one side of the drift region;
depositing a P-type doped semiconductor material, polysilicon, an oxide and polysilicon in the trench in sequence to form a shield gate, an insulating layer and a control gate;
forming the P-type source region and the N-type source region on the substrate region by using a P-type doped semiconductor material and an N-type doped semiconductor material respectively;
forming a source electrode above the source region;
forming a metal gate over the trench;
a drain is formed under the substrate region.
9. The method of claim 8, wherein the forming a body region on the drift region by ion implantation or diffusion comprises:
and depositing metal on the drift region to form a barrier buffer region.
10. The method of claim 9, wherein doping the body region to form a source region comprises:
and forming a P-type source region and an N-type source region on the substrate region by using a P-type doped semiconductor material and an N-type doped semiconductor material respectively, so that the P-type source region is connected with the N-type source region.
CN202111449785.7A 2021-11-30 2021-11-30 Shielded gate trench field effect transistor and method of making the same Pending CN114141861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111449785.7A CN114141861A (en) 2021-11-30 2021-11-30 Shielded gate trench field effect transistor and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111449785.7A CN114141861A (en) 2021-11-30 2021-11-30 Shielded gate trench field effect transistor and method of making the same

Publications (1)

Publication Number Publication Date
CN114141861A true CN114141861A (en) 2022-03-04

Family

ID=80386287

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111449785.7A Pending CN114141861A (en) 2021-11-30 2021-11-30 Shielded gate trench field effect transistor and method of making the same

Country Status (1)

Country Link
CN (1) CN114141861A (en)

Similar Documents

Publication Publication Date Title
US20080308838A1 (en) Power switching transistors
US11728421B2 (en) Split trench gate super junction power device
US9293559B2 (en) Dual trench-gate IGBT structure
CN114744037A (en) Shielding gate groove type field effect transistor with variable doping concentration structure and preparation method thereof
US20180261594A1 (en) Semiconductor device
KR20070026690A (en) Schottky device and method of forming
CN110600537B (en) Separation gate CSTBT with PMOS current clamping and manufacturing method thereof
US20230053369A1 (en) Soi lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof
CN111384153A (en) SGT device with grounded P-type region and preparation method thereof
US20200105742A1 (en) A semiconductor device comprising an insulated gate field transistor connected on series with a high voltage field effect transistor
WO2012017227A1 (en) Semiconductor device
GB2607292A (en) Semiconductor device
JP4033150B2 (en) Semiconductor device and manufacturing method thereof
CN110416295B (en) Groove-type insulated gate bipolar transistor and preparation method thereof
CN116864539A (en) Three-channel planar gate SiC MOSFET device and manufacturing method thereof
CN114141860A (en) Shielding gate structure groove type power semiconductor device and preparation method thereof
CN114171579A (en) Shielding gate groove type field effect transistor of groove type source electrode and preparation method thereof
CN114664934B (en) DMOS transistor with field plate and manufacturing method thereof
EP0461376A1 (en) Modulation doped base heterojunction bipolar transistor
CN114284339A (en) Shielding gate groove type field effect transistor of step type substrate region and preparation method thereof
CN114141861A (en) Shielded gate trench field effect transistor and method of making the same
KR20190124894A (en) Semiconductor device and method manufacturing the same
CN101512738B (en) Semiconductor device and method of forming the same
JP2022548604A (en) Semiconductor device comprising an insulated gate field effect transistor connected in series with a field effect transistor
CN114335149A (en) Shielding gate trench type field effect transistor based on charge compensation and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination