JP4033150B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

As a prior art as the background of the present invention, there is an invention described in the following Japanese Patent Application Laid-Open No. 2003-318398 filed by the present applicant.
In the prior art, an N ⁻ type polycrystalline silicon region and an N ⁺ type polycrystalline silicon region are in contact with one main surface of a semiconductor substrate in which an N ⁻ type epitaxial region is formed on an N ⁺ type silicon carbide substrate region. The epitaxial region, the N ⁻ type polycrystalline silicon layer, and the N ⁺ type polycrystalline silicon region form a heterojunction. A gate electrode is formed via a gate insulating film adjacent to the junction between the epitaxial region and the N ⁺ type polycrystalline silicon region. The N ⁻ type polycrystalline silicon region is connected to the source electrode, and a drain electrode is formed on the back surface of the N ⁺ type silicon carbide substrate region.
The conventional technology configured as described above functions as a switch by controlling the potential of the gate electrode in a state where the source electrode is grounded and a predetermined positive potential is applied to the drain electrode. That is, in a state where the gate electrode is grounded, a reverse bias is applied to the heterojunction of the N ⁻ type polycrystalline silicon region and the N ⁺ type polycrystalline silicon region and the epitaxial region, and the drain electrode and the source electrode are not connected. Current does not flow through. However, when a predetermined positive voltage is applied to the gate electrode, the gate electric field acts on the heterojunction interface between the N ⁺ type polycrystalline silicon region and the epitaxial region, and the energy formed by the heterojunction surface at the gate oxide film interface Since the thickness of the barrier is reduced, a current flows between the drain electrode and the source electrode. This prior art uses a heterojunction portion as a current cutoff / conduction control channel, so that the channel length functions at the thickness of the heterobarrier, so that a low resistance conduction characteristic is obtained.

JP 2003-318398 A

However, in the conventional structure described above, N ^- polycrystalline silicon layer and an N ⁺ -type polycrystalline silicon region and the N type ^- the hetero junction formed by the type epitaxial region, from physically hetero barrier height Since a determined leakage current is generated, there is a limit to reducing the leakage current.
The present invention has been made to solve the above-described problems of the prior art, and a semiconductor capable of easily reducing leakage current generated at a hetero interface while ensuring a driving force equivalent to that of the prior art. An object is to provide a device (high withstand voltage field effect transistor).

  In order to achieve the above object, in the present invention, a first hetero semiconductor region and a second hetero semiconductor region which are in contact with one main surface of a semiconductor substrate of a first conductivity type and have a band gap different from that of the semiconductor substrate. Each of which forms a heterojunction, and a gate electrode formed through a gate insulating film at a junction between the first hetero semiconductor region and the semiconductor substrate, and the first hetero semiconductor region And a source electrode connected to the second hetero semiconductor region, a drain electrode ohmically connected to the semiconductor substrate, and at least the second hetero semiconductor region being the first hetero semiconductor region Are configured to have opposite conductivity types.

  According to the present invention, when conducting, a heterojunction between the first source region (first hetero semiconductor region) of the first conductivity type and the drain region (hereinafter referred to as the first hetero junction). ) Is used as a channel, so that on-resistance equivalent to the conventional one can be obtained, and at the time of shut-off, a heterojunction between the second source region (second hetero semiconductor region) and the drain region The portion (hereinafter referred to as the second heterojunction portion) has an effect that the leakage current can be reduced as compared with the conventional case because the second source region has the second conductivity type.

Example 1
FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention, and shows a structure in which two structural unit cells face each other. In this embodiment, a high-voltage field effect transistor using silicon carbide as a substrate material will be described as an example.
For example, an N ⁻ -type drain region 2 is formed on an N ⁺ -type substrate region 1 of which the polytype of silicon carbide is 4H type, and the main surface facing the junction surface of drain region 2 with substrate region 1 (FIG. 1). 1, for example, a first source region 3 (first hetero semiconductor region) made of N-type polycrystalline silicon and a second source region 4 made of P-type polycrystalline silicon. (Second hetero semiconductor region) are formed. That is, the junction between the drain region 2 and the first source region 3 and the second source region 4 is made of a heterojunction made of materials having different band gaps between silicon carbide and polycrystalline silicon. There is an energy barrier.

  Further, a gate insulating film 5 made of, for example, a silicon oxide film is formed so as to be in contact with the junction surface of the first source region 3 and the drain region 2, and a gate electrode 6 insulated by the gate insulating film 5 is formed. Has been. Further, the source (the upper surface of the first source region 3 and the second source region 4 in FIG. 1) facing the joint surface of the first source region 3 and the second source region 4 with the drain region 2 has a source. An electrode 7 is formed. In addition, drain electrode 8 is formed to be connected to silicon carbide substrate region 1.

  In the present embodiment, as shown in FIG. 1, a groove is formed in the surface layer portion of the drain region 2, and a gate electrode 6 is formed in the groove via a gate insulating film 5. Although the configuration of the mold is described, as shown in FIG. 2, a so-called planar configuration in which no groove is formed in the drain region 2 may be used.

Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS. Since FIGS. 7 and 8 show a series of steps, serial numbers (A) to (F) are given to the respective steps.
First, as shown in FIG. 7A, on an N-type silicon carbide semiconductor substrate formed by epitaxially growing an N ⁻ -type drain region 2 on an N ⁺ -type substrate region 1, for example, an LP-CVD method is performed. After the polycrystalline silicon is deposited by, for example, boron doping is performed in a BBr ₃ atmosphere to form a P-type polycrystalline silicon layer (portions 3 and 4 in the figure). The polycrystalline silicon layer may be formed by depositing silicon by electron beam evaporation or sputtering and then recrystallizing by laser annealing or the like, or a single crystal heteroepitaxially grown by molecular beam epitaxy or the like It may be formed of silicon. In addition, a combination of ion implantation and activation heat treatment after implantation may be used for doping. For example, the impurity concentration of the drain region 2 is 1 × 10 ¹⁶ cm ⁻³ and the thickness is 10 μm. For example, the thickness of the polycrystalline silicon layer is 0.5 μm.

  Next, as shown in FIG. 7B, a silicon nitride film is deposited on the polycrystalline silicon layers (3, 4) by, for example, LP-CVD, and a mask material 12 is formed by photolithography and etching. To do. Note that although a silicon nitride film is described here as an example of a material for the mask material, other materials can be used as long as they are materials that can be selectively etched at least and can be easily removed. May be used.

  Next, as shown in FIG. 7C, the polysilicon layer (3, 4) and the surface layer portion of the drain region 2 are etched by, for example, reactive ion etching (dry etching), and a trench having a predetermined depth is obtained. Form. As a method for etching the polycrystalline silicon layer, other etching methods such as wet etching may be used.

Next, as shown in FIG. 8D, when phosphorus doping is performed in a POCl ₃ atmosphere, for example, with the mask material 12, phosphorus is introduced from the ion-etched surface of the polycrystalline silicon layer. However, since phosphorus is not introduced from the portion covered with the mask material 12, an N-type polycrystalline silicon layer is formed only in a region in contact with the ion-etched surface. That is, the N-type first source region 3 and the P-type second source region 4 are formed.

Next, as shown in FIG. 8E, for example, after removing the mask material 12 with a phosphoric acid solution, gate insulation is performed along the upper surfaces of the first source region 3 and the second source region 4 and the inner walls of the trenches. A film 5 is deposited. Further, a polycrystalline silicon layer to be the gate electrode 6 is deposited. Thereafter, phosphorus is doped into the polycrystalline silicon layer to be the gate electrode 6 by vapor phase diffusion using POCl ₃ . Then, after forming the gate electrode 6 by photolithography and etching, an interlayer insulating film is deposited, the interlayer insulating film and the gate insulating film 5 are removed by photolithography and etching, and a contact hole is opened.

Finally, as shown in FIG. 8F, a drain electrode 8 made of, for example, titanium (Ti) or nickel (Ni) is formed in the substrate region 1 corresponding to the back surface side, and the first corresponding to the front surface side. A source electrode 7 is formed on the top surfaces of the source region 3 and the second source region 4 by sequentially depositing titanium (Ti) and aluminum (Al), and the first embodiment of the present invention shown in FIG. A silicon carbide semiconductor device is completed.
As described above, the semiconductor device of this embodiment can be easily realized by a conventional manufacturing technique.

Next, the operation will be described. In this embodiment, for example, the source electrode 7 is grounded and a positive potential is applied to the drain electrode 8 for use.
First, when the gate electrode 6 is set to a ground potential or a negative potential, for example, the cutoff state is maintained. That is, energy barriers for conduction electrons are formed at the heterojunction interfaces between the first source region 3 and the second source region 4 and the drain region 2. At this time, since the first source region 3 and the second source region 4 are both made of a silicon material, the energy barrier difference ΔEc with the drain region 2 made of silicon carbide is substantially the same. However, the first source region 3 that is N-type and the second source region 4 that is P-type have a difference in Fermi energy indicated by energy from the conduction band to the Fermi level. The width of the depletion layer extending to the bonding interface is different. That is, since the depletion layer width extending from the junction interface with the second source region 4 is larger than the depletion layer width extending from the junction interface with the first source region 3, a higher blocking property is obtained, thereby causing leakage. The current can be reduced.

  Further, for example, when the impurity concentration of the second source region 4 is set higher than the impurity concentration of the first source region 3, a PN diode composed of the second source region 4 and the first source region 3. Since the depletion layer generated by the built-in electric field extends toward the first source region, the leakage current at the heterojunction between the first source region and the drain region can be further reduced.

  Furthermore, in this embodiment, the first source region 3 can be easily controlled and formed to have a width that the gate electric field extends from the gate electrode 6 due to the manufacturing method. If an inversion region is formed as the potential across the entire first source region 3, it is possible to further increase the blocking property as a semiconductor device.

In this embodiment, when the first source region 3 is formed, impurities are introduced by self-alignment from the portion where the gate electrode 6 is in contact with the gate insulating film 5. Even in the case of forming an integrated semiconductor element, the width of the first source region 3 can be controlled with high accuracy, so that variation in blocking performance can be suppressed.
As described above, in this embodiment, it is possible to achieve higher blocking performance than the conventional structure.

  Next, when a positive potential is applied to the gate electrode 6 so as to change from the cutoff state to the conduction state, the gate electric field is applied to the heterojunction interface where the first source region 3 and the drain region 2 are in contact via the gate insulating film 5. Therefore, an accumulation layer of conduction electrons is formed in the first source region 3 and the drain region 2 in the vicinity of the gate electrode 6. That is, the potential on the first source region 3 side at the junction interface between the first source region 3 and the drain region 2 in the vicinity of the gate electrode 6 is pushed down, and the energy barrier on the drain region 2 side becomes steep, so that the energy is increased. Conduction electrons can be conducted through the barrier.

  At this time, in this embodiment, when the first source region 3 is formed, impurities are introduced in a self-aligned manner from the portion where the gate electrode 6 is in contact with the gate insulating film 5 interposed therebetween. Even in the case where a semiconductor element in which is integrated is formed, the width of the first source region 3 can be controlled with high accuracy, so that variation in on-resistance for each cell can also be suppressed. That is, since current concentration can be suppressed, higher reliability can be obtained.

  Next, when the gate electrode 6 is again set to the ground potential in order to shift from the conductive state to the cut-off state, the conductive electron accumulation state formed at the heterojunction interface between the first source region 3 and the drain region 2 is released, Tunneling in the energy barrier stops. Then, when the flow of conduction electrons from the first source region 3 to the drain region 2 stops and the conduction electrons in the drain region 2 flow to the substrate region 1 and are exhausted, a heterojunction portion is formed on the drain region 2 side. As a result, the depletion layer spreads and becomes a cutoff state.

Further, in this embodiment, as in the conventional structure, for example, reverse conduction (reflux operation) in which the source electrode 7 is grounded and a negative potential is applied to the drain electrode 8 is also possible.
For example, when the source electrode 7 and the gate electrode 8 are set to the ground potential and a predetermined positive potential is applied to the drain electrode 8, the energy barrier against the conduction electrons disappears, and the first source region 3 and the second source region 2 from the drain region 2 side. Conduction electrons flow to the source region 4 side of the substrate, and a reverse conduction state is established. At this time, since there is no injection of holes and conduction is performed only with conduction electrons, loss due to reverse recovery current when shifting from the reverse conduction state to the cutoff state is small. It is also possible to use the gate electrode 6 described above as a control electrode without being grounded.

As described above, this embodiment can realize the same operation as the conventional structure with the configuration shown in FIG. 1 and has the following characteristics when compared with the conventional structure.
At the time of interruption, since the heterojunction between the second source region 4 and the drain region 2 has the second source region 4 of the second conductivity type, the leakage current can be reduced as compared with the conventional case.

  Further, when the impurity concentration of the second source region 4 is higher than the impurity concentration of the first source region 3, the built-in electric field of the PN diode constituted by the second source region 4 and the first source region 3 is used. Since the depletion layer due to is extended by the first source region side 3, the leakage current at the heterojunction between the first source region 3 and the drain region 2 can be further reduced.

  Further, since the lateral extension of the first source region 3 can be suppressed, the first source region 3 and the drain region can be controlled by controlling the minimum channel thickness that the electric field from the gate electrode 6 can reach. The leakage current at the first heterojunction between 2 can be easily reduced.

  Furthermore, since the lateral extension of the first source region 3 can be formed by self-alignment, the first source region 3 can be uniformly formed even when a plurality of unit cells are integrated. The leakage current is less likely to be biased at the time of interruption, and the on-resistance is less likely to be biased at the time of conduction, so that the reliability is further improved.

(Example 2)
FIG. 3 is a cross-sectional view of a second embodiment of the semiconductor device according to the present invention and corresponds to FIG. 1 of the first embodiment. In the present embodiment, the description of the same operation as in FIG. 1 is omitted, and different features will be described in detail.

As shown in FIG. 3, in this embodiment, a predetermined portion of the drain region 2 where the gate electrode 6 (via the insulating film 5) and the first source region 3 are in contact with the N ⁺ type having a higher concentration than the drain region 2 is provided. The conductive region 9 is formed. Further, the first portion of the drain region 2 is in contact with the first source region 3 or the second source region 4 at a predetermined distance from the portion where the gate electrode 6 and the source region 3 face each other. An electric field relaxation region 10 is formed. Further, a second electric field relaxation region 11 is formed so as to be in contact with the bottom of the groove where the gate electrode 6 is formed via the insulating film 5.

  With such a configuration, in the conductive state, the energy barrier at the heterojunction between the first source region 3 and the conductive region 9 can be relaxed, and higher conductive characteristics can be obtained. That is, the on-resistance is further reduced and the conduction performance is improved.

  In the cut-off state, a depletion layer corresponding to the drain potential spreads between the first electric field relaxation region 10 and the second electric field relaxation region 11 and the drain region 2. That is, in the first embodiment, the drain field applied to the heterojunction interface between the first source region 3 and the second source region 4 and the drain region 2 is relaxed by the first electric field relaxation region 10. Therefore, the leakage current is further reduced, and the interruption performance is further improved. In addition, since the drain electric field applied to the gate insulating film 5 is also relaxed by the second electric field relaxation region 11, the dielectric breakdown of the gate insulating film 5 can be made difficult to occur, and the reliability of the gate insulating film 5 can be reduced. Can be improved.

  Further, since the thickness of the semiconductor substrate (drain region 2) immediately below the second electric field relaxation region 11 is equal to the thickness of the semiconductor substrate immediately below the first electric field relaxation region 10, the manufacturing process can be simplified. Can do.

  In this embodiment, the conductive region 9, the first electric field relaxation region 10, and the second electric field relaxation region 11 are all formed, but any one of them may be formed. .

(Example 3)
4 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention, corresponding to FIG. 1 of the first embodiment. In the present embodiment, the description of the same operation as in FIG. 1 is omitted, and different features will be described in detail.
As shown in FIG. 4, in this embodiment, an N ⁺ type having a higher concentration than the drain region 2 is formed in a predetermined portion of the drain region 2 where the gate electrode 6 (via the insulating film 5) and the first source region 3 are in contact. The conductive region 9 is formed. Unlike the second embodiment, the conductive region 9 is also formed through the insulating film 5 at the bottom of the groove where the gate electrode 6 is formed.

Hereinafter, an example of a manufacturing method is shown using FIG.
First, the manufacturing steps shown in FIG. 9A are the same as those up to FIG.
Next, as shown in FIG. 9B, when phosphorus doping is performed at a higher temperature, for example, in a POCl ₃ atmosphere with the mask material 12, the ion-etched surface of the polycrystalline silicon layer is formed. In addition, phosphorus is also introduced from the silicon carbide surface. However, as in the first embodiment, phosphorus is not introduced from the portion covered with the mask material 12, so that the N-type polycrystalline silicon layer and the N ⁺ -type conductive region 9 are formed only in the region in contact with the ion-etched surface. Are formed simultaneously.

In this embodiment, the introduction of the impurity is described in the case of introducing the impurity by vapor phase diffusion, but an impurity introduction method such as ion implantation may be used.

  Next, as shown in FIG. 9C, a gate insulating film 5, a gate electrode 6, a source electrode 7, and a drain electrode 8 are formed in the same manner as in the first embodiment, and the embodiment of the present invention shown in FIG. 3 completes the silicon carbide semiconductor device.

As described above, the semiconductor device of this embodiment can be easily realized by a conventional manufacturing technique.
By adopting such a configuration, in the conductive state, similarly to the effect of the conductive region 9 shown in Example 2, the energy barrier of the heterojunction between the first source region 3 and the conductive region 9 is relaxed, Higher conduction characteristics can be obtained.

  Furthermore, in the formation method shown in this embodiment, the width of the portion of the conductive region 9 in contact with the first source region 3 can be formed with the minimum necessary width with high accuracy, self-alignment, and simultaneously. From this, it is possible to suppress the current bias between the cells at the time of conduction and at the time of interruption, and to further reduce the leakage current at the heterojunction between the first source region 3 and the conductive region 9 at the time of interruption. Therefore, the on-resistance can be reduced without significantly impairing the blocking performance.

Example 4
FIG. 5 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention, corresponding to FIG. 3 of the second embodiment. In the present embodiment, the description of the portion that performs the same operation as in FIG. 3 is omitted, and different features will be described in detail.
As shown in FIG. 5, in this example, similarly to Example 2, the conductive region 9, the first electric field relaxation region 10, and the second electric field relaxation region 11 are configured. 9 and the second electric field relaxation region 11 can be formed by self-alignment.

Hereinafter, an example of a manufacturing method is shown using FIG. 10, FIG. Since FIG. 10 and FIG. 11 show a series of steps, serial numbers (A) to (E) are given to the respective steps.
First, until the manufacturing process shown in FIG. 10A, in FIG. 7A of the first embodiment, for example, the first electric field relaxation region 10 is formed before forming the polycrystalline silicon layer, and thereafter The steps similar to those in FIG. 7A of Embodiment 1 are taken.
Next, as shown in FIG. 10B, a mask material 12 is formed in the same manner as in FIGS. 7B and 7C of Example 1, and a trench is formed by ion etching.

Next, as shown in FIG. 10C, in the state where the mask material 12 is provided, for example, aluminum ions or boron ions are ion-implanted to form the second electric field relaxation region 11.
Furthermore, as shown in FIG. 11D, when phosphorus doping is performed at a higher temperature, for example, in a POCl ₃ atmosphere with the mask material 12, the ion-etched surface of the polycrystalline silicon layer is removed from the surface. Although phosphorus is introduced, phosphorus is not introduced from the portion covered with the mask material 12, so that an N-type polycrystalline silicon layer is formed only in a region in contact with the ion-etched surface. That is, the N-type first source region 3, the P-type second source region 4, and the N ⁺ -type conductive region 9 are formed simultaneously.
In the present embodiment, the case where the second source region 4 and the conductive region 9 are formed after the second electric field relaxation region 11 is formed has been described, but either may be formed first. Absent.

Finally, as shown in FIG. 11E, the gate insulating film 5, the gate electrode 6, the source electrode 7 and the drain electrode 8 are formed in the same manner as in the first embodiment, and according to the fourth embodiment of the present invention shown in FIG. A silicon carbide semiconductor device is completed.
If the conductive region 9 is formed so that the impurity concentration is lower than that of the second electric field relaxation region 11 in the step of FIG. 11D, the structure shown in FIG. If the impurity concentration is higher than that of the electric field relaxation region 11, the structure shown in FIG. 6 is obtained.

  As described above, the semiconductor device of this embodiment can be easily realized by a conventional manufacturing technique.

  By adopting such a configuration, in the conductive state, similarly to the effect of the conductive region 9 shown in Example 2, the energy barrier of the heterojunction between the first source region 3 and the conductive region 9 is relaxed, Higher conduction characteristics can be obtained, and the drain electric field applied to the gate insulating film 5 is also relaxed by the second electric field relaxation region 11, so that dielectric breakdown of the gate insulating film 5 is less likely to occur. it can.

  Furthermore, in the formation method shown in this embodiment, the width of the portion where the conductive region 9 and the first source region 3 are in contact with each other can be formed with the minimum necessary width with high accuracy, self-alignment, and simultaneously. In addition, the second electric field relaxation region 11 can also be formed by self-alignment. From this, it is possible to suppress the current bias between the cells at the time of conduction and at the time of interruption, in addition to reducing the leakage current at the heterojunction between the first source region 3 and the conductive region 9 at the time of interruption as much as possible. In addition, since the drain electric field in the gate insulating film 5 can be relaxed at the same time, the on-resistance can be reduced without impairing the blocking performance and reliability.

As described above, in Embodiments 1 to 4, the semiconductor device using silicon carbide as the substrate material has been described as an example. However, the substrate material may be other semiconductor materials such as silicon, silicon germane, gallium nitride, and diamond.
In all the examples, the 4H type was used as the polytype of silicon carbide, but other polytypes such as 6H and 3C may be used.

  In all of the embodiments, the drain electrode 8 and the source electrode 7 are arranged so as to face each other with the drain region 2 interposed therebetween, and the so-called vertical structure transistor in which the drain current flows in the vertical direction has been described. The drain electrode 8 and the source electrode 7 may be arranged on the same main surface, and a transistor having a so-called lateral structure in which a drain current flows in the lateral direction may be used.

  Moreover, although the example using polycrystalline silicon as the material used for the first source region 3 and the second source region 4 has been described, any material such as germanium or silicon germanium can be used as long as it is a material that forms a heterojunction with silicon carbide. But it doesn't matter.

Further, as an example, N-type silicon carbide is used as the drain region 2 and N-type polycrystalline silicon is used as the first source region 3, but N-type silicon carbide and P-type polycrystalline silicon are used. Any combination of silicon, P-type silicon carbide and P-type polycrystalline silicon, or P-type silicon carbide and N-type polycrystalline silicon may be used.
Further, it goes without saying that modifications are included within the scope not departing from the gist of the present invention.

Sectional drawing of Example 1 of this invention. Sectional drawing which shows the other example of Example 1 of this invention. Sectional drawing of Example 2 of this invention. Sectional drawing of Example 3 of this invention. Sectional drawing of Example 4 of this invention. Sectional drawing which shows the other example of Example 4 of this invention. Sectional structure figure which shows a part of manufacturing process of Example 1 of this invention. Sectional structure drawing which shows another part of manufacturing process of Example 1 of this invention. Sectional structure figure which shows the manufacturing process of Example 3 of this invention. Sectional structure figure which shows a part of manufacturing process of Example 4 of this invention. Sectional structure figure which shows the other part of the manufacturing process of Example 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate region 2 ... Drain region 3 ... First source region 4 ... Second source region 5 ... Gate insulating film 6 ... Gate electrode 7 ... Source electrode 8 ... Drain electrode 9 ... Conductive region 10 ... First electric field relaxation Region 11 ... Second electric field relaxation region 12 ... Mask material

Claims (19)

A first conductivity type semiconductor substrate, a first conductivity type first hetero semiconductor region in contact with one main surface of the semiconductor substrate and having a different band gap from the semiconductor substrate, and a second conductivity type second hetero semiconductor region; A semiconductor region, a gate electrode formed through a gate insulating film at a junction between the first hetero semiconductor region and the semiconductor substrate, and connected to the first hetero semiconductor region and the second hetero semiconductor region the semiconductor device according to claim a source electrode, a Turkey that having a said semiconductor substrate and ohmic-connected drain electrodes. 2. The semiconductor device according to claim 1, wherein an impurity concentration of the second hetero semiconductor region is made larger than an impurity concentration of the first hetero semiconductor region. The semiconductor substrate has a groove at a predetermined interval on one main surface of the semiconductor substrate, and faces the gate electrode through the gate insulating film in the vicinity of the surface layer portion of the sidewall of the groove; the semiconductor device according to claim 1 or claim 2, characterized in that the first hetero semiconductor region is in contact. A conductive region that is of the first conductivity type and has a higher impurity concentration than the semiconductor substrate, in a predetermined region of the semiconductor substrate that faces the gate electrode through the gate insulating film and is in contact with the first hetero semiconductor region the semiconductor device according to any one of claims 1 to 3, characterized in that There are formed. The predetermined region of the semiconductor substrate, which is separated from the region facing the gate electrode via the gate insulating film, is in contact with either the first hetero semiconductor region or the second hetero semiconductor region . the semiconductor device according to any one of claims 1 to 4, characterized in that one electric field relaxation region is formed. Any of claims 1 to 5, characterized in that the second field limiting region of the second conductivity type at a location opposite to the gate electrode via the gate insulating film is formed in said semiconductor body A semiconductor device according to 1. According to any one of claims 1 to 6, wherein the thickness of said second of said semiconductor substrate right under the electric field relaxation region is equal to the thickness of the semiconductor substrate immediately below the first field limiting region Semiconductor device. The semiconductor device according to any one of claims 1 to 7, characterized in that said semiconductor substrate is made of wide-gap semiconductor. The semiconductor device according to any one of claims 1 to 8, characterized in that said semiconductor substrate is made of silicon carbide. The first hetero semiconductor region is a single crystal silicon, semiconductor device according to any one of claims 1 to 9, characterized in that it consists of polycrystalline silicon or amorphous silicon. The semiconductor device according to any one of claims 1 to 10, wherein the second hetero semiconductor region is made of the same semi-conductor material as the first hetero semiconductor. Laminating a hetero semiconductor layer on one principal surface side of the semiconductor substrate (1);
A step (2) of selectively etching the hetero semiconductor layer using a mask pattern; and introducing a predetermined impurity from the etched portion of the hetero semiconductor layer into the hetero semiconductor layer to form the first hetero semiconductor region. Step (3);
Forming the gate oxide film in contact with the first hetero semiconductor region and the semiconductor substrate;
The method of manufacturing a semiconductor device according to any one of claims 1 to 11, characterized in that at least containing. Laminating a hetero semiconductor layer on one principal surface side of the semiconductor substrate (1);
And step (2) is selectively etched using the mask pattern of the hetero semiconductor layer, wherein introducing the semiconductor body to a predetermined impurities facing the etched portion of the hetero semiconductor layer, wherein said conductive region first Forming a second electric field relaxation region (4),
Forming the gate oxide film in contact with the first hetero semiconductor region and the semiconductor substrate;
The method of manufacturing a semiconductor device according to claim 5 or claims 7 to 11, characterized in that at least containing. 13. The method of manufacturing a semiconductor device according to claim 12, wherein at least the step (3 ) is performed in a state having the mask pattern used in the step (2). Wherein in a state having the mask pattern used in step (2), less as the method of manufacturing the semiconductor device according to claim 1 3, characterized in that it also performs pre-Symbol step (4). Least Oite even before Symbol Step (4) The method of manufacturing a semiconductor device according to claim 13, characterized in that the introduction of impurity by ion implantation. Oite least said step (3), a method of manufacturing a semiconductor device according to claim 12, characterized in that the vapor-phase diffusion to introduce impurities. Laminating a hetero semiconductor layer on one principal surface side of the semiconductor substrate (1);
A step (2) of selectively etching the hetero semiconductor layer using a mask pattern; and introducing a predetermined impurity from the etched portion of the hetero semiconductor layer into the hetero semiconductor layer to form the first hetero semiconductor region. Step (3);
(4) introducing a predetermined impurity into the semiconductor substrate facing the etched portion of the hetero semiconductor layer to form the conductive region and the second electric field relaxation region,
Forming the gate oxide film in contact with the first hetero semiconductor region and the semiconductor substrate;
And introducing the impurities in the same step, respectively, in the step of forming the first hetero semiconductor region in the step (3) and the step of forming the conductive region in the step (4). 12. The method for manufacturing a semiconductor device according to claim 5 , wherein the method is for manufacturing a semiconductor device. The method according to claim 12 or 13 , further comprising at least a step of introducing an impurity into a predetermined region of the hetero semiconductor layer to form the second hetero semiconductor region before the step (2). The manufacturing method of the semiconductor device of description.

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