KR100691598B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to control a decrease of driving force by forming a hetero semiconductor layer in contact with a semiconductor substrate and a buried region and by patterning the hetero semiconductor layer to form a hetero semiconductor region. A predetermined groove is formed at one side of a main surface of a semiconductor substrate(1) by using a mask layer with a predetermined opening. A buried region is formed to come in contact with at lest the sidewall of the groove, protruding from the groove. A hetero semiconductor layer is formed in a manner that comes in contact with the semiconductor substrate and the buried region. The hetero semiconductor layer is patterned to form a hetero semiconductor region(3) by an etch-back process or a CMP process.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a cross-sectional view of a first embodiment of the present invention.

2A to 2H are sectional views at the time of manufacture of the first embodiment of the present invention.

3 is a cross-sectional view of another first embodiment of the present invention.

4A and 4B are sectional views at the time of manufacture of another 1st embodiment of this invention.

5A to 5F are cross-sectional views during the manufacture of another first embodiment of the present invention.

Fig. 6 is a sectional view of another first embodiment of the present invention.

Fig. 7 is a sectional view of another first embodiment of the present invention.

Fig. 8 is a sectional view of another first embodiment of the present invention.

Fig. 9 is a sectional view of another first embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: substrate

2: drain area

3: hetero semiconductor region

4: gate insulating film

5: gate electrode

6: source electrode

7: drain electrode

8: antioxidant film

9: mask layer

10: sacrificial oxide film

11: landfill area

12: second hetero semiconductor region

13: challenge area

14: field relaxation area

15, 17: home

16: cap oxide film

30: hetero semiconductor layer

[Document 1] Japanese Unexamined Patent Publication No. 2003-318398

The present invention relates to a method of manufacturing a semiconductor device.

As a prior art which becomes the background of this invention, there exists following patent document 1 which this applicant applied for.

In this prior art, an N ^- type polycrystalline silicon region and an N ⁺ type polycrystalline silicon region are formed on a main surface of a semiconductor substrate on which an N ^- type silicon carbide epitaxial region is formed on an N ⁺ type silicon carbide substrate. The epitaxial region, the N ^- type polycrystalline silicon region, and the N ⁺ type polycrystalline silicon region have a heterojunction. Further, a gate electrode is formed adjacent to the junction of the epitaxial region and the N ⁺ type polycrystalline silicon region via a gate insulating film. The N ⁻ type polycrystalline silicon region is connected to the source electrode, and a drain electrode is formed on the back side of the N ⁺ type silicon carbide substrate.

The semiconductor device of the prior art having the above-described structure functions as a switch by controlling the potential of the gate electrode while the source electrode is grounded and a predetermined amount of potential is applied to the drain electrode. That is, in the state where the gate electrode is grounded, a reverse bias is applied to the heterojunction of the N ⁻ type polycrystalline silicon region and the N ⁺ type polycrystalline silicon region and the epitaxial region so that no current flows between the drain electrode and the source electrode. However, when a predetermined positive voltage is applied to the gate electrode, the gate electric field acts on the heterojunction interface between the N ⁺ type polycrystalline silicon region and the epitaxial region, and the thickness of the energy barrier formed by the heterojunction surface of the gate oxide film interface becomes thin. The current flows between the drain electrode and the source electrode. In this prior art, since the hetero junction is used as a control channel for blocking current and conducting current, the channel length functions about the thickness of the hetero barrier, so that low resistance conduction characteristics can be obtained.

[Patent Document 1] Japanese Unexamined Patent Publication No. 2003-318398

However, in the above prior art, when the polycrystalline silicon region formed on the silicon carbide epitaxial region is patterned and the channel interface between the polycrystalline silicon region and the silicon carbide epitaxial region is formed, physical etching such as dry etching is used, The etching surface of the silicon carbide epitaxial region is damaged, and the driving force is lowered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device capable of suppressing a decrease in driving force.

MEANS TO SOLVE THE PROBLEM In order to solve the said subject, this invention is a hetero semiconductor region which contact | connects one main surface of a 1st conductivity type semiconductor substrate, and whose band gap is different from the said semiconductor substrate, and the junction part of the said hetero semiconductor region and the said semiconductor substrate A mask layer having a predetermined opening in a method of manufacturing a semiconductor device having a gate electrode formed through a gate insulating film, a source electrode connected to the hetero semiconductor region, and a drain electrode ohmic connected to the semiconductor substrate. Forming a predetermined groove on one main surface side of the semiconductor substrate by using a method, forming a buried region in contact with at least the sidewall of the groove, and protruding from the groove, and in the semiconductor substrate and the buried region Forming a hetero semiconductor layer so as to be in contact; and patterning the hetero semiconductor layer to form the hetero semiconductor. It is a structure including the process of forming an area | region.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail using drawing. In addition, in the drawing demonstrated below, the thing with the same function attaches | subjects the same code | symbol, and the description of the repetition is abbreviate | omitted.

(1st embodiment)

"rescue"

1 shows a first embodiment of a semiconductor device according to the present invention. The figure is sectional drawing in which two structural unit cells faced. In this embodiment, a semiconductor device using silicon carbide (SiC) as a substrate material will be described as an example.

For example, a drain region 2 composed of an N ⁻ type silicon carbide epitaxial layer is formed on a substrate 1 having a polytype of silicon carbide of 4H type, N ⁺ type, so that the substrate 1 of the drain region 2 is formed. For example, a hetero semiconductor region 3 made of, for example, N-type polycrystalline silicon is formed so as to be in contact with the main surface opposite to the bonding surface of the same. That is, the junction of the drain region 2 and the hetero semiconductor region 3 is a heterojunction made of a material having a different band gap between silicon carbide and polycrystalline silicon, and an energy barrier exists at the junction interface. A gate insulating film 4 made of, for example, a silicon oxide film is formed in contact with the junction portion of the hetero semiconductor region 3 and the drain region 2. Further, on the gate insulating film 4, the source electrode 6 is disposed on the surface of the gate semiconductor 5 facing the junction surface of the hetero semiconductor region 3 with the drain region 2, and the drain electrode is disposed on the substrate 1. (7) is formed to connect. In this embodiment, as shown in Fig. 1, a so-called trench type structure is formed in which the groove 15 is formed in the drain region 2 to fill the gate electrode 5.

<< production method >>

Next, a method for manufacturing a silicon carbide semiconductor device in accordance with the embodiment shown in FIG. 1 will be described with reference to FIGS. 2A to 2H.

First, as shown in FIG. 2A, an anti-oxidation film (mask) is formed on an N-type silicon carbide semiconductor substrate formed by epitaxially growing an N ⁻ -type drain region 2 on an N ⁺ -type silicon carbide substrate 1. As layer 8, a silicon nitride film formed by, for example, LP-CVD is deposited. Further, a mask layer 9 having a predetermined opening is formed on the anti-oxidation film 8 of the silicon nitride film by photolithography and etching.

Next, as shown in Fig. 2B, the mask layer 9 is used as a mask, and the surface layer portions of the anti-oxidation film 8 and the drain region 2 are etched by, for example, reactive ion etching (dry etching), The drain region 2 etches a predetermined depth to form the groove 15. In addition, another etching method may be used as a method of etching the antioxidant film 8 and the drain region 2 of the nitride oxide film as long as it is an anisotropic etching method.

Next, as shown in Fig. 2C, since the etching damage occurs in the etched drain region 2 by dry etching, in order to remove it, for example, sacrificial oxidation is performed by dry O ₂ oxidation at 1100 占 폚. A sacrificial oxide film 10 is formed. At this time, since the silicon nitride film formed by LP-CVD is used as the anti-oxidation film 8 in this embodiment, since the oxidation rate is relatively close to the drain region 2 made of silicon carbide, the sacrificial oxide film 10 having the same degree is used. ) Is also formed on the antioxidant film 8 of the silicon nitride film. For this reason, the upper end part of the side wall of the drain region 2 and the edge part of the antioxidant film 8 can maintain substantially the same surface. As the method for forming the sacrificial oxide film 10, oxidation in dry O ₂ oxidation is taken as an example, but any method may be used as long as the area where etching damage of the drain region 2 has occurred can be blown into the oxide film.

Next, as shown in Fig. 2D, the sacrificial oxide film 10 (Fig. 2C) is removed by wet etching with a mixed solution of ammonium fluoride and hydrofluoric acid, for example.

Next, as shown in Fig. 2E, the buried region 11 is formed using a reflowable material such as SOG. In the present embodiment, the case where the buried region 11 is formed to be substantially flush with the upper end of the groove 15 including the groove of the antioxidant film 8 is shown, but at least the drain region 2 and the antioxidant film 8 are shown. If it is formed so as to be in contact with the joining interface of), it may not be completely embedded or may protrude from the groove. In addition, when forming the buried region 11, the material of the buried region may also be formed on the antioxidant film 8, and then etched back to form the buried region.

Next, as shown in Fig. 2F, the anti-oxidation film 8 made of silicon nitride is removed with, for example, a phosphoric acid solution, and then polycrystalline silicon is deposited by, for example, LP-CVD. Thereafter, for example, phosphorus doping is performed in a POCl ₃ atmosphere to form a hetero semiconductor layer 30 made of N-type polycrystalline silicon. The polycrystalline silicon layer may be formed by recrystallization by laser annealing or the like after being deposited by an electron beam deposition method, a sputtering method, or the like, or may be formed of monocrystalline silicon grown heteroepitaxially by, for example, molecular beam epitaxy. In addition, a combination of ion implantation and activation heat treatment after implantation may be used for doping the polycrystalline silicon layer.

Next, as shown in Fig. 2G, for example, a mask layer (not shown) having a predetermined opening is formed in a predetermined region of the hetero semiconductor 30 of polycrystalline silicon by photolithography and etching. For example, a part of the hetero semiconductor layer 30 is etched by reactive ion etching (dry etching) to form the hetero semiconductor region 3. Then, for example, the buried regions 11 (FIG. 2F) formed of oxides are wet etched with a mixed solution of ammonium fluoride and hydrofluoric acid, for example.

Finally, as shown in FIG. 2H, the gate insulating film 4 is deposited along the inner walls of the hetero semiconductor region 3 and the drain region 2. Furthermore, the polycrystalline silicon layer used as the gate electrode 5 is deposited. Thereafter, phosphorus is doped into the polycrystalline silicon layer serving as the gate electrode 5 by high layer diffusion using POCl ₃ . Then, after forming the gate electrode 5 by photolithography, etching, etc., the drain electrode 7 which consists of titanium (Ti) and nickel (Ni) is attached to the board | substrate 1 corresponded to the back surface side, for example. The source electrode 6 is formed by sequentially depositing titanium (Ti) and aluminum (Al) in the hetero semiconductor region 3 corresponding to the surface side (isolated with the gate electrode 5 by an insulating film). ], The silicon carbide semiconductor device according to the first embodiment of the present invention shown in FIG. 1 is completed. In addition, in this embodiment, although the shape in which the gate electrode 5 was embedded in the groove is shown as an example, it may be formed so that it may be mounted on the hetero semiconductor region 3 via the gate insulating film 4. In addition, although the shape which the neighboring ones connected so that the source electrode 6 may cover the gate electrode through the insulating film is shown as an example, it does not matter even if it is not connected.

As described above, in the present embodiment, a first semiconductor semiconductor substrate (substrate 1 and drain region 2) and a hetero semiconductor region in contact with one main surface of the semiconductor substrate and having a band gap different from that of the semiconductor substrate ( 3), a gate electrode 5 formed through a gate insulating film 4 at a junction portion of the hetero semiconductor region 3 and the semiconductor substrate, a source electrode 6 connected to the hetero semiconductor region 3, and the semiconductor In the method for manufacturing a semiconductor device having a drain electrode 7 resistively connected to a substrate, a predetermined groove 15 is formed on one main surface side of the semiconductor substrate by using a mask layer 9 having a predetermined opening. And a second step of forming the buried region 11 so as to be in contact with at least the sidewall of the groove 15 and to be pushed out of the groove 15, and to be in contact with the semiconductor substrate and the buried region 11. Third process of forming the hetero semiconductor layer 30 And a fourth step of forming the hetero semiconductor region 3 by patterning the hetero semiconductor layer 30.

With such a configuration, the semiconductor device of the present embodiment can be easily realized by a conventional manufacturing technique, and at the same time, the upper end portion of the groove 15 of the drain region 2 in which the etching damage is removed by the present manufacturing method and the hetero semiconductor. The structure in which the edge part of the area | region 3 becomes substantially the same surface can be formed easily. From this, the gate electrode 5 via the gate insulating film 4 can be formed so as to face substantially perpendicularly to the junction interface between the drain region 2 and the hetero semiconductor region 3, so that it is applied to the gate electrode 5. Since the electric field spreads efficiently at the heterojunction interface according to one voltage, the driving force at the time of conduction improves. In addition, in this embodiment in which the drain region 2 is made of silicon carbide by using a silicon nitride film as the anti-oxidation film 8, the upper end of the groove 15 of the drain region 2 and the end of the hetero semiconductor region 3 are removed. It can be formed on the same plane more easily.

In the fourth step, the hetero semiconductor region 3 may be formed by etching back the hetero semiconductor layer 30. Thereby, the source electrode 6 can be formed on a flat surface, and the reliability of a semiconductor device can be improved.

Further, the buried region 11 is made of a material which can be removed after the third step. Thereby, a manufacturing process becomes easy. That is, the material of the buried region 11 is easily etched by wet etching, and a material having a relatively large selectivity with the drain region 2 and the hetero semiconductor region 3 is used, so that the manufacturing process becomes easy.

After the fourth step, the gate insulating film 4 is formed to contact the hetero semiconductor region 3 and the heterojunction interface of the semiconductor substrate. Thereby, the heterojunction insulated gate field effect transistor can be provided in an easy manufacturing process.

In addition, a sacrificial oxidation step is provided between the first step and the second step. It is possible to easily form a structure in which the upper end of the groove 15 of the drain region 2 and the end of the hetero semiconductor region 3 are substantially flush with each other while removing the etching damage. From this, the gate electrode 5 via the gate insulating film 4 can be formed so as to face substantially perpendicularly to the junction interface between the drain region 2 and the hetero semiconductor region 3, so that it is applied to the gate electrode 5. Since the electric field spreads efficiently at the heterojunction interface according to one voltage, the driving force at the time of conduction improves.

Further, the semiconductor substrate is made of silicon carbide. This makes it possible to easily realize a high breakdown voltage semiconductor device using a general semiconductor material.

In addition, the hetero semiconductor region 3 is composed of at least one of monocrystalline silicon, polycrystalline silicon or amorphous silicon. Thereby, a semiconductor device can be easily implemented using a general semiconductor material.

In addition, the antioxidant film 8 which is a mask layer consists of a material which has a value close to the thermal oxidation rate of silicon carbide. As a result, the sacrificial oxide film 10 of the same degree is also formed on the antioxidant film 8 of the silicon nitride film. For this reason, the upper end part of the side wall of the drain region 2 and the edge part of the antioxidant film 8 can maintain substantially the same surface.

"action"

Next, the operation will be described. In the present embodiment, for example, the source electrode 6 is grounded and a positive potential is applied to the drain electrode 7 to be used.

First, when the gate electrode 5 is set at, for example, the ground potential or the negative potential, the blocking state is maintained. That is, energy barriers to conductive electrons are formed at the heterojunction interfaces of the hetero semiconductor region 3 and the drain region 2, respectively.

Next, when a positive potential is applied to the gate electrode 5 so as to change from the blocking state to the conducting state, the gate is passed through the gate insulating film 4 to the heterojunction interface where the hetero semiconductor region 3 and the drain region 2 contact each other. Since the electric field extends, an accumulation layer of conductive electrons is formed in the hetero semiconductor region 3 and the drain region 2 near the gate electrode 5. That is, the potential at the hetero semiconductor region 3 side at the junction interface between the hetero semiconductor region 3 and the drain region 2 in the vicinity of the gate electrode 5 is lowered and the energy at the drain region 2 side is reduced. The steepness of the barrier allows conductive electrons to conduct within the energy barrier. At this time, by adopting the present manufacturing method, a structure in which the upper end portion of the groove 15 of the drain region 2 from which the etching damage is removed and the end portion of the hetero semiconductor region 3 are approximately the same plane can be easily formed. From this, the gate electrode 5 via the gate insulating film 4 can be formed so as to face substantially perpendicularly to the junction interface between the drain region 2 and the hetero semiconductor region 3, so that the gate electrode 5 Since the electric field spreads efficiently on the heterojunction interface according to the applied voltage, high driving force can be obtained.

Next, when the gate electrode 5 is brought to the ground potential again so as to transition from the conduction state to the interruption state, the accumulation state of the conductive electrons formed at the heterojunction interface of the hetero semiconductor region 3 and the drain region 2 is released. Tunneling in the energy barrier is stopped. Then, the flow of the conduction electrons from the hetero semiconductor region 3 to the drain region 2 stops, and the conduction electrons in the drain region 2 flow to the substrate 1, and when exhausted, the drain region 2 side The depletion layer extends from the heterojunction to the blocking state.

Also in this structure, similarly to the conventional structure, for example, reverse conduction (reflux operation) in which the negative potential is applied to the drain electrode 7 by grounding the source electrode 6 is also possible.

For example, when a predetermined positive potential is applied to the drain electrode 7 with the source electrode 6 and the gate electrode 5 at the ground potential, the energy barrier to the conductive electrons disappears, and the drain region 2 is removed from the drain region 2 side. Conductive electrons flow into the hetero semiconductor region 3 to become a reverse conduction state. At this time, since no conduction of holes is conducted and only conduction electrons are conducted, the loss due to reverse recovery current at the time of transition from the reverse conduction state to the interruption state is also small. It is also possible to use the above-described gate electrode 5 as a control electrode without grounding.

<Structure of Figure 3>

In the structure of FIG. 3, the hetero semiconductor region 3 is formed flat, the gate insulating film 4 is formed on the sidewall of the groove 15, and the gate electrode 5 is the groove 15, compared to the structure of FIG. 1. Is embedded in the flat, and the source electrode 6 is formed flat on the surface of the device is different.

Next, a method of manufacturing a silicon carbide semiconductor device having the structure shown in FIG. 3 will be described with reference to FIGS. 4A to 4B.

First, up to FIG. 2F showing the manufacturing process of the structure of FIG. 1, it is similar to the structure of FIG. In the structure shown in FIG. 2F, the hetero semiconductor region 3 is flattened by chemical mechanical polishing (CMP (Chemical Mechanical Polishing)), and the hetero semiconductor region 3 and the buried region are shown in FIG. 4A. The surface containing (11) is formed flat.

Next, the buried region 11 formed of, for example, an oxide is wet etched with a mixed solution of ammonium fluoride and hydrofluoric acid, for example, to be in the state shown in Fig. 4B.

Finally, as shown in FIG. 3, the gate insulating film 4 is deposited along the inner surfaces of the hetero semiconductor region 3 and the drain region 2 similarly to the structure of FIG. Furthermore, the polycrystalline silicon layer used as the gate electrode 5 is deposited. Thereafter, phosphorus is doped into the polycrystalline silicon layer serving as the gate electrode 5 by high layer diffusion using POCl ₃ . Then, after forming the gate electrode 5 by photolithography, etching, etc., the drain region 7 which consists of titanium (Ti) and nickel (Ni) is formed in the board | substrate 1 corresponded to the back surface side, for example. The source electrode 6 is formed by sequentially depositing titanium (Ti) and aluminum (Al) in the hetero semiconductor region 3 corresponding to the surface side (isolated from the gate electrode 5 by an insulating film). 3, a silicon carbide semiconductor device having the structure of the present invention shown in FIG. In addition, in this embodiment, although the shape in which the gate electrode 5 was embedded in the groove is shown as an example like FIG. 1, it may be formed so that it may be mounted on the hetero semiconductor region 3 via the gate insulating film 4. In addition, although the shape which the neighboring ones connected so that the source electrode 6 may cover the gate electrode through the insulating film is shown as an example, it does not matter even if it is not connected.

In the fourth step of forming the hetero semiconductor region 3 by patterning the hetero semiconductor layer 30 (see FIG. 2F) as described above, the hetero semiconductor region 3 is formed by chemical mechanical polishing of the hetero semiconductor layer 30. Form. Thus, in the manufacturing process of the structure of FIG. 1, as shown in FIG. 2G, a mask layer (not shown) having a predetermined opening is formed in a predetermined region of the hetero semiconductor layer 30 by photolithography and etching. The process can be simplified. Moreover, since the surface of an element can be made flat, problems regarding reliability, such as disconnection, can be suppressed.

<The manufacturing method of FIGS. 5A-5F>

Next, another manufacturing method of the present embodiment will be described with reference to FIGS. 5A to 5F. The structure after completion is the same as that of FIG.

First, up to FIG. 2D showing the manufacturing process of the structure of FIG. 1, the same as that of FIG. In the structure shown in FIG. 2D, as shown in FIG. 5A, a gate insulating film 4 is deposited along the inner walls of the anti-oxidation film (mask layer) 8 and the drain region 2. In addition, the polycrystalline silicon layer 50 serving as the gate electrode 5 is deposited. Thereafter, phosphorus is doped into the polycrystalline silicon layer 50 serving as the gate electrode 5 by high layer diffusion using POCl ₃ .

Next, the polycrystalline silicon layer 50 is etched back to form the gate electrode 5 in the state shown in Fig. 5B.

Next, as shown in Fig. 5C, a cap oxide film 16 is formed on the gate electrode 7 by thermal oxidation.

Next, as shown in FIG. 5D, the upper portions of the gate insulating film 4 and the cap oxide film 16 on the antioxidant film 8 are removed by dry etching.

Next, as shown in Fig. 5E, after removing the anti-oxidation film 8 made of silicon with, for example, a phosphoric acid solution, polycrystalline silicon is deposited by, for example, LP-CVD. Thereafter, for example, phosphorus doping is performed in a POCl ₃ atmosphere to form a hetero semiconductor layer 30 made of N-type polycrystalline silicon. The polycrystalline silicon layer may be formed by recrystallization by laser annealing or the like after being deposited by an electron beam deposition method, a sputtering method, or the like, or may be formed of single crystal silicon grown heteroepitaxially by, for example, molecular beam epitaxy or the like. In addition, a combination of ion implantation and activation heat treatment after implantation may be used for doping the polycrystalline silicon layer.

Finally, similarly to the structure of FIG. 3, as shown in FIG. 5F, the hetero semiconductor region 3 is flatly processed by chemical mechanical polishing, and the substrate 1 corresponding to the back surface side is, for example, titanium (Ti) The drain electrode 7 made of nickel (Ni) is formed, and the source electrode 6 is formed by sequentially depositing titanium (Ti) and aluminum (Al) in the hetero semiconductor region 3 corresponding to the surface side. The silicon carbide semiconductor device of the structure of this invention shown in 3 is completed.

As described above, in the present embodiment, a first semiconductor semiconductor substrate (substrate 1 and drain region 2) and a hetero semiconductor region in contact with one main surface of the semiconductor substrate and having a band gap different from that of the semiconductor substrate ( 3), a gate electrode 5 formed through a gate insulating film 4 at a junction portion of the hetero semiconductor region 3 and the semiconductor substrate, a source electrode 6 connected to the hetero semiconductor region 3, and the semiconductor A method of manufacturing a semiconductor device having a drain electrode 7 resistively connected to a substrate, wherein the predetermined groove 15 is formed on one main surface side of the semiconductor substrate by using a mask layer having a predetermined opening. A first step, a second step of forming a gate insulating film 4 in contact with at least the sidewall of the groove 15, a third step of forming a gate electrode 5 in contact with the gate insulating film 4, and the semiconductor substrate In contact with each other and on the gate electrode 5 And a fourth step of forming the hetero semiconductor layer 30 through the cap oxide film 16 serving as the insulating film, and a fifth step of forming the hetero semiconductor region 3 by patterning the hetero semiconductor layer 30. It is.

With such a configuration, the semiconductor device of the present embodiment can be easily realized by a conventional manufacturing technique, and the upper end portion of the groove 15 of the drain region 2 in which the etching damage is removed by taking the present manufacturing method is heterogeneous. The structure in which the edge part of the semiconductor region 3 becomes substantially the same surface can be formed easily. From this, the gate electrode 5 via the gate insulating film 4 can be formed so as to face substantially perpendicularly to the junction interface between the drain region 2 and the hetero semiconductor region 3, so that it is applied to the gate electrode 5. Since the electric field spreads efficiently at the heterojunction interface along one voltage, the driving force at the time of conduction improves. In addition, in this embodiment in which the drain region 2 is made of silicon carbide by using a silicon nitride film as the anti-oxidation film 8, the upper end of the groove 15 of the drain region 2 and the end of the hetero semiconductor region 3 are removed. It can be formed on the same plane more easily.

In addition, the gate insulating film 4 includes a thermal oxide film formed at least by thermal oxidation. Since the gate insulating film 4 of good quality can be formed easily by this, the improvement of the driving force in a conductive state can be expected, and high reliability can be obtained.

In addition, although the structure of FIGS. 1 and 3 has been described as an example using the manufacturing method of the present invention, the present invention can be applied to the structure shown in FIGS. 6 to 9, for example.

<Structure of Figure 6>

The structure of FIG. 3 differs from that of FIG. 1 in that a hetero semiconductor region made of, for example, an N-type polycrystalline silicon is formed so as to be in contact with a main surface of the drain region 2 opposite to the bonding surface of the substrate 1. The second hetero semiconductor region 12 made of 3) and P-type polycrystalline silicon is formed. That is, the junction portion of the drain region 2, the hetero semiconductor region 3, and the second hetero semiconductor region 12 is composed of a hetero junction made of a material having a different band gap between SiC and polycrystalline silicon, and an energy barrier at the junction interface. This exists. A gate insulating film 4 made of, for example, a silicon oxide film is formed in contact with the junction portion of the hetero semiconductor region 3 and the drain region 2. Further, on the gate insulating film 4, the source electrode 6 is disposed on the surface of the gate electrode 5 that faces the junction surface of the hetero semiconductor region 3 and the drain region 2 of the second hetero semiconductor region 12. The drain electrode 7 is connected to the substrate 1.

In the method of manufacturing the structure of FIG. 6, after the hetero semiconductor region 3 is formed, the conductive portion of the hetero semiconductor region 3 (for example, the second hetero semiconductor region 12) is transferred to the predetermined portion of the hetero semiconductor region 3, for example. An impurity of type P, which is opposite to the type N, is introduced. Thus, the conductivity type and impurity concentration of the hetero semiconductor region can be designed freely.

Next, the operation of this structure will be described. Basically, the structure is the same as that of FIG. That is, energy barriers to conductive electrons are formed at the heterojunction interfaces of the hetero semiconductor region 3, the second hetero semiconductor region 12, and the drain region 2, respectively. At this time, since both the hetero semiconductor region 3 and the second hetero semiconductor region 12 are made of a silicon material, the energy barrier difference ΔEc with the drain region 2 made of silicon carbide becomes substantially the same. However, in the N-type hetero semiconductor region 3 and the P-type second hetero semiconductor region 12, there is a difference in the Fermi energy represented by the energy from the conduction band to the Fermi level. Therefore, the depletion layer extending to the junction interface of the drain region 2 is different. Width is different. That is, since the depletion layer width extending from the junction interface with the second hetero semiconductor region 12 is larger than the depletion layer width extending from the junction interface with the hetero semiconductor region 3, higher blocking property, that is, leakage current can be reduced. Can be. For example, when the impurity concentration of the second hetero semiconductor region 12 is set higher than the impurity concentration of the hetero semiconductor region 3, the second hetero semiconductor region 12 is composed of the hetero semiconductor region 3 and the hetero semiconductor region 3. Since the depletion layer generated by the built-in electric field of the PN diode extends toward the hetero semiconductor region 3 side, the leakage current at the heterojunction between the hetero semiconductor region 3 and the drain region can be further reduced.

In the present structure, when the hetero semiconductor region 3 is designed to have a width such that the gate electric field extends from the gate electrode 5, for example, the gate electrode 5 is negatively charged, for example, a hetero semiconductor region. If the inversion region is formed in the entire area of (3), it is also possible to further improve the blocking property as a semiconductor device.

<Structure of Figure 7>

In the structure of FIG. 7, in the structure of FIG. 1, an N ⁺ type conductive region 13 having a higher concentration than the drain region 2 is formed in a predetermined portion between the gate insulating film 4 and the drain region 2. As shown in FIG. Hereinafter, an example of a manufacturing method is demonstrated.

For example, in the state shown in Fig. 2D, when phosphorus doping is carried out at a higher temperature than, for example, in a POCl ₃ atmosphere, phosphorus is introduced to the silicon carbide surface to form an N ⁺ type conductive region 13. In addition, the introduction of impurities may use the introduction of impurities by solid phase diffusion, or, for example, a method of introducing impurities such as ion implantation may be used.

With such a configuration, in the conductive state, the energy barrier of the heterojunction between the hetero semiconductor region 3 and the conductive region 13 is alleviated, and the hetero semiconductor region 3 passes through the conductive region 13 to the drain region 2. A large number of carriers tend to flow, thereby obtaining higher conduction characteristics and further reducing on resistance.

<Structure of Figure 8>

In addition to the structure of FIG. 1, the structure of FIG. 8 includes the drain region 2 in contact with the hetero semiconductor region 3 where the gate electrode 5 and the hetero semiconductor region 3 are spaced apart from each other by a predetermined distance. An electric field relaxation region 14 is formed on the surface. Hereinafter, an example of a manufacturing method is demonstrated.

In FIG. 2A of the structure of FIG. 1, for example, before forming the hetero semiconductor layer 30, a mask layer having a predetermined opening is used as a mask, and ion implantation of aluminum ions or boron ions to form a P-type field relaxation region. (14) is formed. Moreover, you may form by solid phase diffusion. The subsequent process is the same as the structure of FIG.

With such a configuration, in the conduction state, the energy barrier of the heterojunction between the hetero semiconductor region 3 and the drain region 2 can be alleviated to obtain higher conduction characteristics. In other words, the on-resistance is smaller and the conduction performance is improved.

In the blocking state, the depletion layer according to the drain potential is diffused between the electric field relaxation region 14 and the drain region 2. That is, since the drain electric field applied to the heterojunction interface between the hetero semiconductor region 3 and the drain region 2 is relaxed by the electric field relaxation region 14, the leakage current is further reduced and the breaking performance is further improved.

<Structure of Figure 9>

The structure of FIG. 9 is a modification of the structure of FIG. 1, and in FIG. 2A, the groove 17 is formed in the drain region 2 before the oxidation prevention film 8 is formed, and then the hetero semiconductor layer 30 is formed. ). The subsequent process is the same as the structure of FIG. Such a structure can further reduce the leakage current in the hetero semiconductor region 3 than the structure of FIG.

As described above, various structures as shown in Figs. 6 to 9 can be formed using the basic process of the present invention.

As mentioned above, although the semiconductor device which made silicon carbide the board | substrate material was demonstrated as an example in all the structures of this embodiment, the board | substrate material may be other semiconductor materials, such as silicon, silicon germanium, gallium nitride, and a diamond. In addition, in all structures, although it demonstrated using 4H type as a polytype of silicon carbide, other polytypes, such as 6H and 3C, may be sufficient. In all the structures, the drain electrode 7 and the source electrode 6 are arranged so as to face the drain region 2 so as to face each other, and the drain current 7 is described as a transistor having a so-called vertical structure. For example, a so-called transverse transistor may be provided in which the drain electrode 7 and the source electrode 6 are disposed on the same main surface and the drain current flows in the transverse direction.

In addition, although the example using polycrystalline silicon as a material used for the hetero semiconductor region 3 or the second hetero semiconductor region 12 has been described, any material may be used as long as it is a material forming a heterojunction with silicon carbide. As an example, an N-type silicon carbide is described as the drain region 2 using N-type polycrystalline silicon as the hetero semiconductor region 3, but N-type silicon carbide, P-type polycrystalline silicon, and P are respectively described. Any combination of type silicon carbide and P type polycrystalline silicon, P type silicon carbide and N type polycrystalline silicon may be used.

Moreover, it goes without saying that modification is included in the range which does not deviate from the main point of this invention.

In addition, the mask layer used in order to form a predetermined | prescribed groove | channel on the one main surface side of a semiconductor base material in a claim corresponds to the mask layer 9 and the antioxidant film 8 in embodiment.

According to this invention, the manufacturing method of the semiconductor device which can improve a driving force can be provided.

Claims (11)

A first conductivity type semiconductor substrate, A hetero semiconductor region in contact with one main surface of the semiconductor substrate and having a band gap different from that of the semiconductor substrate, A gate electrode formed through a gate insulating film at a junction portion of the hetero semiconductor region and the semiconductor substrate; A source electrode connected to the hetero semiconductor region, In the manufacturing method of the semiconductor device which has a drain electrode resistance-connected with the said semiconductor base material, A first step of forming a predetermined groove on one main surface side of the semiconductor substrate by using a mask layer having a predetermined opening, A second step of forming a buried region in contact with at least a sidewall of said groove and protruding from said groove, A third step of forming a hetero semiconductor layer in contact with the semiconductor substrate and the buried region; And a fourth step of patterning said hetero semiconductor layer to form said hetero semiconductor region. The method for manufacturing a semiconductor device according to claim 1, wherein in the fourth step, the hetero semiconductor region is formed by etching back the hetero semiconductor layer. The method for manufacturing a semiconductor device according to claim 1, wherein in the fourth step, the hetero semiconductor region is formed by chemical mechanical polishing of the hetero semiconductor layer. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the buried region is made of a material which can be removed after the third step. The semiconductor device according to any one of claims 1 to 4, further comprising a step of forming the gate insulating film so as to contact the heterojunction interface between the hetero semiconductor region and the semiconductor substrate after the fourth step. Manufacturing method. A first conductivity type semiconductor substrate, A hetero semiconductor region in contact with one main surface of the semiconductor substrate and having a band gap different from that of the semiconductor substrate, A gate electrode formed through a gate insulating film at a junction portion of the hetero semiconductor region and the semiconductor substrate; A source electrode connected to the hetero semiconductor region, In the manufacturing method of the semiconductor device which has a drain electrode resistance-connected with the said semiconductor base material, A first step of forming a predetermined groove on one main surface side of the semiconductor substrate by using a mask layer having a predetermined opening, A second step of forming the gate insulating film at least in contact with a sidewall of the groove; A third step of forming the gate electrode in contact with the gate insulating film; A fourth step of forming a hetero semiconductor layer on the gate electrode via the semiconductor substrate and the interlayer insulating film; And a fifth step of patterning the hetero semiconductor layer to form the hetero semiconductor region. The method of manufacturing a semiconductor device according to claim 6, wherein the gate insulating film includes a thermal oxide film formed by at least thermal oxidation. The semiconductor device manufacturing method according to any one of claims 1 to 7, wherein a sacrificial oxidation process is provided between the first process and the second process. The semiconductor device manufacturing method according to any one of claims 1 to 8, wherein the semiconductor substrate is made of silicon carbide. The method of manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the hetero semiconductor region is made of at least one of single crystal silicon, polycrystalline silicon, or amorphous silicon. The semiconductor device manufacturing method according to claim 9 or 10, wherein the mask layer is made of a material having a value close to the thermal oxidation rate of silicon carbide.

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