JP5211472B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device of a field effect transistor having a high breakdown voltage and a low on-resistance, and a manufacturing method thereof.

Conventionally, as this type of technology, for example, those described in the following documents are known (see Patent Document 1). In the technique described in this document, an N ⁻ -type polycrystalline silicon region and a P ⁺ -type region are formed on one main surface of a semiconductor substrate in which an N ⁻ -type epitaxial region is formed on an N ⁺ -type silicon carbide substrate region. The polycrystalline silicon region is formed in contact with the epitaxial region, and the epitaxial region, the N ⁻ type polycrystalline silicon region, and the P ⁺ type polycrystalline silicon region form a heterojunction. A gate electrode is formed adjacent to the junction between the epitaxial region and the N ⁻ -type polycrystalline silicon region via a gate insulating film. The N ⁻ -type polycrystalline silicon region is connected to the source electrode via the N ⁺ -type polycrystalline silicon region, and a drain electrode is formed on the back surface of the N ⁺ -type silicon carbide substrate region to constitute a field effect transistor. Yes.

The field effect transistor configured as described above functions as a switching element by controlling the potential of the gate electrode in a state where the source electrode is grounded and a predetermined positive potential is applied to the drain electrode. That is, in a state where the gate electrode is grounded, a reverse bias is applied to the heterojunction of the N ⁻ type polycrystalline silicon region and the P ⁺ type polycrystalline silicon region and the epitaxial region. At this time, the heterojunction between the P ⁺ type polycrystalline silicon region having high blocking properties and the epitaxial region occupies most, and the heterojunction between the N ⁻ type polycrystalline silicon region acting as a channel and the epitaxial region Is formed so that no current flows between the drain electrode and the source electrode.

On the other hand, when a predetermined positive voltage is applied to the gate electrode, a gate electric field acts on the heterojunction interface between the N ⁻ -type polycrystalline silicon region and the epitaxial region, and the energy formed by the heterojunction surface at the gate oxide film interface. The thickness of the barrier is reduced. Therefore, a current flows from the drain electrode to the source electrode through the epitaxial region, the N ⁻ type polycrystalline silicon region, and the N ⁺ type polycrystalline silicon region.

In this way, in the cut-off state, while having a high cut-off property, when conducting, since the heterojunction is used as the control channel, the channel length functions at the thickness of the hetero-barrier. Characteristics are obtained.
JP-A-2005-101147

However, the conventional structure has a structure in which a P ⁺ type polycrystalline silicon region that maintains a breakdown voltage and an N ⁺ type polycrystalline silicon region that acts as a low resistance region are stacked. Therefore, impurity dopant introduced into polycrystalline silicon region of N ⁺ type in the manufacturing process are diffused into the polycrystalline silicon regions of the P ⁺ type, hetero junction between P ⁺ -type polycrystalline silicon region and the epitaxial region There has been a problem that the withstand voltage of the glass tends to decrease.

On the other hand, a polycrystalline silicon region in which the P ⁺ type polycrystalline silicon region and the N ⁺ type polycrystalline silicon region are combined so that the breakdown voltage of the hetero junction between the P ⁺ type polycrystalline silicon region and the epitaxial region does not decrease. When the layer is formed thick, the selectivity of the mask material when patterning the polycrystalline silicon region layer is limited. In addition, since there is a limit to the controllability when etching the polycrystalline silicon region layer, there is a limit to eliminating the cause of deterioration of the on-resistance due to damage during etching.

  Therefore, the present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device of a field effect transistor that satisfies both a high breakdown voltage and a low on-resistance, and a method for manufacturing the same. .

In order to achieve the above object, means for solving the problems of the present invention is provided on a part of the surface of the semiconductor substrate in contact with one main surface of the semiconductor substrate of the first conductivity type and the semiconductor substrate , A first hetero semiconductor region having a band gap different from that of the semiconductor substrate, and a second conductivity type second electrode having a band gap different from that of the semiconductor substrate in contact with one main surface of the semiconductor substrate and the first hetero semiconductor region. A hetero insulating region, a gate insulating film formed over a portion of the semiconductor substrate that is not covered with the first hetero semiconductor region from the side of the first hetero semiconductor region, and the gate insulating film, A gate electrode in contact therewith, a source electrode ohmically connected to the first hetero semiconductor region, and a drain electrode ohmically connected to the semiconductor substrate. Part of the semiconductor region is stacked on the second hetero semiconductor region, and contact with the gate electrode through at least the gate insulating film, and the surface and the side surface of the second hetero semiconductor region of said semiconductor body The thickness of the channel portion of the first hetero semiconductor region formed in contact with the second hetero semiconductor region in the portion where the second hetero semiconductor region and the first hetero semiconductor region are stacked. And the thickness of the first hetero semiconductor region is thin.

  According to the present invention, the impurity introduced into the first hetero semiconductor region is not diffused at the heterojunction interface between the second hetero semiconductor region and the drain region. In addition to being able to be obtained, etching damage is caused around the heterojunction between the first hetero semiconductor region and the drain region facing the gate electrode through the gate insulating film when forming the first hetero semiconductor region. The process to exclude can be assembled easily. Thereby, a low on-resistance can be obtained when the semiconductor device is conductive.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best embodiment for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device of a field effect transistor (FET) according to Embodiment 1 of the present invention, which is a cross-sectional view in which two structural unit cells face each other. In the embodiments described below, an apparatus using silicon carbide as a substrate material will be described as an example.

In Figure 1, for example N polytype of silicon carbide on the substrate region 1 is a N ⁺ -type 4H type ^- -type drain region 2 is formed of a main opposite the junction surface between the substrate region 1 of the drain region 2 For example, a second hetero semiconductor region 3 made of P ⁺ -type polycrystalline silicon and a first hetero semiconductor region 4 made of N-type polycrystalline silicon are formed so as to contact the surface. That is, the junction between the drain region 2 and the second hetero semiconductor region 3 and the first hetero semiconductor region 4 is formed of a hetero junction made of a material having different band gaps between silicon carbide and polycrystalline silicon. Each has a predetermined energy barrier. A gate insulating film 5 made of, for example, a silicon oxide film is formed so as to be in contact with the junction surface between the first hetero semiconductor region 4 and the drain region 2 together. A gate electrode 6 is formed on the gate insulating film 5 so as to be connected to the first hetero semiconductor region 4, and a source electrode 7 is connected to the substrate region 1 so as to be connected to the drain electrode 8.

  In the first embodiment, the second hetero semiconductor region 3 and the first hetero semiconductor region 4 having a thickness of the channel portion of the first hetero semiconductor region 4 in contact with the gate electrode 6 through the gate insulating film 5 are stacked. It is formed to be smaller than the sum of the thicknesses of the formed portions. In FIG. 1, the case where the thickness of the first hetero semiconductor region 4 is made thinner than the thickness of the second hetero semiconductor region 3 is shown as an example, but it may be the same or thicker. However, the thinner the first hetero semiconductor region 4 is, the easier it is to avoid characteristic deterioration during the manufacturing process described later. Although not shown in FIG. 1, the second hetero semiconductor region 3 and the source electrode 7 may be connected at a predetermined portion in the depth direction, for example.

  Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS.

First, as shown in FIG. 2A, for example, LP-CVD is performed on an N-type silicon carbide semiconductor substrate formed by epitaxially growing an N ⁻ -type drain region 2 on an N ⁺ -type substrate region 1. A second polycrystalline silicon layer formed by the method is formed, and boron is introduced into this layer by, for example, ion implantation, thereby depositing three layers of P ⁺ -type second hetero semiconductor regions.

  At this time, the second polycrystalline silicon layer may be formed by depositing by electron beam evaporation or sputtering and then recrystallizing by laser annealing or the like, or heteroepitaxially grown by, for example, molecular beam epitaxy. It may be formed of single crystal silicon. In addition, solid phase diffusion or vapor phase diffusion may be used for doping. Further, for example, an oxide film is deposited on the second hetero semiconductor region 3 layer, and then a predetermined mask material 9 is formed by photolithography and etching.

Next, as shown in FIG. 2A (b), the P ⁺ -type polycrystalline silicon layer is etched by, for example, reactive ion etching (dry etching) to form the second hetero semiconductor region 3. At this time, a sacrificial oxide film is formed by dry O ₂ oxidation at, for example, about 900 ° C. with or without the mask material, and then sacrificed by wet etching with a mixed solution of ammonium fluoride and hydrofluoric acid, for example. The oxide film may be removed and the etching damage may be recovered by dry etching. As a method for etching the second polycrystalline silicon layer, another etching method may be used as long as it is an anisotropic etching method.

  Next, as shown in FIG. 2A (c), a first multi-layer having a thickness smaller than that of the second hetero semiconductor region 3 is formed on the etched second hetero semiconductor region 3 by, for example, LP-CVD. After the crystalline silicon is deposited, impurities such as phosphorus or arsenic are introduced by ion implantation, for example, to form an N-type first polycrystalline silicon layer. The first polycrystalline silicon layer may be formed by depositing by electron beam evaporation or sputtering and then recrystallizing by laser annealing or the like, or by heteroepitaxial growth using, for example, molecular beam epitaxy. It may be formed of crystalline silicon. In addition, solid phase diffusion or vapor phase diffusion may be used for doping.

At this time, in Example 1, the thickness of the second hetero semiconductor region 3 is set such that the impurity introduced into the first hetero semiconductor region 4 is at least a heterojunction between the second hetero semiconductor region 3 and the drain region 2. Since the thickness is formed so as not to reach the interface, at least the heterojunction interface between the P ⁺ -type second hetero semiconductor region 3 and the drain region 2 has a predetermined breakdown voltage determined by the work function difference between the two. be able to.

  Further, a predetermined mask material 10 is formed on the first hetero semiconductor region 4 layer by photolithography and etching.

Next, as shown in FIG. 2B (d), since the thickness of the first hetero semiconductor region 4 is made thinner than the thickness of the second hetero semiconductor region 3 in Example 1, dry etching is performed. Control becomes easy, for example, the surface layer portion of a predetermined region of the first polycrystalline silicon layer is etched by dry etching, and after the resist mask is removed, the predetermined region of the remaining first polycrystalline silicon layer is changed to, for example, 900 ° C. The first hetero semiconductor region 4 can be formed by oxidizing with dry O ₂ oxidation and performing wet etching with a mixed solution of ammonium fluoride and hydrofluoric acid. In addition, patterning by thermal oxidation using a combination of dry etching and sacrificial oxidation or a mask such as an oxide film is also possible.

Finally, a gate insulating film 5 is deposited along the inner walls of the first hetero semiconductor region 4 and the drain region 2 as shown in FIG. Further, a polycrystalline silicon layer to be the gate electrode 6 is deposited. Thereafter, phosphorus is doped into the polycrystalline silicon layer to be the gate electrode 6 by solid layer diffusion using, for example, POCl ₃ . Then, after forming the gate electrode 6 by photolithography, etching, or the like, the drain electrode 8 made of, for example, titanium (Ti) or nickel (Ni) is formed in the substrate region 1 corresponding to the back surface side, and corresponds to the front surface side. A source electrode 7 is formed by sequentially depositing titanium (Ti) and aluminum (Al) so as to be connected to the first hetero semiconductor region 4, and the semiconductor device of Example 1 shown in FIG. 1 is completed.

  As described above, the semiconductor device according to the first embodiment can be easily realized by a conventional manufacturing technique. In the first embodiment, the impurity introduced into the first hetero semiconductor region 4 does not diffuse at the heterojunction interface between the second hetero semiconductor region 3 and the drain region 2, and a predetermined breakdown voltage is obtained in the cutoff state. At the same time, when the first hetero semiconductor region 4 is formed, around the heterojunction between the first hetero semiconductor region 4 and the drain region 2 facing the gate electrode 6 through the gate insulating film 5. Since a process of eliminating etching damage can be easily adopted, a low on-resistance can be obtained when the FET is conductive.

  Next, the operation of the FET having the structure manufactured in the above manufacturing process will be described.

  In the first embodiment, for example, the source electrode 7 is grounded and a positive potential is applied to the drain electrode 8 for use. First, when the gate electrode 6 is set to a ground potential or a negative potential, for example, the cutoff state is maintained. This is because energy barriers for conduction electrons are formed at the heterojunction interfaces between the first hetero semiconductor region 4 and the second hetero semiconductor region 3 and the drain region 2. At this time, since both the first hetero semiconductor region 4 and the second hetero semiconductor region 3 are made of a silicon material, the energy barrier difference ΔEc with the drain region 2 made of silicon carbide is substantially the same. However, since there is a difference in the Fermi energy indicated by the energy from the conduction band to the Fermi level, the first hetero semiconductor region 4 that is N-type and the second hetero semiconductor region 3 that is P-type have different drain regions. The width of the depletion layer extending to the junction interface between the two hetero semiconductor regions 3 is different, and the width of the depletion layer extending from the junction interface with the second hetero semiconductor region 3 is larger than the width of the depletion layer extending from the junction interface with the first hetero semiconductor region 4. Become.

At this time, in the prior art, the P ⁺ type polycrystalline silicon region that maintains the withstand voltage and the N ⁺ type polycrystalline silicon region that acts as a low resistance region are simply stacked. and impurity dopants for forming a polycrystalline silicon region of N ⁺ type is diffused into the polycrystalline silicon regions of P ⁺ type, the breakdown voltage of the heterojunction between the P ⁺ -type polycrystalline silicon region and the epitaxial region was easy decreased .

On the other hand, in the first embodiment, since the thickness of the second hetero semiconductor region 3 is thicker than the diffusion length of the impurity introduced into the first hetero semiconductor region 4, at least the P ⁺ type is formed. At the heterojunction interface between the second hetero semiconductor region 3 and the drain region 2, a predetermined breakdown voltage determined by the work function difference between them can be obtained. Further, by increasing the width of the junction between the second hetero semiconductor region 3 and the drain region 2 as compared with the junction between the first hetero semiconductor region 4 and the drain region 2, a higher blocking property, that is, a lower leakage current is obtained. Characteristics can be realized.

In the present embodiment, the second hetero semiconductor region 3 is described as a P ⁺ type having a conductivity type different from that of the first hetero semiconductor region 4 so that the withstand voltage can be maximized. The hetero semiconductor region 3 may be N-type or may not have impurities introduced therein. That is, the first hetero semiconductor region 4 and the second hetero semiconductor region 3 do not have to be separate regions, and may exist as one “hetero semiconductor region” in which these regions are integrated.

  Next, when a positive potential is applied to the gate electrode 6 so as to shift from the cut-off state to the conductive state, the gate electric field is reached through the gate insulating film 5 to the heterojunction interface where the first hetero semiconductor region 4 and the drain region 2 are in contact. Therefore, an accumulation layer of conduction electrons is formed in the first hetero semiconductor region 4 and the drain region 2 in the vicinity of the gate electrode 6. That is, the potential on the first hetero semiconductor region 3 side at the junction interface between the first hetero semiconductor region 3 and the drain region 2 in the vicinity of the gate electrode 6 is pushed down, and the energy barrier on the drain region 2 side becomes steep. Conduction electrons can be conducted through the energy barrier.

  At this time, in Example 1, since the thickness of the first hetero semiconductor region 4 is thin, the selectivity of the mask material is not hindered, and at the same time, the control of the etching depth of the dry etching is facilitated. A method combining dry etching and thermal oxidation, or patterning using only thermal oxidation is also possible. For this reason, it is possible to avoid deterioration of on-resistance caused by dry etching or the like, and to obtain good on-resistance.

  Next, when the gate electrode 6 is again set to the ground potential in order to shift from the conductive state to the cut-off state, the accumulated state of the conduction electrons formed at the heterojunction interface of the first hetero semiconductor region 4 and the drain region 2 is released. And tunneling in the energy barrier stops. When the flow of conduction electrons from the first hetero semiconductor region 4 to the drain region 2 stops and the conduction electrons in the drain region 2 flow to the substrate region 1 and are exhausted, a heterojunction portion is formed on the drain region 2 side. As a result, the depletion layer spreads and becomes a cutoff state.

  On the other hand, in the first embodiment, as in the conventional structure, for example, reverse conduction (reflux operation) in which the source electrode 7 is grounded and a negative potential is applied to the drain electrode 8 is also possible. For example, when the source electrode 7 and the gate electrode 6 are set to the ground potential and a predetermined positive potential is applied to the drain electrode 8, the energy barrier against the conduction electrons disappears, and the first hetero semiconductor region 4 and the first hetero semiconductor region 4 from the drain region 2 side. Conduction electrons flow to the side of the second hetero semiconductor region 3 and enter a reverse conducting state. At this time, since there is no injection of holes and conduction is performed only with conduction electrons, loss due to reverse recovery current when shifting from the reverse conduction state to the cutoff state is small. The gate electrode 6 described above can be used as a control electrode without being grounded.

  Furthermore, since the first hetero semiconductor region 4 is formed of a polycrystalline silicon layer different from the second hetero semiconductor region 3, the conductivity type and concentration of the impurity can be freely set, so that the design flexibility is increased. improves.

  FIG. 3 is a cross-sectional view illustrating a configuration of a field effect transistor (FET) semiconductor device according to a second embodiment of the present invention. In FIG. 3, the feature of the second embodiment is that, in addition to the structure of the first embodiment shown in FIG. 1, the gate electrode 6 and the first hetero semiconductor region 4 are separated from each other by a predetermined distance. In addition, the electric field relaxation region 11 is formed on the surface of the drain region 2 so as to be in contact with the first hetero semiconductor region 4 or the second hetero semiconductor region 3, and the others are the same as in FIG.

  Hereinafter, an example of a manufacturing method for obtaining the structure shown in FIG. 3 will be described.

  In FIG. 2A, for example, before the first polycrystalline silicon layer 3 is formed, the electric field relaxation region 11 is formed by ion implantation of aluminum ions or boron ions through a mask layer having a predetermined opening. To do. It may be formed by solid phase diffusion. The subsequent steps are the same as the steps shown in FIG.

  With this configuration, a depletion layer corresponding to the drain potential expands between the electric field relaxation region 11 and the drain region 2 in the cutoff state. That is, since the drain electric field applied to the heterojunction interface between the first hetero semiconductor region 4 and the second hetero semiconductor region 3 and the drain region 2 is relaxed by the electric field relaxation region 11, the leakage current is further reduced. Further, the blocking performance is further improved.

FIG. 4 is a cross-sectional view showing the configuration of a field effect transistor (FET) semiconductor device according to Embodiment 3 of the present invention. In FIG. 4, this embodiment 3 is characterized by a predetermined portion of the drain region 2 where the gate insulating film 5 and the first hetero semiconductor region 4 are in contact with the structure of the embodiment 2 shown in FIG. In addition, the N ⁺ type conductive region 12 having a higher concentration than the drain region 2 is formed, and the others are the same as in FIG.

  Hereinafter, an example of a manufacturing method for obtaining the structure shown in FIG. 4 will be described. Like the structure shown in FIG. 3, from the state of FIG. 2A, for example, before forming the first polycrystalline silicon layer 3, aluminum ions or boron ions are passed through a mask layer having a predetermined opening. Are implanted to form the electric field relaxation region 11. Thereafter, nitrogen ions or phosphorus ions are introduced through a predetermined mask to form the conduction region 12. Note that the electric field relaxation region 11 and the conductive region 12 may be formed in any order first. The subsequent steps are the same as the steps shown in FIG.

  With this configuration, in the conductive state, the energy barrier at the heterojunction between the first hetero semiconductor region 4 and the conductive region 12 is relaxed, and higher conductive characteristics can be obtained. That is, the on-resistance is further reduced, and the conduction performance is improved.

  In the cut-off state, a depletion layer corresponding to the drain potential spreads between the electric field relaxation region 11 and the drain region 2. That is, since the drain electric field applied to the heterojunction interface between the first hetero semiconductor region 3 and the second hetero semiconductor region 4 and the drain region 2 is relaxed by the electric field relaxation region 11, the leakage current is further reduced. Further, the blocking performance is further improved.

  In addition, in this structure, although the case where the electric field relaxation area | region 11 and the conduction | electrical_connection area | region 12 are formed together is illustrated, only the conduction | electrical_connection area | region 12 may be formed.

  FIG. 5 is a cross-sectional view showing a configuration of a field effect transistor (FET) semiconductor device according to Embodiment 4 of the present invention. In the first embodiment shown in FIG. 1, the so-called planar type structure in which no groove is formed in the drain region 2 is adopted, but the feature of the fourth embodiment is that as shown in FIG. The trench region is formed in the surface layer portion of the drain region 2 and the gate electrode 6 is formed in the trench via the gate insulating film 5. .

  In the structure shown in FIG. 5, when the first polycrystalline silicon layer 4 (see FIG. 2 (d)) is etched by, for example, reactive ion etching, the surface layer portion of the drain region 2 is also etched to form a trench structure. To do. The subsequent steps are the same as the steps in FIG.

  FIG. 6 is a cross-sectional view showing a configuration of a field effect transistor (FET) semiconductor device according to Embodiment 5 of the present invention. In FIG. 6, the feature of the fifth embodiment is that the second embodiment shown in FIG. 3 and the fourth embodiment shown in FIG. 5 are combined. The manufacturing method for obtaining such a configuration can be manufactured by carrying out the manufacturing steps used in Examples 2 and 4 together. By adopting such a configuration, it is possible to obtain the effects obtained in both the second and fourth embodiments.

  FIG. 7 is a sectional view showing a configuration of a field effect transistor (FET) semiconductor device according to Embodiment 6 of the present invention. In FIG. 7, the feature of the sixth embodiment is that the third embodiment shown in FIG. 4 and the fourth embodiment shown in FIG. The manufacturing method for obtaining such a configuration can be manufactured by carrying out the manufacturing steps used in Examples 3 and 4 together. By adopting such a configuration, it is possible to obtain the effects obtained in both the second and fourth embodiments.

  FIG. 8 is a cross-sectional view showing a configuration of a field effect transistor (FET) semiconductor device according to Embodiment 7 of the present invention. In FIG. 8, the feature of the seventh embodiment is that the first hetero semiconductor region 4 shown in FIG. 1 is different from the first embodiment shown in FIG. The channel portion 13 of the first hetero semiconductor region 4 in contact with the gate electrode 6 through the drain region 2 and the gate insulating film 5 is P-type, and the source electrode contact portion of the first hetero semiconductor region 4 in contact with the source electrode 7 14 is N-type, so-called inversion channel configuration, and the others are the same as in FIG.

  Hereinafter, an example of a manufacturing method of this structure will be described. In FIG. 2C, for example, after the first polycrystalline silicon layer 3 is formed, boron ions are ion-implanted through a mask layer having a predetermined opening to form the channel portion 13. Further, arsenic ions or phosphorus ions are ion-implanted using a mask layer having another predetermined opening to form the source electrode contact portion 14. Each region may use solid phase diffusion or gas phase diffusion. The subsequent steps are the same as the steps shown in FIG.

  By adopting such a configuration, in the cutoff state of the FET, since the channel portion 13 is configured as a P-type, higher blocking performance can be obtained as compared with the case where it is configured as an N-type. .

  8 illustrates the configuration corresponding to FIG. 1 by way of example, but the configuration shown in FIGS. 3 to 7 can also be implemented.

  FIG. 9 is a sectional view showing the structure of a field effect transistor (FET) semiconductor device according to Example 8 of the present invention. Here, a different part from Example 1 shown in FIG. 1 is demonstrated in detail.

  In the first embodiment, the second hetero semiconductor region 3 and the source electrode 7 are connected to each other at a predetermined portion in the depth direction of the drawing, for example. Compared to the structure of 1, the source electrode 7 and the second hetero semiconductor region 3 are connected in the cell portion as shown in FIG. Hereinafter, an example of a manufacturing method for obtaining the structure of the eighth embodiment will be described with reference to FIG.

  After going through the same steps up to the previous FIG. 2B, as shown in FIG. 10A, on the second hetero semiconductor region 3 etched in the same manner as in Example 1, for example, LP-CVD method. After depositing the first polycrystalline silicon having a thickness smaller than that of the second hetero semiconductor region 3, phosphorus or arsenic is introduced by, for example, ion implantation to form an N-type first polycrystalline silicon layer. To do. Subsequently, a mask material 10 in which a predetermined position of the first hetero semiconductor region 4 layer on the second hetero semiconductor region 3 is exposed (no pattern) is formed by photolithography and etching.

Next, as shown in FIG. 10B, the mask material 10 is used to etch the surface layer portion of a predetermined region of the first polycrystalline silicon layer, for example, by dry etching, and the mask material 10 is removed and remains. A predetermined region of the first polycrystalline silicon layer is oxidized by dry O ₂ oxidation at about 900 ° C., for example, and wet-etched with a mixed solution of ammonium fluoride and hydrofluoric acid, whereby the first hetero semiconductor region 4 is formed. Form. At this time, a part of the surface layer portion (location where the source electrode is joined) of the second hetero semiconductor region 3 is exposed.

Finally, as shown in FIG. 10C, a gate insulating film 5 is deposited along the inner walls of the first hetero semiconductor region 4 and the drain region 2. Subsequently, a polycrystalline silicon layer to be the gate electrode 6 is deposited. Thereafter, phosphorus is doped into the polycrystalline silicon layer to be the gate electrode 6 by solid layer diffusion using, for example, POCl ₃ . Then, after forming the gate electrode 6 by photolithography, etching, or the like, a drain electrode 8 made of, for example, titanium (Ti) or nickel (Ni) is formed in the substrate region 1 corresponding to the back side, and corresponds to the front side. The source electrode 7 is formed by sequentially depositing titanium (Ti) and aluminum (Al) so as to be connected to the first hetero semiconductor region 4 and the second hetero semiconductor region 3, and the implementation shown in FIG. The semiconductor device according to Example 8 is completed.

  By adopting such a configuration, the potential of the second hetero semiconductor region 3 can be made substantially equal to the potential of the source electrode 7 without unevenness for each cell, so that a stable breakdown voltage can be obtained in the cutoff state of the FET. . In addition, since the depletion layer extending from the second hetero semiconductor region 3 tends to extend uniformly when shifting from the conductive state to the cut-off state, it is possible to avoid a current bias for each cell, so that breakdown during transients can be avoided. It becomes possible to improve the tolerance.

  In reverse conduction (reflux operation), when a predetermined positive potential is applied to the drain electrode 8, the energy barrier to the conduction electrons disappears, and the first hetero semiconductor region 4 and the first hetero semiconductor region 4 from the drain region 2 side. Conduction electrons flow to the side of the second hetero semiconductor region 3 and enter a reverse conducting state. At this time, since the second hetero semiconductor region 3 is connected to the source electrode 7 with a low resistance, it can conduct with a low on-resistance.

  In the eighth embodiment, although not shown, it can be carried out together with the embodiments shown in FIGS.

  FIG. 11 is a cross-sectional view showing a configuration of a field effect transistor (FET) semiconductor device according to Embodiment 9 of the present invention. Here, a different part from Example 1 shown in FIG. 1 is demonstrated in detail.

  In the first embodiment shown in FIG. 1, the second hetero semiconductor region 3 is formed on one main surface of the drain region 2, whereas the feature of the ninth embodiment is that the drain region A groove is formed in a predetermined region 22 and the second hetero semiconductor region 23 is formed so as to be in contact with the bottom of the groove. Although FIG. 11 shows the case where the second hetero semiconductor region 23 is buried in the groove, it may protrude from the groove or may be recessed.

  Hereinafter, an example of a manufacturing method for obtaining the structure of the ninth embodiment will be described with reference to process cross-sectional views of FIGS. 12-A, 12-B, and 12-C.

First, as shown in FIG. 12A (a), a predetermined material is formed on an N-type silicon carbide semiconductor substrate formed by epitaxially growing an N ⁻ -type drain region 22 on an N ⁺ -type substrate region 21. The mask material 29 made of is patterned. The mask material 29 may be any mask material that can be selectively etched in the next step, such as an oxide film, SiN film, metal mask, or resist mask.

Next, as shown in FIG. 12A (b), along the pattern of the mask material 29 formed in FIG. 12A, for example, by reactive ion etching (dry etching), a predetermined region of the drain region 22 is formed. Grooves are formed. At this time, in a state where the mask material 29 is provided or removed, sacrificial oxidation is performed by dry O ₂ oxidation, for example, at about 1100 ° C. Etching damage recovery by dry etching may be performed. As a method for etching the drain region 22, another etching method may be used as long as it is an anisotropic etching method.

Next, as shown in FIG. 12-A (c), the second polycrystalline silicon layer 23 is formed by, for example, LP-CVD, and boron is introduced by, for example, ion implantation, so that P ⁺ -type can be obtained. A second hetero semiconductor region 23 layer is deposited. At this time, the second polycrystalline silicon layer 23 is formed by recrystallization by laser annealing or the like after being deposited by electron beam evaporation or sputtering, or by heteroepitaxial growth by, for example, molecular beam epitaxy or the like. It may be formed of silicon. In addition, solid phase diffusion or vapor phase diffusion may be used for doping.

Next, as shown in FIG. 12B (d), the P ⁺ type polycrystalline silicon layer is etched back by, for example, reactive ion etching (dry etching) to form the second hetero semiconductor region 23. At this time, for example, a material that can be planarized may be formed in advance before etching back the P ⁺ -type polycrystalline silicon layer so that the planar etching can be performed. In addition, as long as the process can be planarized, another method such as a CMP process may be used.

  Next, as shown in FIG. 12B (e), the thickness of the etched second hetero semiconductor region 23 and drain region 22 is thinner than that of the second hetero semiconductor region 23 by, for example, LP-CVD. After the first polycrystalline silicon is deposited, phosphorus or arsenic is introduced by, for example, ion implantation to form an N-type first polycrystalline silicon layer that becomes the first hetero semiconductor region 24.

The first polycrystalline silicon layer is formed of single crystal silicon deposited by electron beam evaporation or sputtering and then recrystallized by laser annealing or the like, or heteroepitaxially grown by, for example, molecular beam epitaxy. It may be formed. In addition, solid phase diffusion or vapor phase diffusion may be used for doping. At this time, the thickness of the second hetero semiconductor region 23 is set so that the impurity introduced into the first hetero semiconductor region 24 reaches at least the heterojunction interface between the second hetero semiconductor region 23 and the bottom of the drain region 22. Therefore, at least at the heterojunction interface between the P ⁺ -type second hetero semiconductor region 23 and the drain region 22, a predetermined breakdown voltage determined by the work function difference between them can be obtained.

  Subsequently, a predetermined mask material 30 is formed on the first hetero semiconductor region 24 layer by photolithography and etching.

Next, as shown in FIG. 12B (f), since the thickness of the first hetero semiconductor region 24 is made thinner than the thickness of the second hetero semiconductor region 23, the dry etching can be easily controlled. For example, a surface layer portion of a predetermined region of the first polycrystalline silicon layer is etched through a resist mask by dry etching, and then the resist mask is removed. The first hetero semiconductor region 24 is formed by oxidation by dry O ₂ oxidation at ° C. and wet etching with a mixed solution of ammonium fluoride and hydrofluoric acid. In addition, patterning by thermal oxidation using a method such as a combination of dry etching and sacrificial oxidation or a mask such as an oxide film is also possible.

Finally, as shown in FIG. 12C (g), a gate insulating film 25 is deposited along the surfaces of the first hetero semiconductor region 24 and the drain region 22. Subsequently, after a polycrystalline silicon layer to be the gate electrode 26 is deposited, phosphorus is doped into the polycrystalline silicon layer to be the gate electrode 26 by solid layer diffusion using, for example, POCl ₃ . Then, after forming the gate electrode 26 by photolithography, etching, or the like, a drain electrode 28 made of, for example, titanium (Ti) or nickel (Ni) is formed in the substrate region 1 corresponding to the back surface side, and corresponds to the front surface side. A source electrode 27 is formed by sequentially depositing titanium (Ti) and aluminum (Al) so as to be connected to the first hetero semiconductor region 24 to complete the semiconductor device of Example 9 shown in FIG. .

  As described above, the semiconductor device of the ninth embodiment can be easily realized by a conventional manufacturing technique as in the first embodiment. Further, since the heterojunction interface between the second hetero semiconductor region 23 and the drain region 22 is formed at a position deeper than the channel portion where the first hetero semiconductor region 24, the drain region 22, and the gate insulating film 25 are in contact with each other. In the cut-off state, higher breakdown voltage can be obtained. In addition, since the first hetero semiconductor region 24 serving as a current path can be formed in a flat shape as compared with the first embodiment when conducting, the stress concentration of the film itself due to the thermal stress caused by the current concentration. Can be mitigated and reliability can be improved.

  Although the configuration of the ninth embodiment has been described by taking the configuration shown in FIG. 11 as an example, it may be implemented in combination with the features adopted in the above-described embodiment, for example, the embodiment described below. The configuration of the tenth to the fourteenth embodiment is also possible.

FIG. 13 is a cross-sectional view showing a configuration of a field effect transistor (FET) semiconductor device according to Example 10 of the present invention. In FIG. 13, the feature of the tenth embodiment is that, in comparison with the ninth embodiment shown in FIG. 11, a drain region is formed in a predetermined portion of the drain region 22 in contact with the gate insulating film 25 and the first hetero semiconductor region 24. The P ⁺ -type conductive region 31 having a concentration higher than 22 is formed, and the others are the same as in FIG.

  Hereinafter, an example of the manufacturing method of this structure is demonstrated. First, from the state shown in FIG. 12-A (a), before forming the mask material 29, for example, nitrogen ions or phosphorus ions are introduced in a state having a predetermined mask different from the mask material 29, and a conduction region is formed. 31 is formed. The subsequent steps are the same as those shown in FIG.

  With such a configuration, in the FET conduction state, the energy barrier of the heterojunction between the first hetero semiconductor region 24 and the conduction region 31 is relaxed, and higher conduction characteristics can be obtained. That is, the on-resistance is further reduced and the conduction performance is improved.

  FIG. 14 is a cross-sectional view showing a configuration of a field effect transistor (FET) semiconductor device according to Example 11 of the present invention. In the structure shown in FIG. 11, the gate electrode 26 has a so-called planar configuration in which no groove is formed in the drain region 22, whereas the feature of the eleventh embodiment is that This is because a so-called trench type structure in which a groove is formed in the surface layer portion of the region 22 and a gate electrode 26 is formed in the groove via a gate insulating film 25 is employed.

  The groove is formed by simultaneously etching the surface layer portion of the drain region 22 when the first polycrystalline silicon layer 24 is etched by, for example, reactive ion etching in the step shown in FIG. To do. The subsequent steps are the same as those shown in FIG.

  FIG. 15 is a sectional view showing the structure of a field effect transistor (FET) semiconductor device according to Embodiment 12 of the present invention. In the configuration shown in FIG. 11, the first hetero semiconductor region 24 is formed in the N-type, whereas the feature of the embodiment 12 is that the drain region 22 and the gate insulating film 25 are interposed. The channel portion 32 of the first hetero semiconductor region 24 in contact with the gate electrode 26 is formed in P type, and the source electrode contact portion 33 of the first hetero semiconductor region 24 in contact with the source electrode 27 is formed in N type. The other is the same as in FIG. 11, except that an inverted channel configuration is employed.

  Hereinafter, an example of the manufacturing method of this structure is demonstrated. In FIG. 12-B (e), for example, after forming a first polycrystalline silicon layer, boron ions are ion-implanted through a mask layer having a predetermined opening to form a channel portion 32. Subsequently, arsenic ions or phosphorus ions are implanted through a mask layer having another predetermined opening to form the source electrode contact portion 33. Each region may use solid phase diffusion or gas phase diffusion. The subsequent steps are the same as the steps shown in FIG.

  By adopting such a configuration, in the FET cutoff state, since the channel portion 32 is configured as a P-type, higher blocking performance can be obtained as compared with the case where it is configured as an N-type.

  In FIG. 15, the configuration corresponding to FIG. 11 is described as an example. However, the inverted channel can be similarly applied to the configurations illustrated in FIGS. 13 and 14.

  FIG. 16 is a sectional view showing the structure of a field effect transistor (FET) semiconductor device according to Embodiment 13 of the present invention. In the configuration shown in FIG. 11, the second hetero semiconductor region 23 and the source electrode 27 are connected at a predetermined portion in the depth direction, for example. In the cell portion, the source electrode 27 and the second hetero semiconductor region 23 are connected, and the others are the same as in FIG.

  As a manufacturing method of such a configuration, in FIG. 12-B (f), after forming the N-type first polycrystalline silicon layer, the second hetero semiconductor region 23 is formed by photolithography and etching. The step of forming a mask material in which a predetermined position of the first hetero semiconductor region 24 is exposed and selectively etching the first polycrystalline silicon layer through this mask material is the same as the manufacturing step of the previous Example 8. It can be easily realized by implementing together.

  By adopting such a configuration, the potential of the second hetero semiconductor region 23 can be made substantially equal to the potential of the source electrode 27 without unevenness for each cell, so that a stable breakdown voltage can be obtained in the cutoff state of the FET. . Further, when shifting from the conductive state to the cutoff state, the depletion layer extending from the second hetero semiconductor region 23 is likely to extend uniformly, so that it is possible to avoid current bias for each cell. Thereby, it becomes possible to improve the breakdown tolerance at the time of transition.

  Further, during reverse conduction (recirculation operation), when a predetermined positive potential is applied to the drain electrode 28, the energy barrier against the conduction electrons disappears, and the first hetero semiconductor region 24 and the first hetero semiconductor region 24 from the drain region 22 side. Conduction electrons flow to the second hetero semiconductor region 23 side, and a reverse conduction state is established. At this time, since the second hetero semiconductor region 23 is connected to the source electrode 27 with low resistance, it is possible to conduct with low on-resistance.

  Although not shown in the thirteenth embodiment, it can be implemented in combination with the configuration of the electric field relaxation region, the conduction region, and the inversion channel shown in the previous embodiment.

  FIG. 17 is a cross-sectional view showing a configuration of a field effect transistor (FET) semiconductor device according to Embodiment 14 of the present invention. The feature of the fourteenth embodiment is that, corresponding to the structure of the thirteenth embodiment shown in FIG. 16, a groove is formed in the surface layer portion of the drain region 22, and the gate insulating film 25 is interposed in the groove. This is because a so-called trench-type configuration in which the gate electrode 26 is formed is employed, and the others are the same as those in FIG. The manufacturing method having such a configuration can be easily implemented by adding the step of forming the groove previously mentioned to the step shown in FIG.

As described above, in the present embodiment described in Examples 1 to 14, the second hetero semiconductor region 3 (23) is a P ⁺ type having a conductivity type different from that of the first hetero semiconductor region 4 (24). However, the second hetero semiconductor region 3 is not limited to the P ⁺ type, and even if the impurity density is low, the impurities can be further improved. May not be introduced. In other words, the first hetero semiconductor region 4 (24) and the second hetero semiconductor region 3 (23) do not necessarily have to be separate regions, and exist as one “hetero semiconductor region” in which these regions are integrated. You may do it.

  FIG. 18 is a cross-sectional view showing a configuration of a field effect transistor (FET) semiconductor device according to Embodiment 15 of the present invention. A feature of the fifteenth embodiment is that the width of the portion of the first hetero semiconductor region 4 protruding from the second hetero semiconductor region 3 is uniformly formed in a self-aligned manner. Is the same as in the first embodiment.

  Next, a manufacturing method for obtaining the structure of the fifteenth embodiment will be described with reference to FIGS. 19A to 19C.

First, as shown in FIG. 19A, for example, LP-CVD is performed on an N-type silicon carbide semiconductor substrate formed by epitaxially growing an N ⁻ -type drain region 2 on an N ⁺ -type substrate region 1. A second polycrystalline silicon layer is formed by the method, and boron is introduced into this layer by, for example, an ion implantation method, thereby depositing and forming a semiconductor layer to be the P ⁺ -type second hetero semiconductor region 3.

  At this time, the second polycrystalline silicon layer may be formed by depositing by electron beam evaporation or sputtering and then recrystallizing by laser annealing or the like, or heteroepitaxially grown by, for example, molecular beam epitaxy. It may be formed of single crystal silicon. In addition, solid phase diffusion or vapor phase diffusion may be used for doping.

  Next, as shown in FIG. 19A (b), a conductive region 41 is formed on the second hetero semiconductor region 3. The conductive region 41 has a function of connecting the first hetero semiconductor region 4 to be formed later and the source electrode 7. The conductive region 41 may be formed by implanting an N-type impurity into the second hetero semiconductor region 3, or after introducing polycrystalline silicon or the like on the second hetero semiconductor region 3, the N-type impurity is introduced. Alternatively, N-type polycrystalline silicon or the like may be directly deposited on the second hetero semiconductor region 3. Subsequently, after depositing, for example, an oxide film on the conductive layer 41, a predetermined mask material 42 is formed by photolithography and etching.

Next, as shown in FIG. 19A (c), the conductive layer 41 and the semiconductor layer of the second hetero semiconductor region 3 are selectively formed by, for example, reactive ion etching (dry etching) using the mask material 42 as a mask. Etch and pattern. After that, a sacrificial oxide film is formed by dry O ₂ oxidation at, for example, about 900 ° C. with the mask material 42 left or removed, and then wet with, for example, a mixed solution of ammonium fluoride and hydrofluoric acid. Etching damage may be recovered by the previous dry etching by removing the sacrificial oxide film by etching. As a method for etching the second polycrystalline silicon layer, another etching method may be used as long as it is an anisotropic etching method.

  Next, as shown in FIG. 19B (d), the mask material 42 is removed, and the second hetero semiconductor is formed on the patterned conductive layer 41 and the second hetero semiconductor region 3 by, for example, LP-CVD. After the first polycrystalline silicon having a thickness smaller than that of the region 3 is deposited, phosphorus or arsenic is introduced by, for example, ion implantation to introduce an N-type first polycrystalline silicon layer (first hetero semiconductor region 4 ). The first polycrystalline silicon layer may be formed by depositing by electron beam evaporation or sputtering and then recrystallizing by laser annealing or the like, or heteroepitaxially grown by, for example, molecular beam epitaxy. It may be formed of single crystal silicon. In addition, solid phase diffusion or vapor phase diffusion may be used for doping.

At this time, in Example 15, the thickness of the second hetero semiconductor region 3 is set so that the impurity introduced into the first hetero semiconductor region 4 is at least a heterojunction between the second hetero semiconductor region 3 and the drain region 2. Since the thickness is formed so as not to reach the interface, at least the heterojunction interface between the P ⁺ -type second hetero semiconductor region 3 and the drain region 2 has a predetermined breakdown voltage determined by the work function difference between the two. be able to.

  Next, as shown in FIG. 19B (e), a mask material 43 is isotropically deposited on the semiconductor layer of the first hetero semiconductor region 4. As the mask material 43, for example, a silicon oxide film, a silicon nitride film, or the like can be used, and as a deposition method, CVD or the like can be used.

  Next, as shown in FIG. 19B (f), the mask material 43 is selectively etched away by anisotropically etching the mask material 43 using reactive ion etching (RIE) or the like. A sidewall mask 44 is formed.

  Next, as shown in FIG. 19C (g), the semiconductor layer of the first hetero semiconductor region 4 is selectively etched away using the sidewall mask 44 as a mask. As an etching method, dry etching, sacrificial oxidation, oxide film removal by hydrofluoric acid, or a combination of these can be used.

  Next, as shown in FIG. 19C (h), the sidewall mask 44 is removed. When the sidewall mask 44 is removed, the width d1 of the portion where the first hetero semiconductor region 4 protrudes laterally from the second hetero semiconductor region 3 is self-aligned by the width of the sidewall mask 44 as shown in FIG. Stipulated in For this reason, the width d1 of the portion where the first hetero semiconductor region 4 protrudes from the second hetero semiconductor region 3 can be uniformly formed regardless of the alignment of photolithography. As a result, the resistance value of the protruding portion of the first hetero semiconductor region 4 becomes uniform, so that a semiconductor device with little characteristic variation can be provided.

  Finally, as shown in FIG. 19C (i), the semiconductor device having the structure shown in FIG. 18 is completed through the same steps as those shown in FIG. 2-B (e) of the first embodiment.

  FIG. 20 is a cross-sectional view showing a configuration of a field effect transistor (FET) semiconductor device according to Embodiment 16 of the present invention. The feature of the sixteenth embodiment is that the width of the portion of the first hetero semiconductor region 4 protruding from the second hetero semiconductor region 3 is uniformly formed in a self-aligned manner. Is the same as in the first embodiment.

  Next, a manufacturing method for obtaining the structure of the sixteenth embodiment will be described with reference to FIGS.

First, as shown in FIG. 21-A (a), on an N type silicon carbide semiconductor substrate formed by epitaxially growing an N ⁻ type drain region 2 on an N ⁺ type substrate region 1, for example, LP− A second polycrystalline silicon layer is formed by a CVD method, and boron is introduced into this layer by, for example, an ion implantation method, thereby depositing and forming a semiconductor layer of the P ⁺ -type second hetero semiconductor region 3.

  At this time, the second polycrystalline silicon layer may be formed by depositing by electron beam evaporation or sputtering and then recrystallizing by laser annealing or the like, or heteroepitaxially grown by, for example, molecular beam epitaxy. It may be formed of single crystal silicon. In addition, solid phase diffusion or vapor phase diffusion may be used for doping.

  Next, as shown in FIG. 21A (b), a predetermined mask material 42 is formed on the semiconductor layer of the second hetero semiconductor region 3. The mask material 42 may be a resist patterned by photolithography, or an oxide film mask formed by photolithography and etching after depositing an oxide film.

  Next, as shown in FIG. 21A (c), the first amorphous region 47 is formed by introducing impurities 46 using the mask material 42 as a mask. The impurity 46 may be any material that makes the semiconductor layer of the second hetero semiconductor region 3 amorphous. For example, argon may be used. As the introduction method, ion implantation or the like can be used.

  Next, as shown in FIG. 21B (d), the mask material 42 is etched by using wet etching, isotropic dry etching, or the like, and is moved back in the lateral direction, whereby the impurities 46 are removed in the previous step. The area of the opening of the mask material 42 is expanded more than when it is introduced.

  Next, as shown in FIG. 21B (e), a second amorphous region 49 is formed by introducing an impurity 48 using the mask material 42 as a mask. The impurity 48 may be any impurity that makes the semiconductor layer of the second hetero semiconductor region 3 amorphous. For example, argon may be used. As the introduction method, ion implantation or the like can be used. At this time, by adjusting the ion implantation energy so that the projected range of the impurity 48 is shallower than the projected range of the impurity 46, the first and second amorphous materials as shown in FIG. An amorphous region made of a material region can be formed.

  Next, after removing the mask material 42, sacrificial oxidation is performed. In this oxidation treatment, the oxidation rate of the amorphous region composed of the first amorphous layer region 47 and the second amorphous region 49 is faster than that of the semiconductor layer of the second hetero semiconductor region 3. The amorphous region is selectively oxidized faster than the second hetero semiconductor region 3.

  Next, as shown in FIG. 21B (f), the oxide film formed in the previous step is removed by wet etching using hydrofluoric acid or the like. As a result, the second hetero semiconductor region 3 having a shape as shown in FIG. 21-B (f) is obtained. At this time, the width d2 of the protruding portion of the second hetero semiconductor region 3 is defined in a self-aligned manner by the receding width of the mask material 42 receded in FIG. 21-B (d) in the previous step. For this reason, the width | variety of the protrusion part of the 1st hetero semiconductor region 4 can be formed uniformly irrespective of the alignment of photolithography. Therefore, the resistance value of the protruding portion of the first hetero semiconductor region 4 becomes uniform, and a semiconductor device with little characteristic variation can be provided.

  Next, as shown in FIG. 21C (g), impurities are introduced into the second hetero semiconductor region 3 to form the first hetero semiconductor region 4. Arsenic or phosphorus can be used as the impurity, and ion implantation or thermal diffusion can be used as the introduction method.

  Finally, as shown in FIG. 21C (h), the semiconductor device having the structure shown in FIG. 20 is completed through the same steps as those shown in FIG. 2-B (e) of the first embodiment. .

  FIG. 22 is a cross-sectional view showing a configuration of a field effect transistor (FET) semiconductor device according to Embodiment 17 of the present invention. The feature of the seventeenth embodiment is that the width of the portion of the first hetero semiconductor region 4 protruding from the second hetero semiconductor region 3 is uniformly formed in a self-aligned manner. Is the same as in the first embodiment.

  Next, a manufacturing method for obtaining the structure of the seventeenth embodiment will be described with reference to FIGS. 23-A to 23-C.

First, as shown in FIG. 23-A (a), on an N-type silicon carbide semiconductor substrate formed by epitaxially growing an N ⁻ -type drain region 2 on an N ⁺ -type substrate region 1, for example, LP− A second polycrystalline silicon layer is formed by a CVD method, and boron is introduced into this layer by, for example, an ion implantation method, thereby depositing and forming a semiconductor layer of the P ⁺ -type second hetero semiconductor region 3.

  At this time, the second polycrystalline silicon layer may be formed by depositing by electron beam evaporation or sputtering and then recrystallizing by laser annealing or the like, or heteroepitaxially grown by, for example, molecular beam epitaxy. It may be formed of single crystal silicon. In addition, solid phase diffusion or vapor phase diffusion may be used for doping.

  Next, as shown in FIG. 23-A (b), after the first mask material 50 is formed on the semiconductor layer of the second hetero semiconductor region 3, the first mask material 50 is formed on the first mask material 50. A second mask material 51 is laminated. An oxide film is used as the first mask material 50, and a nitride film or the like is used as the second mask material 51. However, as long as the mask materials have different etching rates and can be selectively etched, other combinations are possible. Any combination is possible.

  Next, as shown in FIG. 23-A (c), the first mask material 50 and the second mask material 51 are selectively removed by etching using photolithography and patterned.

  Next, as shown in FIG. 23B (d), the second mask material 51 is selectively removed by etching, and is retracted laterally with respect to the first mask material 50. Thereby, a step is formed between the first mask material 50 and the second mask material 51.

  Next, as shown in FIG. 23-B (e), an impurity 53 is introduced using the first mask material 50 and the second mask material 51 as a mask, and the semiconductor layer of the second hetero semiconductor region 3 is amorphous. A quality region 54 is formed. The impurity 53 may be any material that makes the semiconductor layer of the second hetero semiconductor region 3 amorphous. For example, argon may be used. As the introduction method, ion implantation or the like can be used. Subsequently, after removing the first mask material 50 and the second mask material 51, sacrificial oxidation is performed. In this oxidation process, since the oxidation rate of the amorphous region 54 is faster than that of the second hetero semiconductor region 3, the amorphous region 54 is selectively oxidized faster than the second hetero semiconductor region 3. .

  Next, as shown in FIG. 23B (f), the oxide film formed in the previous step is removed by using wet etching or the like using hydrofluoric acid. As a result, a second hetero semiconductor region 3 having a shape as shown in FIG. At this time, the width d3 of the protruding portion of the second hetero semiconductor region 3 is defined in a self-aligned manner by the receding width of the second mask material 51 that has been receded in the process shown in FIG. 23-B (d). The For this reason, the width | variety of the protrusion part of the 2nd hetero semiconductor region 3 can be formed uniformly irrespective of the alignment of photolithography. Therefore, the resistance value of the protruding portion of the first hetero semiconductor region becomes uniform, and a semiconductor device with little characteristic variation can be provided.

  Next, as shown in FIG. 23C (g), impurities are introduced into the second hetero semiconductor region 3 to form the first hetero semiconductor region 4. Arsenic or phosphorus can be used as the impurity, and ion implantation or thermal diffusion can be used as the introduction method.

  Finally, as shown in FIG. 23-C (h), the semiconductor device having the structure shown in FIG. 22 is completed through the same steps as those shown in FIG. 2-B (e) of the first embodiment. .

  As described above, in all the first to 17th embodiments, the semiconductor device using silicon carbide as the substrate material has been described as an example. However, the substrate material may be other semiconductor materials such as silicon, silicon germane, gallium nitride, and diamond. . Moreover, although 4H type was demonstrated as a polytype of silicon carbide, other polytypes, such as 6H and 3C, may be sufficient. Furthermore, the drain electrode 8 (28) and the source electrode 7 (27) are arranged so as to face each other with the drain region 2 (22) interposed therebetween, and the so-called vertical structure transistor in which the drain current flows in the vertical direction has been described. However, it may be a so-called lateral type transistor in which, for example, the drain electrode 8 (28) and the source electrode 7 (27) are arranged on the same main surface of the semiconductor substrate and the drain current flows in the lateral direction.

  Moreover, although the example using polycrystalline silicon as the material used for the first hetero semiconductor region 4 (24) and the second hetero semiconductor region 3 (23) has been described, any material that forms a heterojunction with silicon carbide may be used. For example, other silicon materials such as single crystal silicon and amorphous silicon, other semiconductor materials such as germanium and silicon germanium, and other polytypes of silicon carbide such as 6H and 3C may be used.

  As an example, the drain region 2 (22) is described using N-type silicon carbide, and the first hetero semiconductor region 4 (24) is described using N-type polycrystalline silicon. Any combination of silicon and P-type polycrystalline silicon, P-type silicon carbide and P-type polycrystalline silicon, P-type silicon carbide and N-type polycrystalline silicon may be used.

It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 3 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 5 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 7 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 8 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 8 of this invention. It is sectional drawing which shows the structure of the semiconductor device based on Example 9 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 9 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 9 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 9 of this invention. It is sectional drawing which shows the structure of the semiconductor device based on Example 10 of this invention. It is sectional drawing which shows the structure of the semiconductor device based on Example 11 of this invention. It is sectional drawing which shows the structure of the semiconductor device based on Example 12 of this invention. It is sectional drawing which shows the structure of the semiconductor device based on Example 13 of this invention. It is sectional drawing which shows the structure of the semiconductor device based on Example 14 of this invention. It is sectional drawing which shows the structure of the semiconductor device based on Example 15 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 15 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 15 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 15 of this invention. It is sectional drawing which shows the structure of the semiconductor device based on Example 16 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 16 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 16 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 16 of this invention. It is sectional drawing which shows the structure of the semiconductor device based on Example 17 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 17 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 17 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 17 of this invention.

Explanation of symbols

1, 21 ... substrate region 2, 22 ... drain region 3, 23 ... second hetero semiconductor region (second polycrystalline silicon layer)
4, 24... First hetero semiconductor region (first polycrystalline silicon layer)
5, 25 ... Gate insulating film 6, 26 ... Gate electrode 7, 27 ... Source electrode 8, 28 ... Drain electrode 9, 10, 29, 30, 42, 43, 50, 51 ... Mask material 11 ... Electric field relaxation region 12, DESCRIPTION OF SYMBOLS 31 ... Conductive region 13, 32 ... Channel part 14, 33 ... Source electrode contact part 41 ... Conductive region 44 ... Side wall mask 46, 48, 53 ... Impurity 47 ... 1st amorphous region 49 ... 2nd amorphous region

Claims (18)

A first conductivity type semiconductor substrate;
A first hetero semiconductor region provided in a part of the surface of the semiconductor substrate in contact with one main surface of the semiconductor substrate, and having a band gap different from that of the semiconductor substrate;
A first conductive surface of the semiconductor substrate and a second hetero semiconductor region of a second conductivity type in contact with the first hetero semiconductor region and having a band gap different from that of the semiconductor substrate;
A gate insulating film formed across a portion of the semiconductor substrate that is not covered by the first hetero semiconductor region from a side of the first hetero semiconductor region ;
A gate electrode in contact with the gate insulating film;
A source electrode ohmically connected to the first hetero semiconductor region;
A drain electrode ohmically connected to the semiconductor substrate;
It said portion of the first hetero semiconductor region is stacked on the second hetero semiconductor region, and contact with the gate electrode through at least the gate insulating film, and the semiconductor substrate surface and the second hetero The thickness of the channel portion of the first hetero semiconductor region formed in contact with the side surface of the semiconductor region is such that the second hetero semiconductor region and the first hetero semiconductor region are stacked at the second hetero semiconductor region. A semiconductor device characterized in that it is thinner than the sum of the thickness of the hetero semiconductor region and the thickness of the first hetero semiconductor region. The semiconductor device according to claim 1, wherein the first hetero semiconductor region is of a first conductivity type. 2. The channel portion of the first hetero semiconductor region is of a second conductivity type, and a portion connected to the source electrode of the first hetero semiconductor region is of a first conductivity type. A semiconductor device according to 1. The second hetero semiconductor region of the portion where the second hetero semiconductor region and the first hetero semiconductor region are stacked has a first conductivity type impurity dopant introduced into the first hetero semiconductor region. The semiconductor device according to claim 1, wherein the semiconductor device has a thickness that does not reach at least a junction between the second hetero semiconductor region and the semiconductor substrate. 5. The semiconductor device according to claim 1, wherein a thickness of the first hetero semiconductor region is smaller than a thickness of the second hetero semiconductor region. A groove on the one principal surface of the semiconductor substrate;
The semiconductor device according to claim 1, wherein the second hetero semiconductor region is formed so as to be in contact with at least a bottom portion of the groove. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide. The semiconductor device according to claim 1, wherein the first hetero semiconductor region is formed of any one of single crystal silicon, polycrystalline silicon, and amorphous silicon. 9. The semiconductor device according to claim 1, wherein the second hetero semiconductor region is formed of any one of single crystal silicon, polycrystalline silicon, and amorphous silicon. The semiconductor device according to claim 1, wherein the first hetero semiconductor region and the second hetero semiconductor region are made of the same material. A first step of forming a second hetero semiconductor layer having a band gap different from that of the semiconductor substrate so as to be in contact with the semiconductor substrate;
A second step of selectively removing the second hetero semiconductor layer formed in the first step to form a second hetero semiconductor region;
The semiconductor substrate is stacked on the semiconductor substrate and the second hetero semiconductor region, and the thickness of the portion stacked on the semiconductor substrate is smaller than the thickness of the portion stacked on the second hetero semiconductor region. And a third step of forming a first hetero semiconductor layer having a different band gap;
A fourth step of selectively removing the first hetero semiconductor layer formed in the third step and forming a first hetero semiconductor region exposing the semiconductor substrate at least at one end;
A fifth step of forming a gate insulating film in contact with the semiconductor substrate exposed in the fourth step and the first hetero semiconductor layer formed in the fourth step;
A sixth step of forming a gate electrode in contact with the gate insulating film formed in the fifth step;
A seventh step of forming a source electrode in ohmic contact with the first hetero semiconductor region;
A method of manufacturing a semiconductor device, comprising: an eighth step of forming an ohmic-connected drain electrode with the semiconductor substrate. In the fourth step, the first hetero semiconductor region is formed so that the surface of the second hetero semiconductor region is exposed at least at the other end of the first hetero semiconductor region. A method for manufacturing a semiconductor device according to claim 11. A ninth step of forming a groove in a predetermined region of the semiconductor substrate;
13. The semiconductor device according to claim 11, wherein, in the second step, the second hetero semiconductor region is formed so as to be in contact with at least a bottom portion of the groove formed in the ninth step. Production method. 14. The method according to claim 11, wherein in the second step, the second hetero semiconductor layer is selectively removed by etch back to form the second hetero semiconductor region. The manufacturing method of the semiconductor device of description. A tenth step of forming a second hetero semiconductor layer having a band gap different from that of the semiconductor substrate so as to be in contact with the semiconductor substrate;
An eleventh step of forming a conductive layer on the second hetero semiconductor layer formed in the tenth step;
A second hetero semiconductor region and a conductive region are formed by selectively removing the second hetero semiconductor layer formed in the tenth step and the conductive layer formed in the eleventh step. And the process of
The semiconductor substrate, the second hetero semiconductor region, and the conductive region are stacked so that the thickness of the portion stacked on the semiconductor substrate is thinner than the thickness of the portion stacked on the second hetero semiconductor region. A thirteenth step of forming a first hetero semiconductor layer having a band gap different from that of the semiconductor substrate;
A fourteenth step of forming sidewalls on the side surfaces of the second hetero semiconductor region and the conductive region via the first hetero semiconductor layer formed in the thirteenth step;
Selectively removing the first hetero semiconductor layer using the side wall formed in the fourteenth step as a mask to form a first hetero semiconductor region exposing the semiconductor substrate at least at one end; A fifteenth step of removing the sidewalls;
A sixteenth step of forming a gate insulating film in contact with the semiconductor substrate exposed in the fifteenth step and the first hetero semiconductor region;
A seventeenth step of forming a gate electrode in contact with the gate insulating film formed in the sixteenth step;
An eighteenth step of forming a source electrode in ohmic contact with the first hetero semiconductor region;
And a nineteenth step of forming a drain electrode in ohmic contact with the semiconductor substrate. In the fourteenth step, the sidewall is formed by selectively etching the mask layer by anisotropic etching after forming a mask layer on the first hetero semiconductor layer. The method for manufacturing a semiconductor device according to claim 15. A twentieth step of forming a second hetero semiconductor layer having a band gap different from that of the semiconductor substrate so as to be in contact with the semiconductor substrate;
A 21st step of selectively forming a mask layer on the second hetero semiconductor layer formed in the 20th step;
A 22nd step of selectively introducing impurities into the second hetero semiconductor layer using the mask layer formed in the 21st step as a mask;
A twenty-third step of selectively etching away the mask layer to recede the mask layer laterally;
Using the mask layer receding in the lateral direction in the 23rd step as a mask, the second hetero semiconductor layer is formed so that the impurity introduction depth is shallower than the impurity introduction performed in the 22nd step. A 24th step of introducing impurities into
A 25th step of removing the mask layer;
A twenty-sixth step of selectively oxidizing the region doped with impurities in the twenty-second step and the twenty-fourth step in the second hetero semiconductor layer to form an oxide film region;
A twenty-seventh step of removing the oxide film region formed in the twenty-sixth step and forming a second hetero semiconductor layer exposing the semiconductor substrate at least at one end;
An impurity is selectively introduced into the second hetero semiconductor layer formed in the twenty-seventh step to form a second hetero semiconductor region, and a first hetero semiconductor having a band gap different from that of the semiconductor substrate. Forming a region, and the thickness of one end of the first hetero semiconductor region is the thickness of the second hetero semiconductor region in the portion where the second hetero semiconductor region and the first hetero semiconductor region are stacked. And a 28th step of forming a thin thickness compared to the sum of the thickness of the first hetero semiconductor region;
A twenty-ninth step of forming a gate insulating film in contact with the semiconductor substrate exposed in the twenty-seventh step and the first hetero semiconductor region;
A 30th step of forming a gate electrode in contact with the gate insulating film formed in the 29th step;
A thirty-first step of forming a source electrode in ohmic contact with the first hetero semiconductor region;
And a thirty-second step of forming a drain electrode in ohmic contact with the semiconductor substrate. A thirty-third step of forming a second hetero semiconductor layer having a band gap different from that of the semiconductor substrate so as to be in contact with the semiconductor substrate;
A thirty-fourth step of selectively forming a first mask layer on the second hetero semiconductor layer;
A thirty-fifth step of forming a second mask layer on the first mask layer formed in the thirty-fourth step;
A thirty-sixth step of selectively removing and patterning the first and second mask layers;
A thirty-seventh step of selectively etching away the second mask layer to recede the second mask layer laterally;
Using the first mask layer formed in the thirty-fourth step and the second mask layer receding in the thirty-seventh step as a mask, impurities are selectively introduced into the second hetero semiconductor layer. A thirty-eighth process;
A 39th step of removing the first mask layer and the second mask layer;
A 40th step of selectively oxidizing a region into which an impurity has been introduced in the thirty-eighth step in the second hetero semiconductor layer to form an oxide film region;
A 41st step of removing the oxide film region formed in the 40th step and forming a second hetero semiconductor layer exposing the semiconductor substrate at least at one end;
An impurity is selectively introduced into the second hetero semiconductor layer formed in the forty-first step to form a second hetero semiconductor region, and a first hetero semiconductor having a band gap different from that of the semiconductor substrate Forming a region, and the thickness of one end of the first hetero semiconductor region is the thickness of the second hetero semiconductor region in the portion where the second hetero semiconductor region and the first hetero semiconductor region are stacked. And a forty-second step of forming a thin thickness compared to the sum of the thickness of the first hetero semiconductor region;
A forty-third step of forming a gate insulating film in contact with the semiconductor substrate exposed in the forty-first step and the first hetero semiconductor region;
A forty-fourth step of forming a gate electrode in contact with the gate insulating film formed in the forty-third step;
A 45th step of forming a source electrode ohmically connected to the first hetero semiconductor region;
And a forty-sixth step of forming a drain electrode in ohmic contact with the semiconductor substrate.

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