JP5092244B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  As a conventional example related to the present invention, a silicon carbide field effect transistor which is a semiconductor device according to the prior art is described in Patent Document 1 below.

  In this conventional example, an N− type polycrystalline silicon region and an N + type polycrystalline silicon region are in contact with one main surface of a semiconductor substrate in which an N− type silicon carbide epitaxial region is formed on an N + type silicon carbide substrate. The N− type silicon carbide epitaxial region, the N− type polycrystalline silicon region, and the N + type polycrystalline silicon region are in a heterojunction. A gate electrode is formed through a gate insulating film adjacent to the junction between the N− type silicon carbide epitaxial region and the N + type polycrystalline silicon region. The N− type polycrystalline silicon region is connected to the source electrode, and a drain electrode is formed on the back surface of the N + type silicon carbide substrate.

The silicon carbide field effect transistor configured as described above functions as a switch by controlling the potential of the gate electrode while the source electrode is grounded and a predetermined positive potential is applied to the drain electrode. That is, in a state where the gate electrode is grounded, a reverse bias is applied to the heterojunction of the N− type polycrystalline silicon region and the N + type polycrystalline silicon region and the epitaxial region, and a current flows between the drain electrode and the source electrode. Not flowing. However, when a predetermined positive voltage is applied to the gate electrode, the gate electric field acts on the heterojunction surface between the N + type polycrystalline silicon region and the epitaxial region, and the energy barrier formed by the heterojunction surface at the gate insulating film interface Since the thickness is reduced, a current flows between the drain electrode and the source electrode. In this semiconductor device, since the heterojunction is used as a current cutoff / conduction control channel, the channel length functions at the thickness of the heterobarrier, so that low resistance conduction characteristics can be obtained.
JP 2003-318398 A

  In the above prior art, a heterojunction surface when a positive high voltage is applied to the drain electrode by forming a P-type electric field relaxation region in the N-type silicon carbide epitaxial region under the N-type polycrystalline silicon region In addition, the electric field at the current driving point can be relaxed and the breakdown voltage can be improved.

  However, in the above configuration, the N-type polycrystalline silicon region and the P-type electric field relaxation region form a PN junction. In this case, since the N-PN junction is formed between the drain electrode and the source electrode, the P-N junction between the P-type field relaxation region and the N-type silicon carbide epitaxial layer cannot be used as a diode.

  Further, since the P-type electric field relaxation region is in a floating state, the potential rises when holes flow into the P-type electric field relaxation region, and the N-type polycrystalline silicon region, the P-type electric field relaxation region, and the N-type silicon carbide. There is a possibility that a parasitic bipolar transistor having an epitaxial region as an emitter, a base, and a collector is turned on, a large current flows, and the element is destroyed.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that is less susceptible to current breakdown.

First and second hetero semiconductor regions made of a semiconductor material having a band gap width different from that of the semiconductor substrate are formed on one main surface of the first conductivity type semiconductor substrate. A gate electrode is disposed through a gate insulating film on a heterojunction surface which is an interface between the semiconductor substrate and the first hetero semiconductor region, and a source electrode connected to the first and second hetero semiconductor regions is In the formed semiconductor device, an electric field relaxation region of a second conductivity type is formed in the semiconductor substrate at a predetermined distance from a position where the first hetero semiconductor region, the semiconductor substrate, and the gate insulating film are in contact with each other, A punch-through prevention region of the second conductivity type is formed in the electric field relaxation region, and the impurity concentration of the punch-through prevention region is equal to or higher than the impurity concentration of the electric field relaxation region, The n-through prevention region and the source electrode are ohmically connected via the second hetero semiconductor region, and the second heterojunction surface, which is an interface between the semiconductor substrate and the second hetero semiconductor region, is located in the punch through prevention region. it constitutes a semiconductor device according to claim you are.

  According to the present invention, the electric field relaxation region of the second conductivity type and the source electrode are connected via the second hetero semiconductor region of the second conductivity type, so that the electric field relaxation region and the source electrode are ohmic-connected to a low resistance. By drawing out carriers flowing into the electric field relaxation region to the source electrode, the parasitic bipolar effect can be suppressed. As a result, a semiconductor device that is less likely to cause current breakdown can be provided.

  In the following embodiments, a semiconductor device in which the semiconductor substrate material is silicon carbide (SiC), the hetero semiconductor is polycrystalline silicon, the first conductivity type is N-type, and the second conductivity type is P-type is taken as an example. explain.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is an energy band diagram in the vicinity of a heterojunction surface between an N-type polycrystalline silicon region (shown as an N-type polysilicon region in the figure) and a P-type silicon carbide region. The electrons in the N-type polycrystalline silicon region and the holes in the P-type silicon carbide region are blocked by the energy barrier and cannot freely go back and forth.

  FIG. 2 is an energy band diagram in the vicinity of a heterojunction surface between a P-type polycrystalline silicon region (shown as a P-type polysilicon region in the figure) and a P-type silicon carbide region. By making the impurity concentration of the P-type silicon carbide region sufficiently high, the energy barrier becomes thin, and the holes in the P-type polycrystalline silicon region and the P-type silicon carbide region can tunnel the energy barrier, Can come and go freely. That is, the P-type polycrystalline silicon region and the P-type silicon carbide region are in ohmic contact.

  Further, the ohmic connection between the source electrode and the P-type polycrystalline silicon region can be achieved by setting the impurity concentration in the P-type polycrystalline silicon region to a sufficiently high concentration, which is generally used in silicon LSIs and power devices. This is the technology used.

  Based on the above principle, the source electrode and the P-type silicon carbide region can be ohmically connected through the P-type polycrystalline silicon region.

  FIG. 3 is a diagram showing a semiconductor device according to this embodiment. This figure is a cross-sectional view showing a unit cell. In fact, a large number of such unit cells are connected in parallel.

  An N− type silicon carbide epitaxial region 2 is laminated on an N + type silicon carbide substrate 1 which is a first conductivity type serving as a drain region, thereby forming a first conductivity type semiconductor substrate. In a predetermined region in N − type silicon carbide epitaxial region 2, a P-type electric field relaxation region 10 that is a second conductivity type is formed.

  An N-type polycrystalline silicon region 4 as a first hetero semiconductor region and a P-type polycrystalline silicon region 3 as a second hetero semiconductor region are formed on a predetermined region of the surface of the epitaxial region 2 which is one main surface of the semiconductor substrate. Is formed. The polycrystalline silicon layers (N-type polycrystalline silicon region 4 and P-type polycrystalline silicon region 3) have a band gap width different from that of silicon carbide, and are heterojunction with epitaxial region 2 (including electric field relaxation region 10). In addition, an energy barrier exists at the joint surface.

  A gate electrode 6 is disposed adjacent to the first heterojunction surface which is an interface between the epitaxial region 2 and the N-type polycrystalline silicon region 4 via a gate insulating film 5.

  As shown in FIG. 3, the N-type polycrystalline silicon region 4 that is the first hetero semiconductor region, the epitaxial region 2 that is a part of the semiconductor substrate, and the gate insulating film 5 are separated from each other by a predetermined distance from the electric field. Relaxation region 10 is formed.

  An interlayer insulating film 7 is formed on the polycrystalline silicon regions 3 and 4 and the gate electrode 6. N-type polycrystalline silicon region 4 and P-type polycrystalline silicon region 3 are connected to source electrode 8. A drain electrode 9 is formed on the back surface of N + type silicon carbide substrate 1.

  In the present embodiment, the source electrode 8 and the P-type electric field relaxation are realized by making a part of the polycrystalline silicon region as a component (part indicated by 3) P-type, as can be seen from the above description. The region 10 can be easily ohmic-connected through the P-type polycrystalline silicon region 3 which is the second hetero semiconductor region.

  In the present embodiment, the P-type electric field relaxation region 10 and the source electrode 8 are ohmically connected via the P-type polycrystalline silicon region 3 to provide a diode having the source electrode 8 as an anode and the drain electrode 9 as a cathode. Can be built in.

  Further, by pulling out holes flowing into the P-type electric field relaxation region 10 to the source electrode 8, the N-type polycrystalline silicon region 4, the P-type electric field relaxation region 10, and the N-type silicon carbide epitaxial region 2 are respectively formed as an emitter, The effect of the parasitic bipolar transistor as the base and collector can be suppressed, and the parasitic bipolar transistor can be turned on and a large current can be prevented from flowing and the device from being destroyed. That is, the present embodiment is a semiconductor device that is less likely to cause current breakdown.

[Second Embodiment]
FIG. 4 shows a semiconductor device according to the second embodiment. This figure is a cross-sectional view showing a unit cell. In fact, a large number of such unit cells are connected in parallel.

  The present embodiment is different from the first embodiment in that a P-type punch-through prevention region 11 is formed in the P-type electric field relaxation region 12, and the P-type electric field relaxation region 12 is a P-type punch-through prevention region. 11 is connected to the P-type polycrystalline silicon region 3 through 11.

  By increasing the impurity concentration at the heterojunction surface (making the impurity concentration of the P-type punch-through prevention region 11 equal to or higher than the impurity concentration of the P-type electric field relaxation region 12, for example), the ohmic contact at the heterojunction surface is achieved. Connection can be made lower resistance. Further, the concentration of the electric field at the end of the electric field relaxation region is further suppressed by lowering the impurity concentration of the P type electric field relaxation region 12 at the PN junction surface with the N-type silicon carbide epitaxial region 2. I can do it.

  In the present embodiment, the P-type punch-through prevention region 11 and the source electrode 8 are ohmically connected to the lower resistance through the P-type polycrystalline silicon region 3 so that the source electrode 8 serves as the anode and drain electrode 9. It is possible to incorporate a lower-loss diode with a cathode as the cathode.

  Further, the holes flowing into the P-type electric field relaxation region 12 are pulled out to a low resistance by the source electrode 8, whereby the N-type polycrystalline silicon region 4, the P-type electric field relaxation region 12, and the N-type silicon carbide epitaxial region 2 are respectively emitters. The parasitic bipolar transistor effect of the base and the collector can be suppressed, and the parasitic bipolar transistor can be turned on and a large current can be prevented from flowing and the device from being destroyed. That is, the present embodiment is a semiconductor device that is less likely to cause current breakdown.

[Third embodiment]
FIG. 5 is a diagram showing a semiconductor device according to the third embodiment. This figure is a cross-sectional view showing a unit cell. In fact, a large number of such unit cells are connected in parallel.

  This embodiment is different from the second embodiment in that the second heterojunction surface which is the interface between the semiconductor substrate and the P-type polycrystalline silicon region 3 which is the second hetero semiconductor region is P This is a point located in the die punch-through prevention region 11. With such a configuration, even when the P-type field relaxation region 12 is depleted, the ohmic contact area between the P-type punch-through prevention region 11 and the P-type polycrystalline silicon region 3 does not change, and a stable ohmic contact is achieved. A connection can be obtained.

  According to the present embodiment, the P-type punch-through prevention region 11 and the source electrode 8 are more stably ohmic-connected through the P-type polycrystalline silicon region 3 so that the source electrode 8 is the anode and drain electrode 9. The operation of the built-in diode with the cathode as the cathode can be further stabilized.

  Further, the holes flowing into the P-type electric field relaxation region 12 are stably extracted to the source electrode 8, whereby the N-type polycrystalline silicon region 4, the P-type electric field relaxation region 12, and the N − -type silicon carbide epitaxial region 2 are respectively emitters. The parasitic bipolar transistor effect of the base and the collector can be suppressed, and the parasitic bipolar transistor can be turned on and a large current can be prevented from flowing and the device from being destroyed. That is, the present embodiment is a semiconductor device that is less likely to cause current breakdown.

  In the above embodiment, the P-type electric field relaxation region and the source electrode can be ohmically connected to each other with a low resistance by connecting the P-type electric field relaxation region and the source electrode via the P-type polycrystalline silicon layer. I can do it.

  As a result, a diode having a source electrode as an anode and a drain electrode as a cathode can be incorporated. This eliminates the need for commutation diodes in the inverter circuit to be formed in different regions or different substrates within the same substrate, thereby enabling downsizing and cost reduction of the inverter circuit.

  Further, by pulling out holes flowing into the P-type electric field relaxation region to the source electrode, parasitic bipolar using the N-type polycrystalline silicon region, the P-type electric field relaxation region, and the N-type silicon carbide epitaxial region as the emitter, base, and collector, respectively. The transistor effect can be suppressed and the breakdown resistance of the device can be improved.

  In the above embodiment, the first conductivity type is N type and the second conductivity type is P type. However, when the first conductivity type is P type and the second conductivity type is N type, The effects of the present invention can be obtained in the same manner as described above.

  Further, as the material of the semiconductor substrate, not only silicon carbide but also gallium nitride or diamond may be used.

  The first and second hetero semiconductor regions may be made of not only polycrystalline silicon but also single crystal silicon, amorphous silicon, single crystal silicon germanium, polycrystalline silicon germanium, or amorphous silicon germanium.

  The first and second hetero semiconductor regions may be made of single crystal germanium, polycrystalline germanium, amorphous germanium, single crystal gallium arsenide, polycrystalline gallium arsenide, or amorphous gallium arsenide.

It is an energy band figure explaining the 1st Example of this invention. It is an energy band figure explaining the 1st Example of this invention. 1 is a cross-sectional structure diagram of an element portion for explaining a first embodiment of the present invention. It is an element part cross-section figure explaining the 2nd Example of this invention. It is an element part cross-section figure explaining the example of 3rd Embodiment of this invention.

Explanation of symbols

  1: N + type silicon carbide substrate, 2: N− type silicon carbide epitaxial region, 3: P type polycrystalline silicon region, 4: N type polycrystalline silicon region, 5: Gate insulating film, 6: Gate electrode, 7: Interlayer Insulating film, 8: source electrode, 9: drain electrode, 10: electric field relaxation region, 11: P-type punch-through prevention region, 12: P-type electric field relaxation region.

Claims (5)

A first conductivity type semiconductor substrate;
A first hetero semiconductor region formed in a predetermined region on one main surface of the semiconductor substrate and made of a semiconductor material having a band gap width different from that of the semiconductor substrate;
A second hetero semiconductor region having a second conductivity type, formed on a predetermined region of the main surface of the semiconductor substrate, made of a semiconductor material having a band gap different from that of the semiconductor substrate;
A gate electrode disposed via a gate insulating film adjacent to a first heterojunction surface which is an interface between the semiconductor substrate and the first hetero semiconductor region;
A source electrode connected to the first and second hetero semiconductor regions;
In a semiconductor device comprising a drain electrode connected to the semiconductor substrate,
A second conductivity type electric field relaxation region is formed in the semiconductor substrate at a predetermined distance from a position where the first hetero semiconductor region, the semiconductor substrate, and the gate insulating film are in contact with each other;
A punch-through prevention region of the second conductivity type is formed in the electric field relaxation region,
The impurity concentration of the punch-through prevention region is not less than the impurity concentration of the electric field relaxation region,
The punch-through prevention region and the source electrode are ohmic-connected through the second hetero semiconductor region ,
A semiconductor device, wherein a second heterojunction surface which is an interface between the semiconductor substrate and the second hetero semiconductor region is located in the punch-through prevention region . The semiconductor device according to claim 1, wherein the first hetero semiconductor region has a first conductivity type. The semiconductor substrate is a silicon carbide semiconductor device according to claim 1 or 2, characterized in that gallium nitride or diamond. Said first and second hetero semiconductor region is a single crystal silicon, polycrystalline silicon, amorphous silicon, single crystal silicon germanium, any one of claims 1 to 3, characterized in that it consists of polycrystalline silicon germanium or amorphous silicon germanium A semiconductor device according to 1. It said first and second hetero semiconductor regions, a single-crystal germanium, polycrystalline germanium, amorphous germanium, monocrystalline gallium arsenide, any one of claims 1 to 3, characterized in that it consists of polycrystalline gallium arsenide, or amorphous gallium arsenide A semiconductor device according to 1.

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