JP5476743B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device that performs current control using a heterojunction.

  A transistor having a heterojunction between a silicon carbide epitaxial layer and a semiconductor layer (for example, a polycrystalline silicon layer) having a band gap different from that of the silicon carbide epitaxial layer has been proposed (see, for example, Patent Document 1).

JP 2003-318398 A

  Here, as an example for reducing the on-resistance of the transistor, it is conceivable to increase the length of the “current driver” per unit area. The “current driving unit” is a region where the silicon carbide epitaxial layer, the polycrystalline silicon layer, and the gate insulating film are in contact with each other, and is a portion that controls current interruption / conduction.

  However, when the above concavo-convex structure is adopted in a vertical semiconductor device using, for example, silicon carbide, the distance from the drain electrode formed on the back surface of the vertical semiconductor device is the distance from the convex portion to the concave portion. Shorter. For this reason, a drain electric field is more strongly applied to the concave portion than the convex portion, and a leak current is likely to be generated at the time of OFF.

  In view of the above problems, an object of the present invention is to provide a semiconductor device that has a low on-resistance and that suppresses the occurrence of a leakage current when it is off.

The present invention includes (a) a first conductive type semiconductor substrate having a first main surface having a concavo-convex structure formed at a predetermined location, and (b) a first main body of the semiconductor substrate having a band gap different from that of the semiconductor substrate. A hetero semiconductor layer disposed by forming a heterojunction at the concave bottom surface and the convex top end of the concave-convex structure on the surface; and (c) a first main body of the semiconductor substrate adjacent to the region where the hetero semiconductor layer is disposed. A gate insulating film disposed on the surface; (d) a gate electrode disposed on the gate insulating film; (e) a source electrode disposed on the hetero semiconductor layer; and (f) a second main body of the semiconductor substrate. A drain electrode disposed on the surface, a current driving portion in which the semiconductor substrate, the hetero semiconductor layer, and the gate insulating film are in contact with each other is formed along the concavo-convex structure , and a heterojunction region on the bottom surface of the concave portion of the hetero semiconductor layer; Hetero contact at the top of the convex part By at least one of impurity concentration and conductivity type as the region to be different, the height of the energy barrier for majority carriers in the semiconductor substrate at the interface of the heterojunction, the convex top end at least part of the bottom portion of the concave portion of the concavo-convex structure Is set higher than.

  According to the present invention, the current driver is formed along the concavo-convex structure formed on the surface of the silicon carbide epitaxial layer, and the energy barrier height at the bottom of the concave portion of the concavo-convex structure is higher than the energy barrier height at the top of the convex portion. In addition, the on-resistance is low, and the occurrence of leakage current at the off time is suppressed.

1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a typical sectional view perspective view showing the composition of the semiconductor device of related technology. It is a typical section perspective view showing the composition of the semiconductor device concerning a 1st embodiment of the present invention. 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIGS. 5A and 5B are energy band diagrams at the heterojunction interface of the semiconductor device according to the first embodiment of the present invention, FIG. 5A is an energy band diagram at the bottom of the recess, and FIG. FIG. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention (the 1). FIG. 6 is a process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the first embodiment (No. 2). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention (the 3). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention (the 4). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention (the 5). It is typical sectional drawing which shows the structure of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is typical sectional drawing which shows the structure of the semiconductor device which concerns on the other modification of the 1st Embodiment of this invention. It is typical sectional drawing which shows the structure of the semiconductor device which concerns on the other modification of the 1st Embodiment of this invention. It is typical sectional drawing which shows the structure of the semiconductor device which concerns on the other modification of the 1st Embodiment of this invention. It is a typical sectional view showing the composition of the semiconductor device concerning a 2nd embodiment of the present invention. It is typical sectional drawing which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a typical sectional view showing the composition of the semiconductor device concerning a 4th embodiment of the present invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention (the 1). It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention (the 2). FIG. 9 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention. It is a typical sectional view showing the composition of the semiconductor device concerning a 6th embodiment of the present invention. It is typical sectional drawing which shows the structure of the semiconductor device which concerns on the 7th Embodiment of this invention.

  Next, first to seventh embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Also, the following first to seventh embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the materials of components, The shape, structure, arrangement, etc. are not specified below. The embodiment of the present invention can be variously modified within the scope of the claims.

(First embodiment)
As shown in FIG. 1, the semiconductor device 1 according to the first embodiment of the present invention is different from the semiconductor substrate 10 of the first conductivity type having the first main surface 101 on which the concavo-convex structure is formed, and the semiconductor substrate 10. A hetero semiconductor layer 20 having a band gap and arranged to form a heterojunction on the first main surface 101 of the semiconductor substrate 10, and adjacent to the region where the hetero semiconductor layer 20 is arranged, The gate insulating film 30 disposed on the first major surface 101, the gate electrode 40 disposed on the gate insulating film 30, the source electrode 50 disposed on the hetero semiconductor layer 20, and the second of the semiconductor substrate 10 A drain electrode 60 disposed on the main surface 102. Then, the current driving unit where the semiconductor substrate 10, the hetero semiconductor layer 20 and the gate insulating film 30 are in contact with each other is formed along the concavo-convex structure, and the height of the energy barrier against majority carriers in the semiconductor substrate 10 at the heterojunction interface is The semiconductor device 1 is formed so that at least a part of the concave bottom surface of the concave-convex structure is higher than the upper end of the convex portion. If the first conductivity type is N-type, the second conductivity type is P-type. If the first conductivity type is P-type, the second conductivity type is N-type. Hereinafter, a case where the first conductivity type is an N type will be described as an example.

  The gate electrode 40, the source electrode 50, and the drain electrode 60 of the semiconductor device 1 are connected to the gate terminal T1, the source terminal T2, and the drain terminal T3, respectively. A predetermined voltage is applied to the gate terminal T1, the source terminal T2, and the drain terminal T3 in order to operate the semiconductor device 1.

The semiconductor substrate 10 shown in FIG. 1 has a structure in which an N ⁺ type silicon carbide substrate 11 in contact with a drain electrode 60 and an N ⁻ type silicon carbide epitaxial layer 12 are laminated. Although the case where the semiconductor substrate 10 is silicon carbide will be described here, the semiconductor substrate 10 made of gallium nitride or diamond can also be used in the first embodiment.

  Hetero semiconductor layer 20 is arranged in a predetermined region on the upper surface of silicon carbide epitaxial layer 12. Silicon carbide epitaxial layer 12 and hetero semiconductor layer 20 having different band gaps are heterojunction, and an energy barrier exists at the junction interface.

  The gate electrode 40 disposed on the gate insulating film 30 is covered with an interlayer insulating film 70. The gate electrode 40 and the source electrode 50 are electrically separated by the interlayer insulating film 70. The gate electrode 40 and the hetero semiconductor layer 20 are electrically separated by the gate insulating film 30. Drain electrode 60 is ohmically connected to the main surface of silicon carbide substrate 11 facing the main surface in contact with silicon carbide epitaxial layer 12.

  FIG. 1 shows a cross section in which two basic cells of a semiconductor device 1 are arranged. A hetero semiconductor layer 20 is formed for each basic cell, and the semiconductor device 1 is generally used in a configuration in which a plurality of basic cells are connected in parallel. Hereinafter, a first embodiment of the present invention will be described using the cross-sectional structure shown in FIG. In addition, the outermost peripheral portion of a chip in which a plurality of basic cells are connected in parallel is provided with a termination structure (not shown) such as a guard ring for reducing the electric field concentration around the field effect transistor when the field effect transistor is turned off and realizing a high breakdown voltage. General termination structures used in the power device field are also applicable.

  The basic operation of the semiconductor device 1 according to the first embodiment will be described below. Here, a case where the hetero semiconductor layer 20 having a band gap different from that of the semiconductor substrate 10 is a polycrystalline silicon (Poly-Si) film will be described as an example. As shown below, the semiconductor device 1 functions as a switching element by controlling the potential of the gate electrode 40 in a state where the source electrode 50 is grounded and a predetermined positive drain voltage Vd is applied to the drain electrode 60. .

  With the gate electrode 40 grounded, a reverse bias is applied to the heterojunction between the semiconductor substrate 10 and the hetero semiconductor layer 20. For this reason, the energy barrier formed at the heterojunction interface blocks the flow of electrons, which are majority carriers in the semiconductor substrate 10, and the semiconductor device 1 is in the off state.

  On the other hand, when a positive gate voltage Vg is applied to the gate electrode 40, a gate electric field acts on the heterojunction interface between the semiconductor substrate 10 and the hetero semiconductor layer 20, and the thickness of the energy barrier at the heterojunction interface is reduced due to electric field concentration. getting thin. Therefore, a tunnel current passing through the heterojunction is generated, and the semiconductor device 1 is turned on.

  As described above, the semiconductor device 1 shown in FIG. 1 controls the current flowing between the source electrode 50 and the drain electrode 60 by controlling the thickness of the energy barrier at the heterojunction interface by the potential applied to the gate electrode 40. To do. That is, the semiconductor device 1 does not form an inversion channel region like a general MOSFET and has a low on-resistance because the channel length is about the thickness of the hetero barrier.

  As already described, the length of the current driving unit, which is a part that controls the interruption / conduction of current, corresponds to the gate width of the MOSFET, and by increasing the length per unit area of the current driving unit, the semiconductor device 1 can be reduced.

  FIG. 2 is a perspective view of a silicon carbide semiconductor device according to a related technique in which an uneven structure is not formed on first main surface 101 of semiconductor substrate 10. 2 corresponds to a perspective view of the left half of the semiconductor device 1 shown in FIG. 1 excluding the gate insulating film 30, the gate electrode 40, and the interlayer insulating film 70. FIG. As shown in FIG. 2, in the related technique in which the uneven structure is not formed on the first main surface 101 of the semiconductor substrate 10, the hetero semiconductor layer 20 is formed on the flat surface of the silicon carbide epitaxial layer 12, and the current driver 90. Are formed linearly. In FIG. 2, the current driver 90 is indicated by a bold line (the same applies below).

  On the other hand, in the semiconductor device 1 according to the first embodiment of the present invention, as shown in FIG. 3, the hetero semiconductor layer 20 is formed on the first main surface 101 of the semiconductor substrate 10 on which the concavo-convex structure is formed. 3 is a perspective view of the left half of the semiconductor device 1 with the gate insulating film 30, the gate electrode 40 and the interlayer insulating film 70 removed from the semiconductor device 1 as in FIG. 2, and FIG. 1 shows the X-axis direction of FIG. It is sectional drawing seen from the direction which the electrode 40 and the source electrode 50 extend | stretch. As shown in FIG. 3, in the semiconductor device 1, the current driving unit 90 in which the semiconductor substrate 10, the hetero semiconductor layer 20, and the gate insulating film 30 are in contact with each other has a concavo-convex structure formed on the first main surface 101 of the semiconductor substrate 10. Formed along. As a result, the current driver 90 becomes longer and the on-resistance becomes lower than when the uneven structure is not formed on the first main surface 101.

  As illustrated in FIG. 3, the hetero semiconductor layer 20 of the semiconductor device 1 is disposed on the low-concentration N-type polycrystalline silicon film 21 and the low-concentration N-type polycrystalline silicon film 21. A high-concentration N-type polycrystalline silicon film 22 having a higher impurity concentration than the crystalline silicon film 21 is formed. The low-concentration N-type polycrystalline silicon film 21 is in contact with the bottom of the concave portion of the concavo-convex structure formed on the first main surface 101 of the semiconductor substrate 10, and the high-concentration N-type polycrystalline silicon film 22 is on the top of the convex portion of the concavo-convex structure. Touch. This is due to the following reason.

  If the length of the current drive unit 90 per unit area is simply increased, it is possible only by forming an uneven structure on the surface of the silicon carbide epitaxial layer 12. However, when a concavo-convex structure is formed on the surface of the silicon carbide epitaxial layer 12, the bottom surface of the concave portion is shorter than the upper end portion of the convex portion (1) the distance to the drain electrode 60 is short (the depletion layer width is narrow), 2) The electric field at the heterojunction interface at the bottom surface of the recess is increased due to the fact that electric field concentration is likely to occur, and leakage current at the time of off is likely to occur. In this case, if the energy barrier against electrons at the heterojunction interface as a whole is increased, the leakage current at the time of OFF can be reduced, but the ON resistance is increased.

  However, in the semiconductor device 1 shown in FIG. 3, the hetero semiconductor layer 20 includes a low-concentration N-type polycrystalline silicon film 21 heterojunction with the semiconductor substrate 10 at the bottom of the recess and a high heterojunction with the semiconductor substrate 10 at the top of the projection. By adopting a structure in which the N-type polycrystalline silicon film 22 is laminated, the energy barrier against electrons at the heterojunction interface at the bottom of the recess becomes higher than the energy barrier at the top of the protrusion. For this reason, it is possible to suppress a leakage current at the time of OFF due to a large electric field at the heterojunction interface at the bottom surface of the recess.

  4 is a cross-sectional view of FIG. 3 as viewed from the Y-axis direction, that is, the direction in which the basic cells of the semiconductor device 1 are arranged. In FIG. 4, the junction between the semiconductor substrate 10 and the hetero semiconductor layer 20 is a current driver 90. A low-concentration N-type polycrystalline silicon film 21 is formed in a region (region A) where the hetero semiconductor layer 20 is heterojunction with the semiconductor substrate 10 at the bottom of the recess. A high-concentration N-type polycrystalline silicon film 22 is formed in a region (region B) where the hetero semiconductor layer 20 is heterojunction with the semiconductor substrate 10 at the upper end of the convex portion.

When polycrystalline silicon is deposited on an N ⁻ -type silicon carbide epitaxial layer to form a heterojunction, the energy barrier ΦBn against electrons in the heterojunction depends on the impurity concentration of the polycrystalline silicon. It has been experimentally confirmed that the energy barrier ΦBn has the relationship shown in the following formula (1):

ΦBn (High-concentration N-type polycrystalline silicon) <ΦBn (Low-concentration N-type polycrystalline silicon)
<ΦBn (low concentration P-type polycrystalline silicon) <ΦBn (high concentration P-type polycrystalline silicon) (1)

Here, “high concentration” and “low concentration” represent relative differences in impurity concentration in polycrystalline silicon.

  Therefore, when the hetero semiconductor layer 20 is made of polycrystalline silicon, by adopting a configuration in which the high concentration N-type polycrystalline silicon film 22 is stacked on the low concentration N-type polycrystalline silicon film 21, as shown in FIG. The energy barrier ΦBn (A) of the heterojunction in the region A can be made higher than the energy barrier ΦBn (B) of the heterojunction in the region B.

FIGS. 5A and 5B schematically show energy band diagrams when the conduction band edges (Ec) of regions A and B shown in FIG. 4 are turned off. 5A shows an energy band diagram of the interface between the N ⁻ type silicon carbide epitaxial layer 12 and the low-concentration N type polycrystalline silicon film 21 in the region A, and FIG. 5B shows the N ⁻ type in the region B. An energy band diagram of the interface between the silicon carbide epitaxial layer 12 and the high-concentration N-type polycrystalline silicon film 22 is shown.

  Comparing FIG. 5A and FIG. 5B, regarding the potential gradient (electric field) in the silicon carbide epitaxial layer 12, the gradient dA in the region A is steeper than the gradient dB in the region B. On the other hand, the energy barrier ΦBn (A) in the region A is higher than the energy barrier ΦBn (B) in the region B. Therefore, even when the drain electric field is larger in the region A than in the region B, the electrons in the hetero semiconductor layer 20 are prevented from leaking when they are turned off due to the thermal barrier over the energy barrier or the tunneling of the energy barrier. it can.

Next, the influence on the on-resistance when the structure shown in FIG. 4 is adopted for the semiconductor device 1 will be described. As shown in FIG. 4, the length of the vertical portion of the heterojunction interface formed by the high-concentration N-type polycrystalline silicon film 22 and the N ⁻ -type silicon carbide epitaxial layer 12 is S, and the length of the upper end of the convex portion is U. And T is the length of the bottom surface of the recess at the heterojunction interface formed by the low-concentration N-type polycrystalline silicon film 21 and the silicon carbide epitaxial layer 12.

As already described, since the energy barrier ΦBn (A) in the region A is higher than the energy barrier ΦBn (B) in the region B, the on-resistance R _{ONA in the} region A is higher than the on-resistance R _{ONB in the} region B. . If it is assumed that the on-resistance R _ONA is very high compared to the on-resistance R _ONB and almost no current flows in the region A even when the on-resistance R _ONB is assumed, the length of the portion contributing to current driving in one period of unevenness is 2 × S + U.

  On the other hand, in the case of the related art shown in FIG. 2 in which the hetero semiconductor layer 20 is deposited on the flat silicon carbide epitaxial layer 12 having no concavo-convex structure to form a heterojunction interface, the width is the same as one cycle of the concavo-convex structure. The length of the portion that contributes to current driving at T + U is T + U.

Therefore, the condition that the length of the current driving unit 90 contributing to the current driving is longer when the concave-convex structure shown in FIG. 4 is formed than when there is no concave-convex structure is expressed by the following formula (2). :

2 × S + U> T + U (2)

From equation (2), the following equation (3) is obtained:

2 × S> T (3)

When the condition of Expression (3) is satisfied, the semiconductor device 1 has a lower on-resistance than a semiconductor device in which the current driver 90 is not formed along the concavo-convex structure.

  As described above, according to the semiconductor device 1 according to the first embodiment of the present invention, the current driver 90 is formed along the concavo-convex structure formed on the first main surface 101 of the semiconductor substrate 10. Thus, the length of the current driver 90 per unit area can be increased. In addition, by making the energy barrier height at the bottom of the recess higher than the energy barrier height at the top of the protrusion, the length of the current drive unit 90 per unit area is lengthened, and the occurrence of leakage current at OFF is suppressed. can do. As a result, it is possible to realize the semiconductor device 1 with low on-resistance and suppressed generation of leakage current when off.

  A method for manufacturing the semiconductor device 1 according to the first embodiment of the present invention will be described with reference to FIGS. In addition, the manufacturing method of the semiconductor device 1 described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modification.

(A) As shown in FIG. 6, a semiconductor substrate 10 in which an N ⁺ type silicon carbide substrate 11 and an N ⁻ type silicon carbide epitaxial layer 12 are laminated is prepared. There are several polytypes (crystal polymorphs) in silicon carbide. Here, silicon carbide used for the semiconductor substrate 10 will be described as a typical 4H. The thickness of the silicon carbide substrate 11 is about several tens to several hundreds μm. Silicon carbide epitaxial layer 12 has, for example, an impurity concentration of 10 ¹⁴ to 10 ¹⁸ cm ⁻³ and a thickness of several μm to several tens of μm.

  (B) A photoresist film 111 is formed on the silicon carbide epitaxial layer 12, and the photoresist film 111 is patterned by a photolithography technique. Then, as shown in FIG. 7, a concavo-convex structure is formed on first main surface 101 of silicon carbide epitaxial layer 12 by dry etching using photoresist film 111 as a mask. Thereafter, the photoresist film 111 is peeled off. The depth of the concavo-convex structure is about several hundred nm to several μm, and the pitch is about several hundred nm to several μm. For example, when a concavo-convex structure having a depth of 500 nm and a pitch of 1 μm (a convex portion width of 500 nm and a concave portion width of 500 nm) is formed, the current driving portion is compared with a case where the first main surface 101 of the silicon carbide epitaxial layer 12 is flat. The length of 90 doubles.

  (C) Next, as shown in FIG. 8, a low-concentration N-type polycrystalline silicon film 21 is deposited on the silicon carbide epitaxial layer 12 so as to fill the recess. As a deposition method, a general low-pressure chemical vapor deposition (CVD) method can be used. The N-type impurity may be introduced during the deposition by the low pressure CVD method, or may be introduced by using an ion implantation method or the like after the deposition. Arsenic (As), phosphorus (P), or the like is used as the N-type impurity. When an N-type impurity is introduced into the low-concentration N-type polycrystalline silicon film 21 using the ion implantation method, a heat treatment is performed at 1000 ° C. for about 20 minutes in order to activate the impurity and make the impurity concentration uniform. Also good.

  (D) As shown in FIG. 9, the upper portion of the low concentration N-type polycrystalline silicon film 21 is formed so that the low concentration N-type polycrystalline silicon film 21 remains in the recess of the first main surface 101 of the silicon carbide epitaxial layer 12. Etch. As an etching method, wet etching or dry etching can be used. In this case, the low-concentration N-type polycrystalline silicon film 21 is mainly etched without etching the convex portion of the silicon carbide epitaxial layer 12 by using an etching condition having a high selectivity between polycrystalline silicon and silicon carbide. Can do.

  (E) As shown in FIG. 10, a high-concentration N-type polycrystalline silicon film 22 is deposited on the silicon carbide epitaxial layer 12 and the low-concentration N-type polycrystalline silicon film 21. As a deposition method, a general low-pressure CVD method can be used. As a method for introducing the N-type impurity, the N-type impurity may be introduced during the deposition by the low pressure CVD method, or may be introduced by using an ion implantation method or the like after the deposition. Arsenic, phosphorus, or the like is used as the N-type impurity. At this time, the concentration of the N-type impurity in the high-concentration N-type polycrystalline silicon film 22 is set higher than that in the low-concentration N-type polycrystalline silicon film 21. When ion implantation is used for the introduction of N-type impurities, heat treatment may be performed to activate the impurities and make the impurity concentration uniform. However, the diffusion of the impurities causes the high-concentration N-type polycrystalline silicon film 22 and The heat treatment conditions are set so that the N-type impurity concentration of the low-concentration N-type polycrystalline silicon film 21 is not equal. By using such a manufacturing method, a crystal grain boundary is generated between the high-concentration N-type polycrystalline silicon film 22 and the low-concentration N-type polycrystalline silicon film 21, and diffusion of impurities can be suppressed.

  A method of manufacturing the semiconductor device 1 after FIG. 10 will be described with reference to FIG. In FIG. 1, the stacked body of the low-concentration N-type polycrystalline silicon film 21 and the high-concentration N-type polycrystalline silicon film 22 shown in FIG.

  (F) A photoresist film is formed on the hetero semiconductor layer 20, and the photoresist film is patterned by a photolithography technique or the like. Using this photoresist film as an etching mask, the hetero semiconductor layer 20 is etched into a desired pattern by dry etching. Here, hetero semiconductor layer 20 in the region where gate insulating film 30 and silicon carbide epitaxial layer 12 are in contact is removed, and a portion of first main surface 101 of silicon carbide epitaxial layer 12 is exposed. Thereafter, the photoresist film is peeled off.

  (G) A gate insulating film 30 is deposited to a thickness of, for example, about 100 nm on the hetero semiconductor layer 20 and on the first main surface 101 of the silicon carbide epitaxial layer 12 exposed by removing the hetero semiconductor layer 20 by etching. As the gate insulating film 30, a silicon oxide film is preferably used, and as a deposition method, a thermal CVD method, a plasma CVD method, a sputtering method, or the like can be employed. Next, a gate electrode 40 is deposited on the gate insulating film 30. As the gate electrode 40, for example, polycrystalline silicon into which impurities are introduced is used.

  (H) A photoresist film is applied on the gate electrode 40, and the photoresist film is patterned by a photolithography technique. Using this photoresist film as a mask, the gate electrode 40 is patterned as shown in FIG. 1, and then the photoresist film is peeled off. Next, an interlayer insulating film 70 is formed to cover the gate electrode 40. A contact hole is opened in the interlayer insulating film 70, and a source electrode 50 in contact with the hetero semiconductor layer 20 through the contact hole is formed on the interlayer insulating film 70.

  (I) A drain electrode 60 is formed on the second main surface 102 of the semiconductor substrate 10 to complete the semiconductor device 1 shown in FIG.

  According to the manufacturing method of the semiconductor device 1 according to the first embodiment of the present invention as described above, the current driver 90 is formed along the concavo-convex structure formed on the first main surface 101 of the semiconductor substrate 10, Furthermore, the energy barrier at the heterojunction interface at the bottom of the concave portion can be made higher than the energy barrier at the heterojunction interface at the upper end of the convex portion. As a result, it is possible to provide the semiconductor device 1 having a low on-resistance and suppressed generation of leakage current at the off time.

<Modification>
In the above description, the case where the rectangular recess as shown in FIG. 4 is formed on first main surface 101 of silicon carbide epitaxial layer 12 has been described. However, as shown in FIG. 11, the bottom of the recess may be circular. Further, as shown in FIG. 12, the bottom end of the recess may be rounded.

  Alternatively, as shown in FIG. 13, the N-type impurity concentration of the hetero semiconductor layer 20 may be distributed so as to continuously change. In this case, a shallow N-type impurity is implanted into the hetero semiconductor layer 20 by ion implantation, and diffusion of the impurity is controlled by heat treatment, or implantation energy of the ion implantation is controlled, so that the vicinity of the bottom surface of the recess can be controlled. The hetero semiconductor layer 20 shown in FIG. 13 having an impurity concentration distribution with a low impurity concentration and a high impurity concentration near the upper end of the convex portion can be realized.

  Further, even if the positions of the bottom surfaces of the recesses are not at the same plane level as shown in FIG. 14, the N-type impurity concentration in the hetero semiconductor layer 20 is adjusted according to the distance from the drain electrode 60 and the degree of electric field concentration. In the same manner as described above, it is possible to obtain the effect of suppressing the generation of the leakage current at the off time.

(Second Embodiment)
FIG. 15 shows a cross-sectional structure of a semiconductor device 1 according to the second embodiment of the present invention. FIG. 15 is a structural diagram corresponding to the structural diagram shown in FIG. 4 of the first embodiment.

The difference from the first embodiment is that the conductivity type of the hetero semiconductor layer 20 is P-type. As shown in FIG. 15, high-concentration P-type polycrystalline silicon film 23 heterojunction with silicon carbide epitaxial layer 12 at the bottom of the recess of N ⁻ -type silicon carbide epitaxial layer 12, and silicon carbide epitaxial layer 12 at the top of the protrusion, A low-concentration P-type polycrystalline silicon film 24 that forms a heterojunction is formed.

  Here, the high concentration and the low concentration represent a relative difference in the impurity concentration in the hetero semiconductor layer 20. That is, the hetero semiconductor layer 20 is a laminate in which a low-concentration P-type polycrystalline silicon film 24 having an impurity concentration lower than that of the high-concentration P-type polycrystalline silicon film 23 is laminated on the high-concentration P-type polycrystalline silicon film 23. is there. Other configurations are the same as those of the first embodiment shown in FIG.

  By adopting the configuration shown in FIG. 15, the energy barrier ΦBn (A) against the electrons at the heterojunction interface of the bottom surface of the recess (region A) is changed from the energy barrier ΦBn (B) of the upper end of the protrusion (region B). Can be high. As a result, the generation of leakage current when the semiconductor device 1 is off can be suppressed.

  As described above, according to the semiconductor device 1 according to the second embodiment of the present invention, it is possible to realize the semiconductor device 1 with low on-resistance and suppressed generation of leakage current at the time of off. Further, by changing the conductivity type of the hetero semiconductor layer 20 to P type, as shown in the formula (1), the semiconductor device 1 according to the first embodiment in which the conductivity type of the hetero semiconductor layer 20 is N type. In comparison, the overall energy barrier at the heterojunction interface is increased. For this reason, the leakage current at the time of OFF can further be reduced. Others are substantially the same as those in the first embodiment, and redundant description is omitted.

  Since the manufacturing method of the semiconductor device 1 according to the second embodiment of the present invention is the same as the manufacturing method of the first embodiment already described, description thereof is omitted.

(Third embodiment)
FIG. 16 shows a cross-sectional structure of a semiconductor device 1 according to the third embodiment of the present invention. FIG. 16 is a structural diagram corresponding to the structural diagram shown in FIG. 4 of the first embodiment.

  The difference from the first embodiment is that the hetero semiconductor layer 20 is a stacked body of a P-type polycrystalline silicon film 25 and an N-type polycrystalline silicon film 26. That is, P type polycrystalline silicon film 25 heterojunction with silicon carbide epitaxial layer 12 is formed at the bottom of the recess, and N type polycrystalline silicon film 26 heterojunction with silicon carbide epitaxial layer 12 is formed at the upper end of the projection.

As shown in the equation (1), when polycrystalline silicon is deposited on the N ⁻ -type silicon carbide epitaxial layer 12 to form a heterojunction, the energy barrier in the P-type polycrystalline silicon is N-type multiple. Higher than the energy barrier in crystalline silicon. Therefore, by adopting the configuration shown in FIG. 16, the energy barrier ΦBn (A) against the electrons at the heterojunction interface of the bottom surface of the recess (region A) is changed to the energy barrier ΦBn ( B) can be higher. As a result, the generation of leakage current when the semiconductor device 1 is off can be suppressed.

  As described above, according to the semiconductor device 1 according to the third embodiment of the present invention, it is possible to realize the semiconductor device 1 with low on-resistance and suppressed generation of leakage current at the off time. Further, in the semiconductor device 1 shown in FIG. 16, since the crystalline silicon film heterojunction with the silicon carbide epitaxial layer 12 at the bottom of the recess is P-type, compared to the first embodiment, the bottom of the recess of the silicon carbide epitaxial layer 12 is compared. The energy barrier at the heterojunction interface of the part can be made higher. For this reason, the leakage current at the time of OFF can further be reduced. Others are substantially the same as those in the first embodiment, and redundant description is omitted.

  Since the manufacturing method of the semiconductor device 1 according to the third embodiment of the present invention is similar to the manufacturing method of the first embodiment already described, the description thereof is omitted.

(Fourth embodiment)
FIG. 17 shows a cross-sectional structure of a semiconductor device 1 according to the fourth embodiment of the present invention. FIG. 17 is a structural diagram corresponding to the structural diagram shown in FIG. 4 of the first embodiment.

  The difference from the first embodiment is that the region A of the hetero semiconductor layer 20 that is heterojunction with the silicon carbide epitaxial layer 12 on the bottom surface of the recess is composed of the low-concentration N-type polycrystalline silicon film 21 and the medium-concentration N-type polycrystalline silicon film 27. It is the point which consists of. As shown in FIG. 17, low-concentration N-type polycrystalline silicon film 21 is formed in region C of hetero semiconductor layer 20 in contact with silicon carbide epitaxial layer 12 at the end of the bottom of the recess where the vertical portion and the horizontal portion are in contact. Yes. Then, medium concentration N-type polycrystalline silicon film 27 is formed in region D of hetero semiconductor layer 20 in contact with silicon carbide epitaxial layer 12 at the center of the bottom of the recess. A high-concentration N-type polycrystalline silicon film 22 is formed in a region B where the semiconductor substrate 10 is heterojunction at the upper end of the convex portion.

  Here, the high concentration, medium concentration, and low concentration represent relative differences in the impurity concentration in the hetero semiconductor layer 20. That is, the impurity concentration of the bottom surface portion of the recess (region A) of the N-type hetero semiconductor layer 20 is adjusted to be higher in the central portion (region D) than the end portion (region C). ) So that the impurity concentration at the upper end (region B) of the convex portion is higher.

  By adopting the configuration shown in FIG. 17, the energy barrier ΦBn (D) against the electrons at the heterojunction interface at the center (region D) of the bottom surface of the recess is changed to the energy barrier ΦBn (B) at the upper end of the protrusion (region B). ) Can be higher. Furthermore, the energy barrier ΦBn (C) at the end portion (region C) of the bottom surface of the recess can be made higher than the energy barrier ΦBn (D) at the center portion (region D) of the bottom surface of the recess.

  The drain electric field tends to concentrate at the end portion (region C) of the bottom surface of the recess as compared with the central portion (region D) of the bottom surface of the recess, and leakage current at the time of off is likely to occur. However, according to the semiconductor device 1 according to the fourth embodiment of the present invention, the height of the energy barrier against electrons at the heterojunction interface is made higher at the end of the recess bottom than at the center of the recess bottom so that the unit area is increased. It is possible to suppress the occurrence of leakage current at the time of turning off while increasing the length of the perimeter current driving unit 90. Others are substantially the same as those in the first embodiment, and redundant description is omitted.

  With reference to FIGS. 18-19, the manufacturing method of the semiconductor device 1 which concerns on the 4th Embodiment of this invention is demonstrated. In addition, the manufacturing method of the semiconductor device 1 described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modification.

  (A) A concavo-convex structure is formed on the first main surface 101 of the semiconductor substrate 10 in the same manner as the method described with reference to FIGS. 6 to 7 in the first embodiment.

  (B) A low concentration N-type polycrystalline silicon film 21 is deposited on the silicon carbide epitaxial layer 12. As a deposition method, a general low-pressure CVD method can be used. The N-type impurity may be introduced during the deposition by the low pressure CVD method, or may be introduced by using an ion implantation method or the like after the deposition. Arsenic, phosphorus, or the like is used as the N-type impurity. When an N-type impurity is introduced into the low-concentration N-type polycrystalline silicon film 21 by using an ion implantation method, a heat treatment at 1000 ° C. for about 20 minutes may be performed in order to activate the impurity and make the impurity concentration uniform. . The concavo-convex structure formed on the first main surface 101 of the silicon carbide epitaxial layer 12 as shown in FIG. 18 by etching the upper portion of the low-concentration N-type polycrystalline silicon film 21 using a photolithography technique or an etching technique. A low-concentration N-type polycrystalline silicon film 21 is formed in a shape along the line.

  (C) As shown in FIG. 19, the low-concentration N-type polycrystalline silicon film 21 is anisotropically dry-etched so that the low-concentration N-type polycrystalline silicon film 21 remains only at the end of the recess bottom. At this time, the low-concentration N-type polycrystalline silicon film 21 can be mainly etched by employing an etching condition in which the selection ratio between polycrystalline silicon and silicon carbide is high.

  Since the manufacturing method after FIG. 19 is the same as the method described with reference to FIGS. 8 to 10 and FIG. 1 of the first embodiment, the description thereof will be omitted.

(Fifth embodiment)
FIG. 20 shows a cross-sectional structure of a semiconductor device 1 according to the fifth embodiment of the present invention. FIG. 20 is a structural diagram corresponding to the structural diagram shown in FIG. 4 of the first embodiment.

  17 differs from the fourth embodiment shown in FIG. 17 in that the P-type polycrystalline silicon film 25 is not the low-concentration N-type polycrystalline silicon film 21 in the region C in contact with the silicon carbide epitaxial layer 12 at the end of the bottom of the recess. The low-concentration N-type polycrystalline silicon film 21 is formed instead of the medium-concentration N-type polycrystalline silicon film 27 in the region D that is formed and is in contact with the silicon carbide epitaxial layer 12 at the center of the bottom of the recess.

  In other words, the P-type polycrystalline silicon film 25 and the low-concentration N-type polycrystalline silicon film 21 are formed in the region A of the hetero semiconductor layer 20 heterojunction with the semiconductor substrate 10 at the bottom of the recess, and the semiconductor is formed at the upper end of the convex portion. A high concentration N-type polycrystalline silicon film 22 is formed in the region B of the hetero semiconductor layer 20 heterojunction with the substrate 10. Here, the high concentration and the low concentration represent a relative difference in the impurity concentration in the hetero semiconductor layer 20.

  As shown in Expression (1), by forming the region C with a P-type polycrystalline silicon film and forming the region D with an N-type silicon film, an energy barrier ΦBn ( C) can be made higher than the energy barrier ΦBn (D) in region D.

  Therefore, by adopting the configuration shown in FIG. 20, the energy barrier ΦBn (D) at the central portion (region D) of the bottom surface of the recess is made higher than the energy barrier ΦBn (B) at the upper end portion of the convex portion (region B). In addition, the energy barrier ΦBn (C) at the end portion (region C) of the bottom surface of the recess can be made higher than the energy barrier ΦBn (D) at the center portion (region D) of the bottom surface of the recess.

  As described above, according to the semiconductor device 1 according to the fifth embodiment of the present invention, it is possible to realize the semiconductor device 1 with low on-resistance and suppressed generation of leakage current at the time of off. Furthermore, the energy barrier in the region C can be increased as compared with the fourth embodiment. Therefore, it is possible to further reduce the off-state leakage current in the C region where electric field concentration is likely to occur. Others are substantially the same as those in the first embodiment, and redundant description is omitted.

  Since the manufacturing method of the semiconductor device 1 according to the fifth embodiment of the present invention is the same as the manufacturing method of the fourth embodiment already described, description thereof is omitted.

(Sixth embodiment)
FIG. 21 shows a cross-sectional structure of a semiconductor device 1 according to the sixth embodiment of the present invention. FIG. 21 is a structural diagram corresponding to the structural diagram shown in FIG. 4 of the first embodiment.

The difference from the fourth embodiment shown in FIG. 17 is that the conductivity type of the hetero semiconductor layer 20 is P-type. As shown in FIG. 21, N at the end of the bottom surface of the recess ^- a high concentration P-type polycrystalline silicon film 23 is formed in a region C in contact with the -type silicon carbide epitaxial layer 12, the central portion of the bottom surface of the recess N ^- type of Medium concentration P-type polycrystalline silicon film 28 is formed in region D in contact with silicon carbide epitaxial layer 12. A low-concentration P-type polycrystalline silicon film 24 is formed in a region B in contact with the N ⁻ -type silicon carbide epitaxial layer 12 at the upper end of the convex portion.

  Here, the high concentration, medium concentration, and low concentration represent relative differences in the impurity concentration in the hetero semiconductor layer 20. That is, the impurity concentration of the bottom surface portion (region A) of the recess of the P-type hetero semiconductor layer 20 is adjusted to be lower in the center portion (region D) than the end portion (region C), and further, the bottom surface portion of the recess (region A). ) Is adjusted so that the impurity concentration at the upper end of the convex portion (region B) is lower.

  By adopting the configuration as described above, the energy barrier ΦBn (D) against the electrons at the heterojunction interface at the central portion (region D) of the bottom surface of the recess is changed to the energy barrier ΦBn (B) at the upper end portion of the protrusion (region B). Further, the energy barrier ΦBn (C) at the end portion (region C) of the bottom surface of the recess can be made higher than the energy barrier ΦBn (D) at the center portion (region D) of the bottom surface of the recess. For this reason, it is possible to reduce the leakage current at the OFF time in the C region where electric field concentration is likely to occur. Further, by making the conductivity type of the hetero semiconductor layer 20 P type, as shown in the formula (1), compared to the fourth embodiment in which the conductivity type of the hetero semiconductor layer 20 is N type, the hetero junction The energy barrier at the interface increases overall.

  As described above, according to the semiconductor device 1 of the sixth embodiment, it is possible to realize the semiconductor device 1 with low on-resistance and suppressed generation of leakage current at the time of off. Furthermore, since the energy barrier at the heterojunction interface is higher as a whole than in the fourth embodiment, it is possible to further reduce the off-state leakage current. Others are substantially the same as those in the first embodiment, and redundant description is omitted.

  Since the manufacturing method of the semiconductor device 1 according to the sixth embodiment of the present invention is the same as the manufacturing method of the fourth embodiment already described, the description thereof is omitted.

(Seventh embodiment)
FIG. 22 shows a cross-sectional structure of a semiconductor device 1 according to the seventh embodiment of the present invention. FIG. 22 is a structural diagram corresponding to the structural diagram shown in FIG. 4 of the first embodiment.

  A difference from the fourth embodiment shown in FIG. 17 is that a high-concentration P-type polycrystalline silicon film 23 is formed in a region C in contact with the silicon carbide epitaxial layer 12 at the end of the bottom of the recess, and Low-concentration P-type polycrystalline silicon film 24 is formed in region D in contact with silicon carbide epitaxial layer 12, and N-type polycrystalline silicon film 26 is formed in region B in contact with silicon carbide epitaxial layer 12 at the upper end of the convex portion. It is. Here, the high concentration and the low concentration represent a relative difference in the impurity concentration in the hetero semiconductor layer 20.

  As shown in the equation (1), the region C is formed of a P-type polycrystalline silicon film and the region D is formed of an N-type silicon film, whereby the energy barrier ΦBn ( C) can be made higher than the energy barrier ΦBn (D) in region D.

  By adopting the configuration shown in FIG. 22, the energy barrier ΦBn (D) against the electrons in the heterojunction at the center (region D) of the bottom surface of the recess is changed to the energy barrier ΦBn (B) at the upper end of the protrusion (region B). Further, the energy barrier ΦBn (C) at the end portion (region C) of the bottom surface of the recess can be made higher than the energy barrier ΦBn (D) at the center portion (region D) of the bottom surface of the recess.

  As described above, according to the semiconductor device 1 according to the seventh embodiment of the present invention, it is possible to realize the semiconductor device 1 with low on-resistance and suppressed generation of leakage current at the time of off. Furthermore, the energy barrier in the region D can be made higher than in the fourth embodiment. For this reason, the leakage current at the time of OFF can further be reduced. Others are substantially the same as those in the first embodiment, and redundant description is omitted.

  Since the manufacturing method of the semiconductor device 1 according to the seventh embodiment of the present invention is the same as the manufacturing method of the fourth embodiment already described, the description thereof is omitted.

(Other embodiments)
As described above, the present invention has been described according to the first to seventh embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the description of the first to seventh embodiments already described, the conductivity type of silicon carbide substrate 11 and silicon carbide epitaxial layer 12 is the N type, but it may be the P type. However, when the majority carrier of the semiconductor substrate 10 is an electron, the carrier mobility in the semiconductor substrate 10 is higher than when the majority carrier is a hole, and the on-resistance can be lowered.

  In the first to seventh embodiments, the case where the groove is formed along the Y-axis direction shown in FIG. 3 is shown. However, if the current driving unit 90 is formed along the unevenness, a hole shape is formed. It may be uneven.

  Moreover, although 4H was used as the polytype of silicon carbide used for the semiconductor substrate 10, 3H, 6H, and other polytype silicon carbide can also be used. Furthermore, although silicon carbide is used as the semiconductor substrate 10, gallium nitride or diamond can also be used.

  In the first to seventh embodiments, examples in which polycrystalline silicon is used for the hetero semiconductor layer 20 have been described. However, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), or the like is used for the hetero semiconductor layer 20. be able to. Moreover, as a kind of crystal | crystallization, a single crystal, a polycrystal, an amorphous, etc. can be used.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

  The semiconductor device of the present invention can be used as a switching element that performs current control using a heterojunction.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Semiconductor base | substrate 11 ... Silicon carbide substrate 12 ... Silicon carbide epitaxial layer 20 ... Hetero semiconductor layer 21 ... Low concentration N type polycrystalline silicon film 22 ... High concentration N type polycrystalline silicon film 23 ... High concentration P type Polycrystalline silicon film 24 ... low-concentration P-type polycrystalline silicon film 25 ... P-type polycrystalline silicon film 26 ... N-type polycrystalline silicon film 27 ... medium-concentration N-type polycrystalline silicon film 28 ... medium-concentration P-type polycrystalline silicon film DESCRIPTION OF SYMBOLS 30 ... Gate insulating film 40 ... Gate electrode 50 ... Source electrode 60 ... Drain electrode 70 ... Interlayer insulating film 90 ... Current drive part 101 ... 1st main surface 102 ... 2nd main surface 111 ... Photoresist film

Claims (11)

A first-conductivity-type semiconductor substrate having a first main surface with a concavo-convex structure formed at a predetermined location ;
A hetero semiconductor layer having a band gap different from that of the semiconductor substrate and arranged to form a heterojunction at a concave bottom surface and a convex top end of the concave-convex structure on the first main surface of the semiconductor base;
A gate insulating film disposed on the first main surface of the semiconductor substrate adjacent to the region where the hetero semiconductor layer is disposed;
A gate electrode disposed on the gate insulating film;
A source electrode disposed on the hetero semiconductor layer;
A drain electrode disposed on the second main surface of the semiconductor substrate,
A current driving unit in which the semiconductor substrate, the hetero semiconductor layer and the gate insulating film are in contact with each other is formed along the concavo-convex structure;
In the semiconductor substrate at the interface of the heterojunction , at least one of impurity concentration and conductivity type is different between a region heterojunction at the bottom surface of the recess of the hetero semiconductor layer and a region heterojunction at the top end of the protrusion. height of an energy barrier for majority carriers, wherein a higher than the protrusion upper at least part of the recess bottom surface of the concave-convex structure. The hetero semiconductor layer is N-type , and in the hetero semiconductor layer, the impurity concentration in the region heterojunction with the semiconductor substrate at the bottom of the recess is higher than the impurity concentration in the region heterojunction with the semiconductor substrate at the upper end of the projection. 2. The semiconductor device according to claim 1, wherein the semiconductor device is low. The hetero semiconductor layer is P-type , and in the hetero semiconductor layer, the impurity concentration in the region heterojunction with the semiconductor substrate at the bottom of the recess is higher than the impurity concentration in the region heterojunction with the semiconductor substrate at the top of the projection. The semiconductor device according to claim 1, wherein the semiconductor device is high. 2. A region of the hetero semiconductor layer heterojunction with the semiconductor substrate at the bottom of the recess is P-type , and a region heterojunction with the semiconductor substrate at the top of the protrusion is N-type. A semiconductor device according to 1. By at least one different impurity concentration and conductivity type as the region of the heterojunction in the area and the central portion of the heterojunction at the end of the recess bottom surface of the hetero semiconductor layer, wherein the end portion of the recess bottom surface the energy barrier at the interface of the heterojunction semiconductor device according to any one of claims 1 to 4, wherein the higher than the energy barrier at the heterojunction interface to the said central portion of the bottom surface of the recess. The hetero semiconductor layer is N-type , and in the hetero semiconductor layer,
The impurity concentration of the region heterojunction with the semiconductor substrate at the center of the bottom surface of the recess is lower than the impurity concentration of the region heterojunction with the semiconductor substrate at the top of the protrusion.
6. The impurity concentration in a region heterojunction with the semiconductor substrate at the end of the bottom surface of the recess is lower than the impurity concentration in a region heterojunction with the semiconductor substrate in the center of the bottom surface of the recess. Semiconductor device. In the hetero semiconductor layer,
The region heterojunction with the semiconductor substrate at the top of the convex part and the center of the bottom of the recess is N-type , and the impurity concentration of the region heterojunction with the semiconductor substrate at the center of the bottom of the recess is Lower than the impurity concentration of the region heterojunction with the semiconductor substrate at the upper end of the part,
6. The semiconductor device according to claim 5, wherein a region heterojunction with the semiconductor substrate at an end of the bottom surface of the recess is of a second conductivity type. The hetero semiconductor layer is P-type , and in the hetero semiconductor layer,
The impurity concentration of the region heterojunction with the semiconductor substrate at the center of the bottom surface of the recess is higher than the impurity concentration of the region heterojunction with the semiconductor substrate at the top of the protrusion.
6. The impurity concentration in a region heterojunction with the semiconductor substrate at the end of the recess bottom is higher than the impurity concentration in a region heterojunction with the semiconductor substrate in the center of the recess bottom. Semiconductor device. In the hetero semiconductor layer,
A region heterojunction with the semiconductor substrate at the upper end of the convex portion is N-type ,
The region heterojunction with the semiconductor substrate at the center of the recess bottom and the end of the recess bottom is P-type , and the impurity concentration of the region heterojunction with the semiconductor substrate at the center of the recess bottom is The semiconductor device according to claim 5, wherein an impurity concentration in an end portion of the bottom surface of the recess is lower than an impurity concentration in a region heterojunction with the semiconductor substrate. It said semiconductor substrate is a silicon carbide semiconductor device according to any one of claims 1 to 9, characterized in that it consists of any one of gallium nitride, and diamond. The hetero semiconductor layer, monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon-germanium, and semiconductor device according to any one of claims 1 to 10, characterized in that it consists either gallium arsenide .

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