CN114744038A - Low-on-resistance shielded gate trench field effect transistor and preparation method thereof - Google Patents
Low-on-resistance shielded gate trench field effect transistor and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The application relates to a low on-resistance shielded gate trench field effect transistor, comprising: the transistor comprises a substrate region, a drift region, a base region, a source region, a groove region, a drain electrode and a source electrode; the groove region comprises a shielding grid, a control grid, an insulating layer and a metal grid; the shielding grid is of a variable doping concentration structure, and the doping concentration of the shielding grid is gradually reduced from top to bottom. When the transistor is forward blocking, the shield gate has a lower doping concentration in the portion near the substrate region. Thus, the portion of the shield gate near the substrate region is more easily depleted at the same applied voltage, i.e., the portion near the substrate region has a thicker depletion layer width. The width of the depletion layer is inversely proportional to the capacitance of the parasitic capacitance, so that the parasitic capacitance formed between the shielding gate and the substrate region in the embodiment of the application is smaller, the parasitic capacitance formed between the shielding gate and the substrate region is weakened, and the switching speed of the device is further improved.
Description
Technical Field
The application relates to the technical field of power semiconductor devices, in particular to a shielded gate trench type field effect transistor with low on-resistance and a preparation method thereof.
Background
Shielded Gate Trench field effect transistors (SGTs) have been widely used in important low voltage fields such as power management. SGT has high channel density and simultaneously has better charge compensation effect. In addition, the shielding gate structure effectively isolates the coupling between the control gate and the drain, thereby remarkably reducing the transmission capacitance.
Therefore, the SGT has lower specific on resistance, smaller on loss and switching loss and higher operating frequency.
In the SGT device, due to the electric field concentration effect and the high polysilicon doping concentration of the shielding gate, when the SGT device is blocked in the forward direction, the electric charge flux emitted by the ionized donors in the voltage-withstanding region is concentrated at the corner of the shielding gate in the trench region, so that the peak voltage borne at the corner of the shielding gate in the trench region is higher, and the shielding gate in the trench region is also easily broken down at the corner.
Therefore, in the SGT device, in order to improve the voltage endurance capability at the corner of the trench-shielded gate, it is necessary to design a new type of shielded gate trench field effect transistor.
Disclosure of Invention
To overcome the problems in the related art, the present application provides a shielded gate trench field effect transistor with low on-resistance, including:
the transistor comprises a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a drain electrode 6 and a source electrode 7;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction, and the base region 3 and the source region 4 are sequentially arranged above the drift region 2;
the groove region 5 is arranged on the side of the substrate region 3 and is respectively connected with the drift region 2, the substrate region 3 and the source region 4;
the trench region 5 comprises a shielding gate 51, a control gate 52, an insulating layer 53 and a metal gate; the control gate 52 and the shielding gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the body region 3 and the source region 4 through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;
the shielding grid 51 is of a variable doping concentration structure, and the doping concentration of the shielding grid 51 is gradually reduced from top to bottom;
the source region 4 consists of an N-type source region 41 and a P-type source region 42; the P-type source region 42, the N-type source region 41 and the trench region 5 are sequentially arranged along the top surface of the body region 3, and the N-type source region 41 is connected to the control gate through the insulating layer 53;
the source 7 is disposed above the source region 4.
In one embodiment, the shielding grids 51 include a first level shielding grid 510, a second level shielding grid 511, and a third level shielding grid 512;
the doping concentration of the first-stage shielding gate 510 is a heavy doping concentration; the doping concentration of the second-stage shielding grid 511 is medium doping concentration; the doping concentration of the third-stage shielding gate 512 is low.
In one embodiment, the insulating layer 53 includes: a low dielectric coefficient sublayer 531 and an oxide sublayer 532;
the control gate 52 is connected to the body region 3 through the oxide sublayer 532;
the shielding gate 51 is connected to the drift region 2 through the low dielectric coefficient sublayer 531.
In one embodiment, the bottom surface of the low dielectric coefficient sublayer 531 is on the same plane as the bottom surface of the drift region 2.
In one embodiment, the doping concentrations of the P-type source region 42 and the N-type source region 41 are both heavy doping concentrations.
In one embodiment, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavily doped concentration;
the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is light doping concentration;
the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration;
the doping concentration of the source region 4 is heavy doping concentration; the doping concentration of the control gate 52 is a heavy doping concentration.
A second aspect of the present application provides a method for manufacturing a low on-resistance shielded gate trench field effect transistor, for manufacturing the low on-resistance shielded gate trench field effect transistor according to any one of the first aspect of the present application, including:
preparing a substrate region with a semiconductor material;
epitaxially forming a drift region on the substrate region;
forming a base region on the drift region in an ion implantation or diffusion mode;
etching a groove on the side face of the drift region;
depositing oxide, polysilicon, oxide, polysilicon and oxide in the trench in sequence to form an insulating layer, a shielding gate and a control gate; the shielding grid is a variable doping concentration structure;
forming a source region on the base region;
depositing metal on the source region to form a source electrode;
a drain is formed under the substrate region.
In one embodiment, the sequentially depositing oxide, polysilicon, oxide, polysilicon and oxide in the trench to form the insulating layer, the shielding gate and the control gate includes:
depositing a low dielectric coefficient medium, polysilicon and a low dielectric coefficient medium in the trench in sequence to form a low dielectric coefficient sublayer and a shielding grid;
depositing oxide, polysilicon and oxide on the low dielectric coefficient sublayer in sequence to form an oxide sublayer and a control gate;
the low dielectric coefficient sub-layer and the oxide sub-layer constitute the insulating layer.
In one embodiment, the sequentially depositing a low dielectric coefficient medium, polysilicon and a low dielectric coefficient medium in the trench to form a low dielectric coefficient sub-layer and a shield gate includes:
depositing a low dielectric coefficient medium, polysilicon and a low dielectric coefficient medium in the trench in sequence to form a low dielectric coefficient sublayer, a first-stage shielding gate, a second-stage shielding gate and a third-stage shielding gate; the doping concentration of the first-stage shielding grid is high doping concentration, the doping concentration of the second-stage shielding grid is medium doping concentration, and the doping concentration of the third-stage shielding grid is low doping concentration.
The technical scheme provided by the application can comprise the following beneficial effects:
since in a conventional SGT the shield gates are all heavily doped polysilicon, there is a parasitic capacitance between the depletion layer in the shield gate and the substrate region when the transistor is forward blocking. The parasitic capacitance slows down the switching speed of the transistor in the conventional transistor.
Therefore, in this application, the shielding gate is a variable doping concentration structure, and the doping concentration of the shielding gate is gradually decreased from top to bottom. When the transistor is forward blocking, the shield gate has a lower doping concentration in the portion near the substrate region. Thus, the portion of the shield gate near the substrate region is more easily depleted at the same applied voltage, i.e., the portion near the substrate region has a thicker depletion layer width. The width of the depletion layer is inversely proportional to the capacitance of the parasitic capacitance, so that the parasitic capacitance formed between the shielding gate and the substrate region in the embodiment of the application is smaller, the parasitic capacitance formed between the shielding gate and the substrate region is weakened, and the switching speed of the device is further improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application, as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.
Fig. 1 is a schematic structural diagram of a low on-resistance shielded gate trench field effect transistor according to an embodiment of the present application;
fig. 2 is a schematic flow chart illustrating a method for manufacturing a low on-resistance shielded gate trench field effect transistor according to an embodiment of the present application;
fig. 3 is another schematic flow chart of a method for manufacturing a low on-resistance shielded gate trench field effect transistor according to an embodiment of the present application.
Detailed Description
Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Example one
In the SGT device, due to the electric field concentration effect and the fact that the polycrystalline silicon doping concentration of the shielding gate is high, when the SGT device is blocked in the forward direction, parasitic capacitance formed between the shielding gate and a substrate region is large, and the switching speed of a transistor is reduced.
Therefore, in order to increase the switching speed of the SGT device, the parasitic capacitance formed between the shield gate and the substrate region needs to be weakened. The embodiment of the application provides a shielded gate trench field effect transistor with low on-resistance.
Fig. 1 is a schematic structural diagram of a shielded gate trench field effect transistor with low on-resistance according to an embodiment of the present application.
Referring to fig. 1, an embodiment of the present application illustrates a low on-resistance shielded gate trench field effect transistor including:
the transistor comprises a substrate region 1, a drift region 2, a base region 3, a source region 4, a groove region 5, a drain electrode 6 and a source electrode 7;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction, and the base region 3 and the source region 4 are sequentially arranged above the drift region 2;
the groove region 5 is arranged on the side of the substrate region 3 and is respectively connected with the drift region 2, the substrate region 3 and the source region 4;
the trench region 5 comprises a shielding gate 51, a control gate 52, an insulating layer 53 and a metal gate; the control gate 52 and the shielding gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the body region 3 and the source region 4 through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;
the shielding grid 51 is of a variable doping concentration structure, and the doping concentration of the shielding grid 51 is gradually reduced from top to bottom;
the source region 4 consists of an N-type source region 41 and a P-type source region 42; the P-type source region 42, the N-type source region 41 and the trench region 5 are sequentially arranged along the top surface of the body region 3, and the N-type source region 41 is connected to the control gate through the insulating layer 53;
the source 7 is disposed above the source region 4.
In the embodiment of the present application, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavy doping concentration; the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is light doping concentration; the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration; the doping concentration of the source region 4 is heavy doping concentration; the doping concentration of the control gate 52 is heavy doping concentration, and the doping type of the control gate 52 is P-type or N-type doping.
In the embodiment of the present application, the value range of the light doping concentration is 1 × 1015cm-3To 5X 1016cm-3(ii) a The value range of the medium doping concentration is 1 multiplied by 1017cm-3To 5X 1018cm-3(ii) a The value range of the heavy doping concentration is 1 multiplied by 1019cm-3To 5X 1020cm-3。
In the embodiment of the present application, the doping type of the shielding gate is P-type doping or N-type doping.
Further, the doping concentration of the doping type of the shielding gate may be a heavily doped concentration or a medium doped concentration.
Since in a conventional SGT, the shield gate is heavily doped polysilicon, when the transistor is forward blocked, a parasitic capacitance exists between the depletion layer in the shield gate and the substrate region. The parasitic capacitance slows down the switching speed of the transistor in the conventional transistor.
Therefore, in the embodiment of the present application, the shielding gate is a variable doping concentration structure, and the doping concentration of the shielding gate decreases from top to bottom. When the transistor is forward blocking, the shield gate has a lower doping concentration in the portion near the substrate region. Thus, the portion of the shield gate near the substrate region is more easily depleted at the same applied voltage, i.e., the portion near the substrate region has a thicker depletion layer width. The width of the depletion layer is inversely proportional to the capacitance of the parasitic capacitance, so that the parasitic capacitance formed between the shielding gate and the substrate region in the embodiment of the application is smaller, the parasitic capacitance formed between the shielding gate and the substrate region is weakened, and the switching speed of the device is further improved.
Example two
Based on the transistor described in the first embodiment, due to the electric field concentration effect, when the SGT device is forward-blocked, the electric charge flux generated by the ionized donors in the voltage-withstanding region is concentrated at the corner of the trench-region shield gate, which results in a higher peak voltage at the corner of the trench-region shield gate.
Therefore, in order to improve the voltage endurance of the SGT device, the electric field strength at the corners of the trench shielding gate needs to be weakened. The embodiment of the application provides a shielded gate trench field effect transistor with low on-resistance.
Fig. 1 is a schematic structural diagram of a shielded gate trench field effect transistor with low on-resistance according to an embodiment of the present application.
Referring to fig. 1, an embodiment of the present application illustrates a low on-resistance shielded gate trench field effect transistor including:
the transistor comprises a substrate region 1, a drift region 2, a body region 3, a source region 4, a trench region 5, a drain electrode 6 and a source electrode 7;
the drift region 2 is connected with the substrate region 1, the direction of the substrate region 1 pointing to the drift region 2 is taken as the upper direction, and the base region 3 and the source region 4 are sequentially arranged above the drift region 2;
the groove region 5 is arranged on the side of the substrate region 3 and is respectively connected with the drift region 2, the substrate region 3 and the source region 4;
the trench region 5 comprises a shielding gate 51, a control gate 52, an insulating layer 53 and a metal gate; the control gate 52 and the shielding gate 51 are sequentially arranged in the trench region 5 from top to bottom and are separated by the insulating layer 53; the control gate 52 is connected to the body region 3 and the source region 4 through the insulating layer 53, and the shield gate 51 is connected to the drift region 2 through the insulating layer 53;
in the embodiment of the present application, the shielding gate 51 is a variable doping concentration structure, and the doping concentration of the shielding gate 51 is gradually decreased from top to bottom.
Further, the shielding grids 51 comprise a first-stage shielding grid 510, a second-stage shielding grid 511 and a third-stage shielding grid 512; the doping concentration of the first-stage shielding gate 510 is a heavily doped concentration; the doping concentration of the second-stage shielding grid 511 is a medium doping concentration; the doping concentration of the third-stage shielding gate 512 is low.
In the embodiment of the present application, the third-stage shielding gate is disposed at the bottom of the shielding gate, near the substrate region, and the doping concentration of the third-stage shielding gate is a low doping concentration. Therefore, when the transistor is in forward blocking, the third stage shielding grid is easier to be depleted under the same applied voltage, and the width of a depletion layer is thicker. Therefore, the parasitic capacitance formed between the third-stage shielding gate and the substrate region is smaller, the parasitic capacitance formed between the shielding gate and the substrate region is weakened, and the switching speed of the device is further improved.
The source region 4 consists of an N-type source region 41 and a P-type source region 42; the P-type source region 42, the N-type source region 41 and the trench region 5 are sequentially arranged along the top surface of the body region 3, and the N-type source region 41 is connected to the control gate through the insulating layer 53;
the source 7 is disposed above the source region 4.
It should be noted that the doping concentrations and the arrangement manners of the substrate region 1, the drift region 2, the body region 3, the source region 4 and the trench region 5 in the embodiment of the present application are the same as those in the first embodiment, and are not described herein again.
In the embodiment of the application, in order to improve the voltage endurance of the SGT device, the electric field strength borne by the corner of the trench shielding gate needs to be weakened. Further, the insulating layer 53 includes: a low dielectric coefficient sublayer 531 and an oxide sublayer 532. Wherein the control gate 52 is connected to the body region 3 through the oxide sub-layer 532; the shielding gate 51 is connected to the drift region 2 through the low dielectric coefficient sublayer 531. The bottom surface of the low dielectric coefficient sublayer 531 is on the same plane as the bottom surface of the drift region 2.
In the embodiment of the application, the shielding grid is connected with the drift region through the low dielectric coefficient sublayer. Because under the same transverse voltage, the low dielectric coefficient sub-layer can bear certain transverse voltage drop compared with the oxide sub-layer, when the transistor is blocked in the forward direction, the low dielectric coefficient sub-layer can inhibit the transverse depletion effect between the drift region and the shielding gate, further the electric field intensity at the corner of the shielding gate in the trench region is weakened, and the voltage resistance of the trench region at the corner is improved.
EXAMPLE III
Corresponding to the shielded gate trench field effect transistor with low on-resistance shown in the first embodiment, the present application also provides a method for manufacturing a shielded gate trench field effect transistor with low on-resistance and a corresponding embodiment.
Fig. 2 is a schematic flow chart illustrating a method for manufacturing a shielded gate trench field effect transistor according to an embodiment of the present application.
As shown in fig. 2, the method for manufacturing a low on-resistance shielded gate trench field effect transistor according to the embodiment of the present application includes the following steps:
201. preparing a substrate region with a semiconductor material;
in the embodiment of the present application, the substrate region is made of an N-type heavily doped semiconductor material, that is, the doping type of the substrate region is N-type doping, and the doping concentration of the substrate region is a heavily doped concentration.
202. Epitaxially forming a drift region on the substrate region;
in the embodiment of the present application, different epitaxy processes may be adopted according to actual requirements, including but not limited to: vapor Phase Epitaxy (VPE) or Chemical Vapor Deposition (CVD).
203. Forming a base region on the drift region in an ion implantation or diffusion mode;
the ion implantation process is a process of doping silicon materials, in the practical application process, a power device product is placed at one end of an ion implanter, and a doping ion source is arranged at the other end of the ion implanter. At one end of the doping ion source, doping body atoms are ionized to carry certain charges, the charges are added to the super high speed by an electric field, penetrate through the surface layer of a product, and the doping atoms are injected into a power device by utilizing the momentum of the atoms to form a doping area.
The diffusion process is a process of doping pure impurity atoms on the surface of the silicon material, and in the practical application process, diborane or phosphine is usually used as an ion source, and the pure impurity atoms are doped on the surface of the silicon material by adopting an intermittent diffusion or displacement diffusion mode.
It should be noted that, in the embodiments of the present application, the preparation method adopted for the substrate region is not strictly limited, and in an actual process, the preparation of the substrate region may be completed by selecting the above different processes according to actual requirements.
204. Etching a groove on the side face of the drift region;
in the embodiment of the application, a trench is etched on one side of the drift region through a photoetching process, and the residual photoresist is removed through wet etching or dry etching.
205. Depositing an oxide, polysilicon, an oxide, polysilicon and an oxide in the trench in sequence to form an insulating layer, a shielding gate and a control gate;
preferably, in this embodiment of the present application, an oxide, a heavily doped polysilicon, an oxide, and a heavily doped polysilicon are sequentially deposited in the trench to form the shield gate, the insulating layer, and the control gate.
In the embodiment of the present application, the doping concentration of the shielding gate decreases gradually from top to bottom, that is, the doping concentration of the portion of the shielding gate close to the control gate is the highest, and the doping concentration of the portion of the shielding gate close to the substrate region is the lowest.
206. Forming a source region on the base region;
207. depositing metal on the source region to form a source electrode;
208. a drain is formed under the substrate region.
Since in a conventional SGT, the shield gate is heavily doped polysilicon, when the transistor is forward blocked, a parasitic capacitance exists between the depletion layer in the shield gate and the substrate region. The parasitic capacitance slows down the switching speed of the transistor in the conventional transistor.
Therefore, in the embodiment of the present application, the shielding gate is a variable doping concentration structure, and the doping concentration of the shielding gate is gradually decreased from top to bottom. When the transistor is forward blocking, the shield gate has a lower doping concentration in the portion near the substrate region. Thus, the portion of the shield gate near the substrate region is more easily depleted at the same applied voltage, i.e., the portion near the substrate region has a thicker depletion layer width. The width of the depletion layer is inversely proportional to the capacitance of the parasitic capacitance, so that the parasitic capacitance formed between the shielding gate and the substrate region in the embodiment of the application is smaller, the parasitic capacitance formed between the shielding gate and the substrate region is weakened, and the switching speed of the device is further improved.
Example four
Corresponding to the low on-resistance shielded gate trench field effect transistor shown in the second embodiment, the present application also provides a method for manufacturing a low on-resistance shielded gate trench field effect transistor and a corresponding embodiment.
Fig. 3 is a schematic flow chart illustrating a method for manufacturing a shielded gate trench field effect transistor with low on-resistance according to an embodiment of the present application.
As shown in fig. 3, the method comprises the following steps:
301. preparing a substrate region with a semiconductor material;
302. epitaxially forming a drift region on the substrate region;
303. forming a base region on the drift region in an ion implantation or diffusion mode;
304. etching a groove on the side face of the drift region;
305. depositing a low dielectric coefficient medium, polysilicon and a low dielectric coefficient medium in the trench in sequence to form a low dielectric coefficient sublayer, a first-stage shielding gate, a second-stage shielding gate and a third-stage shielding gate;
in the embodiment of the present application, the doping concentration of the first-stage shielding gate is a high doping concentration, the doping concentration of the second-stage shielding gate is a medium doping concentration, and the doping concentration of the third-stage shielding gate is a low doping concentration.
306. Depositing an oxide, polysilicon and an oxide on the low dielectric coefficient sublayer in sequence to form an oxide sublayer and a control gate;
in an embodiment of the present application, the low dielectric coefficient sub-layer and the oxide sub-layer constitute the insulating layer.
307. Forming a source region on the base region;
308. depositing metal on the source region to form a source electrode;
309. a drain is formed under the substrate region.
In the embodiment of the application, in order to improve the voltage endurance of the SGT device, the electric field strength borne by the corner of the trench shielding gate needs to be weakened. Further, the control gate is connected with the base region through the oxide sub-layer; the shielding grid is connected with the drift region through the low dielectric coefficient sublayer. The bottom surface of the low dielectric coefficient sublayer and the bottom surface of the drift region are on the same plane.
In the embodiment of the application, the shielding grid is connected with the drift region through the low dielectric coefficient sublayer. Under the same transverse voltage, the low dielectric coefficient sublayer can bear a certain transverse voltage drop compared with the oxide sublayer, so when the transistor is blocked in the forward direction, the low dielectric coefficient sublayer can inhibit the transverse depletion effect between the drift region and the shielding gate, further weaken the electric field intensity at the corner of the shielding gate of the trench region, and improve the voltage withstanding capability of the trench region at the corner.
Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or improvements to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (9)
1. A low on-resistance shielded gate trench field effect transistor comprising:
the transistor comprises a substrate region (1), a drift region (2), a base region (3), a source region (4), a trench region (5), a drain electrode (6) and a source electrode (7);
the drift region (2) is connected with the substrate region (1), the direction of the substrate region (1) pointing to the drift region (2) is taken as the upper direction, and the base region (3) and the source region (4) are sequentially arranged above the drift region (2);
the groove region (5) is arranged on the side of the substrate region (3) and is respectively connected with the drift region (2), the substrate region (3) and the source region (4);
the trench region (5) comprises a shielding grid (51), a control grid (52), an insulating layer (53) and a metal grid; the control grid (52) and the shielding grid (51) are sequentially arranged in the groove region (5) from top to bottom and are separated by the insulating layer (53); the control grid (52) is respectively connected with the base region (3) and the source region (4) through the insulating layer (53), and the shielding grid (51) is connected with the drift region (2) through the insulating layer (53);
the shielding grid (51) is of a variable doping concentration structure, and the doping concentration of the shielding grid (51) is gradually reduced from top to bottom;
the source region (4) consists of an N-type source region (41) and a P-type source region (42); the P-type source region (42), the N-type source region (41) and the trench region (5) are sequentially arranged along the top surface of the base region (3), and the N-type source region (41) is connected with the control gate through the insulating layer (53);
the source electrode (7) is arranged above the source region (4).
2. The low on-resistance shielded gate trench field effect transistor of claim 1,
the shielding grid (51) comprises a first-stage shielding grid (510), a second-stage shielding grid (511) and a third-stage shielding grid (512);
the doping concentration of the first-stage shielding gate (510) is heavy doping concentration; the doping concentration of the second-stage shielding grid (511) is a medium doping concentration; the doping concentration of the third-stage shielding grid (512) is low.
3. A low on-resistance shielded gate trench field effect transistor according to claim 1 wherein the insulating layer (53) comprises: a low dielectric coefficient sublayer (531) and an oxide sublayer (532);
the control gate (52) is connected with the body region (3) through the oxide sub-layer (532);
the shielding grid (51) is connected with the drift region (2) through the low dielectric coefficient sublayer (531).
4. The low on-resistance shielded gate trench field effect transistor of claim 3,
the bottom surface of the low dielectric coefficient sublayer (531) and the bottom surface of the drift region (2) are on the same plane.
5. The low on-resistance shielded gate trench field effect transistor of claim 1, wherein the doping concentration of the P-type source region (42) and the N-type source region (41) are both heavily doped.
6. The low on-resistance shielded gate trench field effect transistor of claim 1 wherein the doping type of the substrate region (1) is N-type doping and the doping concentration of the substrate region (1) is heavily doped;
the doping type of the drift region (2) is N-type doping, and the doping concentration of the drift region (2) is light doping concentration;
the doping type of the substrate region (3) is P-type doping, and the doping concentration of the substrate region (3) is medium doping concentration;
the doping concentration of the source region (4) is heavy doping concentration; the doping concentration of the control gate (52) is a heavy doping concentration.
7. A method for manufacturing a low on-resistance shielded gate trench field effect transistor, for manufacturing the low on-resistance shielded gate trench field effect transistor of any one of claims 1 to 6, comprising:
preparing a substrate region with a semiconductor material;
epitaxially forming a drift region on the substrate region;
forming a base region on the drift region in an ion implantation or diffusion mode;
etching a groove on the side face of the drift region;
depositing oxide, polysilicon, oxide, polysilicon and oxide in the trench in sequence to form an insulating layer, a shielding gate and a control gate; the shielding grid is a variable doping concentration structure;
forming a source region on the base region;
depositing metal on the source region to form a source electrode;
a drain is formed under the substrate region.
8. The method of claim 7, wherein depositing oxide, polysilicon, oxide, polysilicon and oxide in the trench sequentially to form the insulating layer, the shield gate and the control gate comprises:
depositing a low dielectric coefficient medium, polysilicon and a low dielectric coefficient medium in the trench in sequence to form a low dielectric coefficient sublayer and a shielding gate;
depositing an oxide, polysilicon and an oxide on the low dielectric coefficient sublayer in sequence to form an oxide sublayer and a control gate;
the low dielectric coefficient sub-layer and the oxide sub-layer constitute the insulating layer.
9. The method of claim 8, wherein depositing a low-k dielectric, polysilicon, and a low-k dielectric in the trench in sequence to form a low-k sub-layer and a shield gate comprises:
depositing a low dielectric coefficient medium, polysilicon and a low dielectric coefficient medium in the trench in sequence to form a low dielectric coefficient sublayer, a first-stage shielding gate, a second-stage shielding gate and a third-stage shielding gate; the doping concentration of the first-stage shielding grid is high doping concentration, the doping concentration of the second-stage shielding grid is medium doping concentration, and the doping concentration of the third-stage shielding grid is low doping concentration.
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