CN117423749A - SiC MOSFET device capable of improving short circuit capability - Google Patents
SiC MOSFET device capable of improving short circuit capability Download PDFInfo
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- CN117423749A CN117423749A CN202311746831.9A CN202311746831A CN117423749A CN 117423749 A CN117423749 A CN 117423749A CN 202311746831 A CN202311746831 A CN 202311746831A CN 117423749 A CN117423749 A CN 117423749A
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- 239000012535 impurity Substances 0.000 claims description 3
- 230000001419 dependent effect Effects 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 abstract description 48
- 229910010271 silicon carbide Inorganic materials 0.000 abstract description 46
- 239000004065 semiconductor Substances 0.000 description 13
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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Abstract
The invention provides a SiC MOSFET device for improving short circuit capability, belongs to the technical field of silicon carbide (SiC) power devices, and provides a vertical plane SiC MOSFET device with a piecewise gradual change doping epitaxial structure, wherein a drift layer is divided into a first drift layer, a second drift layer and a third drift layer from top to bottom, the doping concentrations of the first drift layer, the second drift layer and the third drift layer are respectively gradual change, and the contact positions of different drift layers have the same doping concentration. According to the SiC MOSFET device with the piecewise graded doping epitaxial structure, the on resistance of the device in the working state is reduced by utilizing the high doping close to the channel region, the potential distribution of the device in short circuit is adjusted by the graded doped drift layer, and the current density in short circuit is reduced, so that the short circuit capacity of the SiC MOSFET device is improved.
Description
Technical Field
The invention relates to a SiC MOSFET device for improving short circuit capability, and belongs to the technical field of silicon carbide (SiC) power devices.
Background
The SiC power MOSFET is a unipolar voltage control device, is mainly applied to a power supply and a power processing system, and plays a role in controlling electric energy conversion. SiC devices are easier to achieve high voltage, low loss, and high power density than conventional Si-based power devices, and thus are becoming the mainstream of the market.
The main high power silicon carbide MOSFETs in the market today are mainly dominated by vertical plane MOSFETs of 650V to 2000V. Fig. 5 is a schematic structure of a conventional vertical plane MOSFET. The structure shown in fig. 5 includes an N-type semiconductor substrate 31, an N-type buffer semiconductor layer 30 and an N-type drift semiconductor layer 29, a selective P-type barrier semiconductor region 27 formed by an ion implantation process, a heavily doped N-type contact semiconductor region 26, a heavily doped P-type contact semiconductor region 28, a gate insulating layer 25, a polysilicon gate electrode 23 as a gate electrode, a planar inversion channel layer 34 formed, an isolation medium 22 formed on top of the gate electrode before forming the ohmic contact layer 24, a thick top metal layer 21, and a bottom metal layer 33 having ohmic contact through a back ohmic contact layer 32.
However, during the short circuit, the vertical planar SiC MOSFET burns out faster, i.e., has a shorter short time, because the device turns on the planar inversion channel layer 34 directly below the top metal layer 21 and has a higher short current density.
In the conventional process, the reduction of the short-circuit current density of the SiC MOSFET device is achieved by increasing the on-resistance of the device, but increasing the on-resistance results in an increase in power consumption when the device is operating normally. In order to achieve the effects of both power consumption and short-circuit capability of the SiC MOSFET device, the invention provides a structure of the SiC MOSFET device, which can reduce the on-resistance of the device in a normal working state and improve the short-circuit capability of the device.
Disclosure of Invention
Aiming at the problems that the current SiC MOSFET device is high in short-circuit current density and easy to burn out in a short-circuit time, the invention provides the SiC MOSFET device structure which can improve the short-circuit capacity of the device while reducing the on-resistance of the device in a normal working state.
The technical scheme of the invention is as follows:
the technical scheme of the invention particularly provides a vertical plane SiC MOSFET device with a piecewise graded doping epitaxial structure from the consideration of the doping concentration distribution of a drift layer of the SiC MOSFET device. And the on-resistance of the device in normal operation is reduced by using the high doped drift layer close to the channel, and the potential distribution in short circuit is adjusted by using the graded doping concentration distribution, so that the short circuit current density of the device is reduced, and the short circuit capability of the SiC MOSFET device is improved.
The SiC MOSFET device for improving the short circuit capability comprises a drain electrode, an N-type SiC substrate and an N-type SiC epitaxial layer from bottom to top, wherein an oxide layer and a polysilicon gate are arranged above the N-type SiC epitaxial layer, source electrodes are arranged on two sides of the oxide layer above the N-type SiC epitaxial layer, and the source electrodes are not contacted with the oxide layer; the N-type SiC epitaxial layer comprises a third drift layer, a second drift layer and a first drift layer from bottom to top, a P well region is arranged in the first drift layer, and an N+ type doped region and a P+ type doped region are arranged in the P well region; the P well region is arranged at two ends of the upper part and the inner part of the first drift layer, the oxide layer is arranged above the first drift layer and covers the first drift layer, the P well region and part of the N+ type doped region, and the source electrode is arranged above the first drift layer and covers the P+ type doped region and part of the N+ type doped region; the N+ type doped region is connected with the P+ type doped region and is positioned at the inner side of the corner of the P well region; the oxide layer and the polysilicon gate are sequentially overlapped in the middle of the surface of the first drift layer;
the doping concentrations in the first drift layer, the second drift layer and the third drift layer are respectively graded.
Preferably, the first drift layer, the second drift layer, and the third drift layer are doped with the same impurity.
Preferably, the thickness of the first drift layer is 10% -20% of the total drift layer thickness, and the thickness of the second drift layer is 10% ± 5% of the total drift layer thickness.
Further preferably, the thickness of the first drift layer ranges from 1 to 2 μm.
Preferably, the first drift layer is doped gradually from top to bottom, and the doping concentration is increased gradually; the initial concentration of the first drift layer depends on the design pressure-resistant requirement, and the drift layer doping concentration corresponding to the pressure-resistant traditional structure or the drift layer doping concentration of the user base structure is used as a reference to be adjusted, wherein the adjustment range is within +/-50%. The second drift layer is doped gradually from top to bottom, and the doping concentration is reduced gradually; the third drift layer is doped gradually from top to bottom, the doping concentration change trend is dependent on the doping concentration of the second drift layer, and when the bottom concentration of the second drift layer is lower than the top concentration of the first drift layer, the doping concentration of the third drift layer is increased gradually; when the bottom concentration of the second drift layer is higher than the top concentration of the first drift layer, the doping concentration of the third drift layer is gradually reduced; the doping concentration at the contact of the first drift layer and the second drift layer is the same; the doping concentration at the contact of the second drift layer and the third drift layer is the same.
Preferably, the doping concentration of the first drift layer is 5×10 15 ～1.5×10 16 cm -3 The doping concentration of the second drift layer is 4×10 15 ～1.5×10 16 cm -3 The doping concentration of the third drift layer is 4×10 15 ～8×10 15 cm -3 Between them.
Preferably, the doping concentration of the first drift layer, the second drift layer and the third drift layer is linear gradual change doping or multi-layer stepwise change doping, the number of steps is at least two, and the concentration in the same step is the same.
The existing drift layer integral gradual change doping can increase the breakdown voltage of the device and reduce the on-resistance in the working state of the device, but has larger short-circuit current in a high-voltage short-circuit state, is easy to burn in a shorter short-circuit time and has poorer short-circuit capability. Compared with the existing integral gradual change doping design, the SiC MOSFET device provided by the invention can realize adjustment of internal potential of the device in a high-voltage state while increasing withstand voltage and reducing on-resistance, reduce saturated current in the high-voltage state, further reduce current density in short circuit and improve short circuit capacity of the device.
The invention has the beneficial effects that:
the invention is based on the high doping near the drift layer of the channel region, so that the on-resistance of the SiC MOSFET is reduced when the SiC MOSFET works normally, the power consumption is reduced when the SiC MOSFET works normally, and the advantage is obvious in the low-voltage field.
The invention adopts a sectional doping epitaxial structure, adjusts the potential distribution of the SiC MOSFET during short circuit, can reduce the current density of the SiC MOSFET during high-voltage short circuit, and enhances the short circuit capability of the device.
Drawings
Fig. 1 is a schematic structural view of a SiC MOSFET device of the present invention;
the device comprises a polysilicon gate electrode 1, a polysilicon gate electrode 2, a source electrode 3, an oxide layer, a 4, N+ type doped region, a 5, P+ type doped region, a 6, P well region, a 7, a first drift layer 8, a second drift layer 9, a third drift layer 10, a SiC substrate 11 and a drain electrode;
FIG. 2a is a schematic view showing the doping concentration distribution of the drift layer according to the present invention;
FIG. 2b is a doping concentration profile of the drift layer of the present invention;
fig. 3 is a graph showing comparison of the output characteristics of the SiC MOSFET of example 1 with respect to the comparative example for improving the short circuit capability;
FIG. 4 is a graph comparing junction temperature versus time during shorting of the SiC MOSFET of example 1 with the comparative example;
fig. 5 is a schematic diagram of a conventional vertical plane MOSFET device;
the semiconductor device comprises a substrate, a top metal layer, a 22, an isolation medium, a 23, a polysilicon gate, a 24, an ohmic contact layer, a 25, a gate insulating layer, a 26, a heavily doped N-type contact semiconductor region, a 27, a P-type barrier semiconductor region, a 28, a heavily doped P-type contact semiconductor region, a 29, an N-type drift semiconductor layer, a 30, an N-type buffer semiconductor layer, a 31, an N-type semiconductor substrate, a 32, a back ohmic contact layer, a 33, a bottom metal layer, a 34 and a planar inversion channel layer, wherein the substrate is formed by the substrate;
fig. 6 is a graph showing the potential distribution in the short-circuited state of example 1 and comparative example.
Detailed Description
The invention will now be further illustrated by way of example, but not by way of limitation, with reference to the accompanying drawings.
Example 1
The device of the invention utilizes a piecewise graded doped epitaxial structure, and improves the short circuit capability of the device while reducing the on-resistance of the device in normal operation. As shown in fig. 1, the SiC MOSFET device for improving the short circuit capability according to the embodiment of the present invention includes, from bottom to top, a drain electrode 11, an N-type SiC substrate 10, and an N-type SiC epitaxial layer, an oxide layer 3 is disposed above the N-type SiC epitaxial layer, a polysilicon gate 1, and source electrodes 2 are disposed on two sides of the oxide layer above the N-type SiC epitaxial layer, where the source electrodes do not contact with the oxide layer; the N-type SiC epitaxial layer comprises a third drift layer 9, a second drift layer 8 and a first drift layer 7 from bottom to top, a P well region 6 is arranged in the first drift layer, and an N+ type doped region 4 and a P+ type doped region 5 are arranged in the P well region; the P well region is arranged at two ends of the upper part and the inner part of the first drift layer, the oxide layer is arranged above the first drift layer and covers the first drift layer, the P well region and part of the N+ type doped region, and the source electrode is arranged above the first drift layer and covers the P+ type doped region and part of the N+ type doped region; the N+ type doped region is connected with the P+ type doped region and is positioned at the inner side of the corner of the P well region; the oxide layer and the polysilicon gate are sequentially overlapped in the middle of the surface of the first drift layer;
the doping concentrations in the first drift layer, the second drift layer and the third drift layer are respectively graded, and the doping impurities in the first drift layer, the second drift layer and the third drift layer are the same.
The first drift layer 7 is doped gradually from top to bottom, and the doping concentration is increased gradually. The doping concentration of the first drift layer 7 is from 7.5X10 15 cm -3 To 1.2X10 16 cm -3 The linear change avoids the advanced breakdown of the device caused by too large concentration and simultaneously avoids the excessively high on-resistance caused by too small concentration. The thickness of the first drift layer 7 is 1.5 mu m, so that the degradation of the short-circuit capability of the device caused by too large thickness under high doping concentration is avoided, and meanwhile, the process difficulty caused by too small thickness is avoided.
The second drift layer 8 is doped gradually from top to bottom, and the doping concentration is reduced gradually, and the doping concentration at the contact position of the first drift layer 7 and the second drift layer 8 is the same. I.e. the maximum doping concentration of the second drift layer 8 is the same as the maximum doping concentration of the first drift layer 7. In this example, the second drift layer 8 has a thickness of 1 μm and a doping concentration of 1.2X10 16 cm -3 Up to 5X 10 15 cm -3 Linear variation.
The third drift layer 9 is doped gradually from top to bottom, and the doping concentration at the contact position of the second drift layer 8 and the third drift layer 9 is the same. In this example, the thickness of the third drift layer 9 is 8.5 μm, and the doping concentration is from 5×10 15 cm -3 To 6.7X10 15 cm -3 Linear variation. The doping concentration profile of this embodiment is shown in fig. 2a and 2 b.
Example 2:
a SiC MOSFET device with improved shorting capability has a structure as described in example 1, except that the first drift layer 7 has a doping concentration of from 5×10 15 cm -3 To 1.5X10 16 cm -3 The first drift layer has a thickness of 2 μm and the second drift layer 8 has a doping concentration of 1.5X10 16 cm -3 Up to 4X 10 15 cm -3 Linearly varying the doping concentration of the third drift layer 9 from 4×10 15 cm -3 Up to 8X 10 15 cm -3 Linear variation.
Example 3:
a SiC MOSFET device with improved shorting capability was constructed as described in example 1, except that the first drift layer had a thickness of 1 μm.
Example 4:
a SiC MOSFET device with improved shorting capability is constructed as described in example 1, except that the doping concentration of the first drift layer, the second drift layer, and the third drift layer are doped in multiple steps, the number of steps is three, and the concentration in the same step is the same.
Comparative example:
comparative example provides a SiC MOSFET device differing from example 1 in that the drift layer employs a uniform doping concentration of 8×10 15 cm -3 The thickness was 11. Mu.m. The comparison is as follows:
in embodiment 1, the upper sides of the first drift layer 7 and the second drift layer 8 are closer to the on channel, the on resistance in the device operation state is more greatly affected, and the on resistance in the device operation state can be reduced by increasing the concentration. The rapid decrease of the doping concentration of the second drift layer 8 and the slow increase of the doping concentration of the third drift layer 9 can adjust the potential distribution when the device is short-circuited, reduce the current density when the device is short-circuited at high voltage, and improve the short-circuit capability of the device. The potential distribution in the short-circuited state of example 1 and comparative example is shown in fig. 6.
Referring to fig. 3, it can be seen that when the first drift layer 7 is employed, the doping concentration is 7.5×10 15 cm -3 To 1.2X10 16 cm -3 Linearly varying, the doping concentration of the second drift layer 8 is 1.2X10 16 cm -3 Up to 5X 10 15 cm -3 Linear variation and doping concentration of the third drift layer 9 of 5×10 15 cm -3 To 6.7X10 15 cm -3 After linear change, the on-state current is obviously improved, and the on-state resistance is reduced in the working state of the device.
Referring to fig. 4, it can be seen that when the first drift layer 7 is employed, the doping concentration is 7.5×10 15 cm -3 To 1.2X10 16 cm -3 Linearly varying, the doping concentration of the second drift layer 8 is 1.2X10 16 cm -3 Up to 5X 10 15 cm -3 Linear variation and doping concentration of the third drift layer 9 of 5×10 15 cm -3 To 6.7X10 15 cm -3 After the linear change, the junction temperature rising speed in the short circuit state of the device is reduced, and the short circuit capacity of the device is improved.
This embodiment 1 is a 1200V SiC MOSFET device, and the drift layer thickness and doping concentration profile can be selected to achieve the same effect according to different withstand voltage requirements. In particular, the concentration of the first drift layer needs to be selected in consideration of the voltage withstanding requirement, and the concentration of the top of the first drift layer is adjusted by taking the doping concentration of the drift layer corresponding to the voltage withstanding traditional structure or the doping concentration of the drift layer of the user base structure as a reference, wherein the adjustment range is within +/-50%.
The above embodiments are only used to further illustrate a SiC MOSFET device for improving the short-circuit capability of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent variation and modification made to the above embodiments according to the technical substance of the present invention falls within the scope of the technical solution of the present invention.
Claims (7)
1. The SiC MOSFET device is characterized by comprising a drain electrode, an N-type SiC substrate and an N-type SiC epitaxial layer from bottom to top, wherein an oxide layer and a polysilicon grid are arranged above the N-type SiC epitaxial layer, and source electrodes are arranged on two sides of the oxide layer above the N-type SiC epitaxial layer; the N-type SiC epitaxial layer comprises a third drift layer, a second drift layer and a first drift layer from bottom to top, a P well region is arranged in the first drift layer, and an N+ type doped region and a P+ type doped region are arranged in the P well region; the P well region is arranged at two ends of the upper part and the inner part of the first drift layer, the oxide layer is arranged above the first drift layer and covers the first drift layer, the P well region and part of the N+ type doped region, and the source electrode is arranged above the first drift layer and covers the P+ type doped region and part of the N+ type doped region;
the doping concentrations in the first drift layer, the second drift layer and the third drift layer are respectively graded.
2. The SiC MOSFET device of claim 1, wherein the first drift layer, the second drift layer, and the third drift layer are doped with the same impurity.
3. The SiC MOSFET device of claim 1 in which the first drift layer has a thickness of 10% -20% of the total drift layer thickness and the second drift layer has a thickness of 10% ± 5% of the total drift layer thickness.
4. The SiC MOSFET device of claim 3, wherein the first drift layer has a thickness in the range of 1-2 μm.
5. The SiC MOSFET device of claim 1, wherein the first drift layer is graded doped from top to bottom with a doping concentration that increases gradually; the second drift layer is doped gradually from top to bottom, and the doping concentration is reduced gradually; the third drift layer is doped gradually from top to bottom, the doping concentration change trend is dependent on the doping concentration of the second drift layer, and when the bottom concentration of the second drift layer is lower than the top concentration of the first drift layer, the doping concentration of the third drift layer is increased gradually; when the bottom concentration of the second drift layer is higher than the top concentration of the first drift layer, the doping concentration of the third drift layer is gradually reduced; the doping concentration at the contact of the first drift layer and the second drift layer is the same; the doping concentration at the contact of the second drift layer and the third drift layer is the same.
6. The SiC MOSFET device of claim 1 wherein the doping concentration of the first drift layer is between 5 x 10 15 ～1.5×10 16 cm -3 The doping concentration of the second drift layer is 4×10 15 ～1.5×10 16 cm -3 The doping concentration of the third drift layer is 4×10 15 ～8×10 15 cm -3 Between them.
7. The SiC MOSFET device of claim 1, wherein the doping concentrations of the first drift layer, the second drift layer, and the third drift layer are linearly graded doping; or doping multiple steps, wherein the number of the steps is at least two, and the concentration in the same step is the same.
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