JP2005064429A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-cost semiconductor device using an FZ bulk wafer, which improves both of high-speed/low-loss characteristics and soft recovery characteristics simultaneously by suppressing increase of dV/dt at the time of reverse recovery and suppressing waveform oscillation at the time of reverse recovery. <P>SOLUTION: At least one of P-type impurities, e.g. aluminium, gallium, indium and zinc whose diffusion coefficient is larger than boron, is diffused at a temperature of 1200°C or below from one principal plane and the other principal plane of the FZ wafer containing phosphorus, an N-type impurity, so as to have a concentration lower than that of the phosphorus, thereby allowing concentration at an N<SP>-</SP>drift layer to be compensated to obtain a formation wherein a net doping concentration is lower than the phosphorus concentration. Thus, a structure can be readily formed using the FZ wafer, wherein a peak impurity concentration resides proximate to a center of a substrate and is decreasingly graded toward both of the principal planes of the substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a diode or IGBT having not only high speed and low loss but also soft recovery characteristics, and a method for manufacturing the same.

  In the pin diode (conventional example B) shown in FIG. 16 that is widely used at present, a large reverse current flows transiently through the diode when switching from the on state to the off state (during reverse recovery). Although this is called reverse recovery current, a larger electric loss is generated in the diode during reverse recovery than in a steady state. It is strongly required as a characteristic of the diode to reduce this loss and increase the speed. Furthermore, a higher electrical duty is generated in the diode during reverse recovery than in the steady state. Increasing the steady-state current flowing through the diode or increasing the blocking voltage increases this electrical duty, which can destroy the diode. In order to guarantee high reliability in a diode for power use, it is strongly required to make the reverse recovery tolerance much larger than the rating.

Currently, minority carrier lifetime control using heavy metal diffusion, electron beam irradiation, or the like is widely applied as a measure for improving reverse recovery characteristics and withstand capability of pin diodes. In other words, by reducing the lifetime, the total carrier concentration in the steady state is reduced, so the carrier concentration that is swept away by the expansion of the space charge region during reverse recovery decreases, and the reverse recovery time and reverse recovery peak current The reverse recovery charge can be reduced and the reverse recovery loss can be reduced. In addition, the electric field strength during reverse recovery due to the holes passing through the space charge region is also alleviated by the decrease in the hole concentration, so that the duty is reduced and the reverse recovery tolerance is improved.
On the other hand, soft recovery of the diode is also an important issue. In recent years, due to environmental problems and the like, it has been required to reduce electromagnetic noise generated from power electronics equipment, and one countermeasure is to suppress the cause of noise such as oscillation by soft recovery of diode reverse recovery. As a means for soft recovery, it is preferable to reduce the minority carrier injection efficiency from the anode side. Typical examples of this means include Merged Pin / Schottky Diode (MPS) (see Non-Patent Document 1) and Soft and Fast recovery Diode (SFD) (see Non-Patent Document 2). In this MPS diode, the anode layer of the pin diode is composed of a p region and a Schottky region.

There is a trade-off relationship between the high speed / low loss characteristics and the soft recovery characteristics of the reverse recovery operation (see Non-Patent Document 3). That is, in order to achieve soft recovery, a large amount of minority carriers are accumulated particularly on the cathode side, and when the space charge region expands from the anode side to the cathode side during reverse recovery, the cathode current is left as much as possible. Decrease rate dir / dt is reduced. However, reverse recovery loss increases, and it takes time to complete reverse recovery. On the other hand, reverse recovery at high speed and low loss mean that minority carriers that accumulate in the drift layer at the time of on-state are reduced, so that it becomes so-called snappy reverse recovery (hard recovery), and both voltage and current are It may oscillate.
For example, as shown in Non-Patent Document 6, if the excess carriers in the n ⁻ drift layer disappear before the reverse recovery process ends, dir / dt increases rapidly, and therefore the anode-cathode voltage of the diode Vak also increases accordingly, and a surge voltage is generated. Since this surge voltage causes electric field concentration inside the element, it causes breakdown of the element. Furthermore, the surge voltage becomes a trigger and becomes a vibration waveform. This vibration waveform becomes a source of radiation noise from a power converter such as an inverter. Therefore, at the time of reverse recovery, surplus carriers must be prevented from disappearing in the middle of the diode reaching the steady state of current blocking.

There is also a method to reduce the reverse recovery loss by reducing the reverse recovery charge by thinning the n ⁻ drift layer within the range that does not impair the device breakdown voltage, but it reduces the cathode-side stored carriers at the time of reverse recovery. Since carriers easily disappear during reverse recovery, oscillation tends to occur as a result. Therefore, with the current method, it is becoming extremely difficult to reduce reverse recovery loss while maintaining soft recovery characteristics.
One typical example of a method for improving the trade-off is to combine the aforementioned low injection structure with a reduction in drift layer thickness. By reducing the injection efficiency of minority carriers, the cathode side surplus carriers are increased to achieve soft recovery, and if the drift layer thickness is reduced, soft recovery can be achieved and high-speed reverse recovery can be achieved. There is also a method of improving soft recovery by local control of lifetime by irradiation with light ion particle beams such as protons and helium ions. However, in these cases, due to the decrease in the drift layer thickness, there is a limit to soft recovery as well as a reduction in breakdown voltage. This is because the expansion of the space charge region in the drift layer during reverse recovery mainly depends on the donor distribution in the drift layer, so if the applied voltage is high in the range of the device breakdown voltage or less, the injection was reduced. In the end, however, drifting causes more carriers to be swept out into the space charge region, resulting in hard recovery.

As another example of improving the trade-off, there is a method of devising the donor distribution of the drift layer. For example, in the diode shown in FIG. 17 (conventional product C), the n drift layer 81 is divided into two regions 81a and 81b, the p anode layer 82 side is set to high specific resistance (low concentration), and the n cathode layer 83 side is set. By using a low specific resistance (high concentration), the depletion layer is kept at a certain voltage or higher (see Patent Document 1).
The diode shown in FIG. 18 (conventional product D) has a structure in which the specific resistance gradually decreases toward the n cathode layer 93, and soft recovery is similarly achieved. However, in the carrier sweeping out at the time of reverse recovery, when the p anode layer 92 side has a high specific resistance, depending on the operation mode of the application (high voltage, low current, etc.), the amount of carriers swept out by drift may increase. Hard recovery (see Patent Document 2).

In the diode shown in FIG. 15 (conventional product A) disclosed in Japanese Patent Application No. 2001-48631 proposed by the inventors, the n drift layer 61 has a lower specific resistance than that of the n drift layer 61. By providing the n buffer layer 61a having a concentration and thickness that depletes itself during reverse biasing, the structure of controlling the elongation of the depletion layer and significantly improving both soft recovery and high speed is provided. However, in this structure, due to the presence of the n buffer layer 61a, the voltage increase rate dV / dt increases when the space charge region just reaches the n buffer layer 61a during reverse recovery (in the vicinity of the peak of the reverse recovery voltage). A phenomenon in which dV / dt increases) was observed. Since this is a demerit from the viewpoint of noise reduction, it is necessary to suppress this increase in dV / dt.
Further, Japanese Patent Application No. 2002-214657 was filed as a semiconductor device capable of reducing reverse recovery loss, further improving soft recovery characteristics, suppressing reverse recovery voltage dV / dt, and suppressing reverse recovery voltage / current waveform oscillation. . The diode disclosed in Japanese Patent Application No. 2002-214657 is shown in FIG. 19 (conventional product E). 19A is a cross-sectional view of the main part, and FIG. 19B is a distribution diagram of the impurity concentration in FIG. 19A. The surface structure of this semiconductor device is the same as that of a normal pin diode, and the p anode layer is formed over the entire active region. In the background art and in the drawings of the embodiments to be described below, there are some which are described using a view showing only the active region in a cross section. A withstand voltage structure such as a guard ring, a field plate, or RESURF is provided. A p-type stopper region is provided at the outer peripheral edge of the anode side surface, and a stopper electrode is provided on the surface thereof. Since the depletion layer does not reach the outer peripheral edge by this stopper region, there is no particular problem even if the n drift layer 11 is exposed on the outer peripheral side surface of the chip. For this reason, it is not necessary to perform a special process after cutting at the chip side end.

In FIG. 19, a p anode layer 12 is formed on one of the n drift layers 11, an n cathode layer 13 is formed on the other, an anode electrode 14 is formed on the p anode layer 12, and a cathode electrode 15 is formed on the n cathode layer 13. To do. The impurity concentration of the n drift layer 11 has a peak near the center as shown in FIG. 4B, and gradually decreases from the peak position Xp to the p anode layer 12 side and the n cathode layer 13 side. .
JP 08-148699 A JP 08-316500 A B. J. Baliga “The pinch rectifier”, IEEE Electron. Dev. Lett. ED-5, p194, 1984. M. Mori. Et al. (M. Mori, et.al.), “A Nobel Soft and Fast Recovery Diode (SFD) With Simpy Layer Formed by Aluminum-Silicon Electrode (A Novel Soft and Fast Recovery Diode (SFD) with Thin P-layer. Formed by Al-Si Electrode) "Proceedings of ISPSD '91, pp113-117, 1991. M. Nemoto, et al., “An Advanced FWD Design Concept with Reverse Reverse Characteristic” Pps 119-122, 2000. Proceedings of ISPSD2000. M. Nemoto, et al., Proceedings of ISPSD '98, pp 305-308, 1998.

In the conventional product E (hereinafter referred to as a broad buffer structure), it is possible to provide not only high speed and low loss but also a soft recovery diode that suppresses oscillation. However, in order to obtain the concentration distribution of this broad buffer structure, it is necessary to create it on a high-concentration CZ (Czochralski) substrate or a low-concentration FZ (floating zone) substrate while continuously changing the phosphorus concentration by epitaxial growth. The FZ bulk wafer had to be prepared by irradiating light ions that form donor levels such as protons. In the case of the broad buffer created by these methods, there is a problem that the manufacturing cost is higher than that of a PIN diode using only an FZ bulk wafer. That is, the broad buffer structure formed by epitaxial growth is expensive for epitaxial growth in addition to the price of the substrate, and in the case of proton irradiation, there is an increase in cost due to the use of a cyclotron.
On the other hand, in recent years, in general-purpose IGBTs and FWDs of 600V to 1200V, a method of forming a thin vertical element by grinding an inexpensive FZ wafer to around 100 μm is becoming the mainstream, improving not only performance but also cost performance. Is also required. However, when this FZ wafer is formed by grinding to around 100 μm, the concentration distribution of the N ⁻ layer can only be a uniform distribution in the depth direction. For this reason, the concept that achieves both low loss and soft recovery characteristics as in the conventional product E cannot be applied when the FZ wafer is ground to about 100 μm. Accordingly, the object of the present invention is to solve the above-mentioned problems, suppress an increase in dV / dt during reverse recovery, suppress waveform vibration during reverse recovery, and achieve both high speed / low loss characteristics and soft recovery characteristics. At the same time, it is to provide an inexpensive semiconductor device using an FZ bulk wafer.

In order to solve the above-described problems and achieve the object, the present invention has a concentration lower than the concentration of phosphorus from one main surface and the other main surface of the FZ wafer containing phosphorus which is an N-type impurity. As described above, the concentration of the N ⁻ drift layer is compensated by diffusing at least one of aluminum, gallium, indium and zinc, which is a P-type impurity having a diffusion coefficient larger than that of boron, for example, at a temperature of 1200 ° C. or less. The net doping concentration is formed to be lower than the phosphorus concentration. Thereby, it is possible to easily form a broad buffer structure using the FZ wafer.

  According to the semiconductor device and the manufacturing method thereof of the present invention, it is possible to form a broad buffer structure by controlling the net doping concentration distribution deep inside the wafer in a simple manner with respect to an inexpensive FZ wafer. It becomes possible. As a result, an inexpensive diode with reduced reverse recovery time and loss and improved soft recovery characteristics or an IGBT with suppressed oscillation can be provided. This makes it possible to provide an inexpensive IGBT module and IPM (intelligent power module) that take into consideration environmental issues with low electrical loss and radiated electromagnetic noise.

1A and 1B show an embodiment showing the best mode of the present invention, where FIG. 1A is a cross-sectional view of an essential part, FIG. 1B is a distribution diagram of impurity concentration in a cross section taken along line XX in FIG. FIG. 3 is an electric field distribution diagram in a section taken along line XX. In FIG. 1, aluminum, gallium, or indium is uniformly introduced from the main surface on the anode side of the N ⁻ drift layer 1 to the entire surface of the N ^- bulk wafer of FZ. At this time, the maximum concentration of aluminum, gallium or indium is set lower than the phosphorus concentration of the N ^- bulk wafer of FZ. Further, zinc is uniformly introduced into the entire surface of the N ^- bulk wafer from the other main surface on the cathode side. At this time, the maximum concentration of zinc is set lower than the phosphorus concentration of the N ^- bulk wafer of FZ. The introduction of aluminum, gallium, indium or zinc is made to be uniform diffusion with a Gaussian distribution. Thereby, the acceptor strongly compensates the donor in the vicinity of each surface of one main surface and the other main surface, so that the net doping concentration distribution is low on both main surfaces, toward the center in the depth direction of the wafer, The load buffer structure gradually increases, and the central portion becomes the effective N buffer layer 1a. Since impurity elements having different diffusion coefficients are introduced into one main surface and the other main surface, a portion having a high net doping concentration can be set at an arbitrary depth position. In this way, a wafer having a concentration distribution similar to the broad buffer structure disclosed in Japanese Patent Application No. 2002-214657 can be formed using an inexpensive FZ wafer. The P anode layer 2, the guard ring 6, and the N ⁺ cathode layer 3 can be formed by general diffusion or ion implantation. Depending on the application, it may be sufficient to change the impurity concentration distribution from one of the main surfaces without changing the impurity concentration distribution from both the main surfaces as the element characteristics of the diode. In such a case, for example, the phosphorus concentration of the N ^- bulk wafer may be kept on the front surface side, and zinc may be introduced only on the back surface side to change the impurity concentration distribution from the back surface side. On the contrary, any one of aluminum, gallium and indium may be introduced only on the surface side to change the impurity concentration distribution only on the surface side. In any case, the production method of the present invention can be applied.

  Referring to FIG. 19B instead of FIG. 1B, in the n drift layer 1, the net doping concentration Nd (X) has the maximum concentration at the position Xp in the n drift layer 1, The impurity concentration is gradually reduced by diffusion of aluminum, indium, gallium or zinc from Xp toward the anode electrode 4 or the cathode electrode 5. The boundary between the p anode layer 2 and the anode electrode 4 is the starting point (0), the distance to the boundary (junction) between the p anode layer 2 and the n drift layer 1 is Xj, and the boundary between the n cathode layer 3 and the n drift layer 1 , The net doping concentration distribution Nd (X) from Xj to Wd is integrated, and the average net doping concentration Ndm divided by Wd−Xj is

Then, two intersections of Nd (X) and Ndm are given and can be placed as Xc and Xd, respectively. A region sandwiched between Xc and Xd is an effective n buffer layer (effective n buffer layer 1a). Further, when the impurity concentration at the intersection of the p anode layer 2 and the n drift layer 1 is N1, and the impurity concentration at the intersection of the n cathode layer 3 and the n drift layer 1 is N2, N1 ≦ N2.
Here, the average net doping concentration Ndm of the n drift layer 1 of the present invention is obtained by dividing the integrated concentration by the width of the n drift layer 1, and its value is about 8 × 10 ¹³ cm ⁻³ . There are two net doping concentrations, as shown in FIG. The integrated concentration between the two points (Xc, Xd) is the integrated concentration of the effective n buffer layer 1a (hereinafter referred to as effective buffer integrated concentration), and the value is about 5 × 10 ¹¹ cm ⁻² , which will be described later. It is almost the same as the integrated concentration of the n buffer layer of A. Therefore, a sufficient soft recovery effect can be obtained, and the reverse recovery voltage / current oscillation is suppressed.

The dV / dt suppression effect near the peak of the reverse recovery voltage depends on the ratio of the maximum net doping concentration Np and the average net doping concentration Ndm of the n drift layer 1 as shown in FIG. Further, the pinning effect of the depletion layer (an effect of stopping the extension of the depletion layer) is greater as the maximum net doping concentration Np of the n buffer layer 1 is higher than the n drift layer average net doping concentration Ndm.
The reason can be explained as follows. As the net doping concentration of the n buffer layer 1 is higher, the depletion layer (= space charge region) can be prevented from entering the n buffer layer 1a.
Therefore, when the space charge region reaches the n buffer layer 1a when the voltage is increasing, the increase in voltage δV is only in the n drift layer 1 having a low net doping concentration (high resistivity) on the p anode layer 2 side. Therefore, the electric field strength increases rapidly. For this reason, dV / dt increases. Therefore, dV / dt can be suppressed by suppressing the maximum net doping concentration Np of the n drift layer 1 (n buffer layer 1a).

Therefore, the product of the present invention suppresses vibration after exceeding the peak of the reverse recovery current, and dV / dt in the vicinity of the peak of the reverse recovery voltage becomes gentle.
FIG. 3 is a diagram showing the relationship between Np / Ndm and dV / dt, which is the ratio of the maximum net doping concentration Np and the average net doping concentration Ndm of the n drift layer 1 (n buffer layer 1a) in the product of the present invention. Here, dV / dt is normalized by the value of the conventional product B. FIG. 2 shows the relationship between the reverse voltage waveform and Np / Ndm. As Np / Ndm decreases, dV / dt decreases.
As shown in FIG. 3, when Np / Ndm is smaller than 5, dV / dt is smaller than twice that of the conventional product B, and when Np / Ndm is smaller than 2, dV / dt is almost the same as that of Conventional Example B. It has become. Therefore, Np / Ndm is desirably 2 or less. Of course, there is no waveform vibration, and the value of dV / dt is smaller than that of the conventional product A in which Np / Ndm is 20.

As described above, the conventional product B has a small dV / dt, but the reverse recovery voltage / current waveform vibrates.
FIG. 4 is a diagram showing the dependence of the device breakdown voltage (breakdown voltage) on the effective buffer integral concentration (net doping) in the product of the present invention. The element breakdown voltage is standardized by the breakdown voltage of the conventional product B. The horizontal axis represents the effective buffer integrated concentration (net doping).
The decrease in electric field strength between any two points from the p anode layer 2 side to the n cathode layer 3 side (electric field strength gradient) is the integral of the n drift layer 1 (including the n buffer layer 1a) between the two points. Determined by density difference.
Therefore, it is necessary to adjust the value to reduce the gradient of the electric field strength so as not to impair the breakdown voltage. As shown in FIG. 4, it can be seen that when the effective buffer integrated concentration exceeds 8 × 10 ¹¹ cm ⁻² , the decrease in breakdown voltage increases. Furthermore, if the effective buffer integrated concentration (net doping) is 6 × 10 ¹¹ cm ^−2, it can be seen that there is no reduction in breakdown voltage. Therefore, the effective buffer integrated concentration (net doping) is 8 × 10 ¹¹ cm ⁻² or less, preferably 6 × 10 ¹¹ cm ⁻² or less.

FIG. 5 is a diagram showing the relationship between the reverse recovery current decrease rate djr / dt and the ratio of Xp to the position index. In this figure, djr / dt when Xp is changed with respect to the position index (the denominator of the equation on the horizontal axis) is normalized for a ratio of 1 to the position index. In addition, the current of the reverse recovery current decrease rate djr / dt on the vertical axis is expressed by current density (A / cm ² ). The position index is

That is. The physical meaning of this position index has been explained by the authors in Japanese Patent Application No. 2001-48631.
In FIG. 5, when the position Xp of the maximum net doping concentration Np of the n drift layer 1 or the effective n buffer layer 1a is the same as the position index, djr / dt becomes the smallest and soft recovery is performed. In general, djr / dt can be made smaller than that of the conventional product B (indicated by ●), and can be effectively reduced between the indices 0.3 to 1.7. In particular, djr / dt is the smallest when the ratio is between 0.8 and 1.2. Therefore, the ratio is preferably between 0.3 and 1.7, and more preferably between 0.8 and 1.2.
FIG. 6 is a graph showing the relationship between the integrated net doping concentration of the entire n drift layer, the reverse recovery loss Err, and the reverse recovery current decrease rate djr / dt in the product of the present invention. The horizontal axis represents the integrated net doping concentration of the entire n drift layer. The integrated concentration (net doping) of the entire n drift layer 1 is changed by fixing the effective buffer integral concentration (net doping) to 5 × 10 ¹¹ cm ⁻² and changing the width (Wd−Xj) of the n drift layer. It was. From this figure, when the integrated concentration (net doping) of the entire n drift layer exceeds about 1.3 × 10 ¹² cm ⁻² , the device does not reach the n cathode layer even when the withstand voltage is so-called non-punch. It becomes a through type.

Further, from FIG. 6, when the integrated concentration (net doping) exceeds 1.3 × 10 ¹² cm ⁻² , the increase in Err increases, and when it exceeds 2 × 10 ¹² cm ⁻² , Err increases rapidly. If the integrated concentration (net doping) is increased by increasing the width of the n drift layer in this manner, the Err is increased.
From the above, it is necessary to carefully design the integrated concentration (net doping) of the entire n drift layer. In order to suppress a rapid increase in Err, the integrated concentration (net doping) is 2 × 10 ¹² cm ⁻² or less, preferably 1.3 × 10 ¹² cm ⁻² or less.
Further, in order to suppress the oscillation and sufficiently reduce the reverse recovery current decrease rate djr / dt, the integration concentration (net doping) must be set appropriately in the same manner. Similarly, from FIG. 6, when the integrated concentration (net doping) is less than 8 × 10 ¹¹ cm ⁻² , the device thickness becomes as thin as about 100 μm, and oscillation occurs. Therefore, the integrated concentration (net doping) needs to be 8 × 10 ¹¹ cm ⁻² or more.

As described above, the range of the integrated concentration (net doping) is 8 × 10 ¹¹ cm ⁻² or more and 2 × 10 ¹² cm ⁻² or less, preferably 8 × 10 ¹¹ cm ⁻² or more and 1.3 × 10 ¹² cm. ^{It should be} less than ^-2 . Further, the surface concentration of the n cathode layer 3 is preferably at least 1 × 10 ¹⁷ cm ⁻³ or more in order to make contact with the cathode electrode 5 with low resistance. Considering the electric field distribution and the integrated concentration when the critical electric field strength is reached, if this integrated concentration is 1.3 × 10 ¹² cm ⁻² over the entire n drift layer, the depletion layer reaches the end of the n drift layer.
FIG. 7 shows the ratio of the net doping concentration Nd (Xj) of the n drift layer 1 and the concentration index in the vicinity of the pn junction Xj between the p anode layer 2 and the n drift layer 1 and the breakdown voltage (breakdown voltage). FIG. The denominator of the horizontal axis is the concentration index,

It is expressed. Here, the element breakdown voltage on the vertical axis is normalized by the element breakdown voltage when the concentration ratio (ratio between the net doping concentration Nd (Xj) and the concentration index) is 1.
The device breakdown voltage is determined by the relationship between the critical electric field strength and the electric field strength distribution during reverse bias. If the impurity concentration at the junction decreases, the device breakdown voltage improves.
In the case of the product of the present invention, the device breakdown voltage can be improved by lowering the net doping concentration in the vicinity of Xj. The device breakdown voltage increases as the concentration ratio decreases, and conversely, when the concentration ratio is 1 or more, the breakdown voltage decreases rapidly. Therefore, it is desirable that the concentration ratio be 1 or less.

8A and 8B show a first embodiment of the present invention, in which FIG. 8A is a cross-sectional view of the main part of the whole chip after dicing, and FIG. FIG. In FIG. 8, on one main surface of an N ^- bulk wafer of FZ having a specific resistance of 28 Ωcm (1.64 × 10 ¹⁴ / cm ³ ), a diode anode structure (a shallow P ^- emitter layer 2b with a low impurity concentration and a deep impurity) A high concentration P ⁺ anode layer 2a) and an electric field relaxation edge structure (guard ring 6) are formed. The anode structure, for example a dose of 1 × ¹⁰ 14 / cm and ^{the P +} anode layer 2a which is spread forming a ^second boron at selective ion implantation to 1150 ° C. 200 minutes, again boron 1 × ¹⁰ 13 / cm uniformly irradiated with ² dose, 400 ° C. for low temperature at the heat treatment activated p ^- emitter layer 2b, these ^{P +} anode layer 2a and the P ^- Al-1% Si to contact the emitter layer 2b The anode electrode 4 is formed. On the other hand, the edge portion having the pressure-resistant structure is formed with a P-type guard ring 6 in which boron is selectively ion-implanted at 2 × 10 ¹⁵ / cm ^{2 in the} outer peripheral region where the anode electrode 4 does not contact. Aluminum, gallium, or indium is uniformly diffused from the anode side in a substantially Gaussian distribution with a surface concentration of 1 × 10 ¹⁴ / cm ³ and a depth of 1 / e of 20 μm, and the surface concentration is higher than the phosphorus concentration of the FZ wafer. The N ^- layer net doping concentration in the vicinity of the PN junction is 6.4 × 10 ¹³ / cm ³ . From the cathode side, zinc is uniformly diffused in a substantially Gaussian distribution with a surface concentration of 1 × 10 ¹⁴ / cm ³ and an l / e depth of 20 μm, and the surface concentration is higher than the phosphorus concentration of the FZ wafer. Low, the N ⁻ layer net doping concentration in the vicinity of the N ⁻ / N ⁺ layer concentration boundary is 6.4 × 10 ¹³ / cm ³ . On the cathode side, shallow N ⁺ cathode layer 3 is ground and wet-etched from the back surface to 120 μm thickness after the surface process of the FZ wafer is completed, and 1 × 10 ¹⁵ / cm ² of phosphorus is ion-implanted at 50 keV or less. The light is activated by irradiation with an energy density of 4 J / cm ² . The cathode electrode 5 is formed by vapor-depositing titanium 0.075 μm, nickel 0.7 μm, and gold 0.2 μm. The dicing surface at the outer peripheral edge of the chip is not subject to any special treatment because the depletion layer is terminated by the surface edge structure (in this case, the guard ring structure).

FIG. 9 is a distribution diagram showing the net doping concentration by acceptor compensation of the present invention. In FIG. 9, first, the concentration N _D (x) = N ₀ of the FZ bulk wafer exists. Here, the acceptor is diffused from the surface with a concentration of N _A1 (x), for example, in a Gaussian distribution. At this time, N ₀ > N _A1 (x). On the other hand, the acceptor is also diffused from the back surface with a concentration of N _A2 (x), for example, in a Gaussian distribution. At this time, N ₀ > N _A2 (x). Therefore, the net doping concentration Net (x) is expressed by the following equation: Net (x) = N ₀ − {N _A1 (x) + N _A2 (x)} (> 0). Thus, for example, Poisson's equation in the N ⁻ layer can be expressed as divE (x) = q / εsNet (x) ·· 2. Here, E is the electric field intensity distribution in the N ⁻ layer, q is the elementary charge, and εs is the dielectric constant of the semiconductor (here, silicon). Therefore, from equation (1), it should be lower than the concentration N ₀ of FZ bulk wafer density compensating acceptor in all positions. In order to achieve this concentration distribution, the integrated concentration of net doping needs to be 8 × 10 ¹¹ / cm ² or more and 1.3 × 10 ¹² / cm ² or less as in Japanese Patent Application No. 2002-214657. The ion implantation dose of the acceptor for use is an amount that does not exceed the above-mentioned integrated concentration, preferably 7 × 10 ¹¹ / cm ² or less.

Here, in practice, in the diode, the P anode layer is formed on the front surface by introducing boron, and the N cathode layer is formed on the back surface by introducing phosphorus. In NPT-IGBT and FS-IGBT, the P well on the front surface is formed by introducing boron, the P collector layer on the back surface is formed by introducing boron, and the N ^- field stop layer is ionized using phosphorus or selenium. It forms by a well-known method at the temperature of 400 to 1000 degreeC by injection | pouring. Therefore, strictly speaking, the net doping concentration Net (x) of the N ⁻ layer is in the case of a diode, and Net (x) = N ₀ + N _D (x) − {N _A0 (x) + N _A1 (x) + N _A2 ( x)} (> 0)... Here, N _D (x) is the phosphorus concentration for the N cathode layer on the back surface, and N _A0 (x) is the boron concentration for the P anode layer on the surface. In the case of NPT-IGBT, N _D (x) may be set to -N _A3 (x) and this may be used as the collector layer concentration on the back surface. In the case of _{FS-IGBT, N} D a _(x), and N D _{(x) -N} A3 (x) as its _N D (x) is the back surface of the field stop layer (phosphorus or selenium) _{concentration, N A3} (X) may be the collector layer concentration on the back surface. However, in practice, as shown in the concentration distribution in the depth direction of FIG. 10, the P anode layer and the N cathode layer have a distribution that is several orders of magnitude shorter than the aluminum or zinc diffusion layer. (A) shows the entire depth, (b) shows the front side and (c) shows the back side enlarged, but for example, boron in the P anode layer is already 1 μm deeper than the PN junction. × 10 ¹¹ / cm ³ , and the influence on the Net (x) of the shallow diffusion layers of the boron layer and the phosphorus layer is extremely small and can be ignored. This is also true for phosphorus in the N cathode layer on the back side. Therefore, in practice, the net doping concentration distribution of the N ⁻ layer is approximately sufficiently established by one equation. Regarding the concentration gradient, for the same reason, the influence on the concentration gradient of Net (x) of the P anode layer on the front surface and the N cathode layer on the back surface can be ignored.

Next, the impurity elements introduced into the FZ bulk wafer will be examined. The diffusion coefficient into silicon is higher in the order of boron <indium <gallium <aluminum <zinc, and aluminum and gallium are one digit higher than boron. Therefore, for example, at 1150 ° C. for 200 minutes or 1200 ° C. for 30 minutes, in an 28 Ωcm N-type FZ bulk wafer, boron diffuses by about 4 μm, and aluminum and gallium diffuse by about 40 μm. On the other hand, zinc has a higher diffusion coefficient, which is 3 × 10 ¹³ cm ² / s at 650 ° C. to 700 ° C. Therefore, for example, at 800 ° C., in an N-type FZ bulk wafer of 28 Ωcm, zinc diffuses about 30 to 40 μm. Therefore, in the present invention, in order to achieve diffusion of 50 μm or less, it is preferable to diffuse at 1200 ° C. or less for aluminum or gallium and 800 ° C. or less for zinc. Further, since the lower limit of diffusion is 5 μm or more, it is preferable to perform heat treatment at 1000 ° C. or more for aluminum or gallium and 400 ° C. or more for zinc. Although gallium is a solid ion implantation source, it is less reactive than aluminum and easy to handle. Since aluminum has a higher diffusion coefficient than gallium, the lead time of the diffusion process can be shortened compared to gallium. Indium has a smaller diffusion coefficient than gallium and aluminum, but is larger than boron and has a lower solid solubility than boron, and is more advantageous than boron in a low-concentration diffusion layer as in the present invention. Zinc has the deepest acceptor level from the valence band. Therefore, since the hole concentration can be made lower than that of boron or aluminum at room temperature (300 K), the element contributes little to the conduction modulation. Furthermore, zinc shows a level 0.26 eV higher than the valence band, and becomes an acceptor. This means that when the space charge region expands during reverse bias, it functions as a 100% acceptor, and during forward conduction, it does not supply holes as an acceptor. Zinc is used for the back surface because it operates only during reverse bias. Is preferred.

FIG. 11 is a process chart showing the production method of the present invention. In FIG. 11, aluminum or gallium is ion-implanted at 3 × 10 ¹¹ / cm ² and 60 keV on one surface of an FZ bulk wafer and diffused at 1150 ° C. for 80 minutes (FIG. 11A). At this time, since aluminum has outward diffusion, a nitride film is used to prevent outward diffusion. By this diffusion, aluminum or gallium is diffused by 20 μm from the surface. After the compensation acceptor is diffused in this manner, a normal element formation process is performed to form the P anode layer 2, the P guard ring 6, and the PSG film 7, and an Al-Si electrode contact hole is formed ( b). At this time, since the aluminum or gallium is also diffused when these shallow (4 to 8 μm) P layers are diffused, the aluminum or gallium finally reaches about 40 μm. Next, grinding is performed from the back surface of the wafer by back grinding until the remaining thickness of the entire wafer becomes 140 μm, and further, grinding is performed to 120 μm by wet etching with hydrofluoric acid (c). Thereafter, zinc is ion-implanted into the back surface at 3 × 10 ¹² / cm ² and 50 keV. Heat treatment is performed at 600 ° C. for 1 hour to diffuse zinc by about 30 μm (d). Again returning to the surface, a film of Al-1% Si is formed by sputtering with 5 μm, and patterned to form an anode electrode. Al—Si sintering is performed at 400 ° C. for 80 minutes, and a passivation polyimide film is formed on the peripheral pressure-resistant structure, and then titanium, nickel and gold are vapor-deposited on the back surface to form a cathode electrode (e).
Since zinc diffuses at 800 ° C. or lower, the acceptor activation rate is lower than high temperature (1000 ° C. or higher) and is 10% or lower. Therefore, in order to make the integrated concentration of zinc activated to be an acceptor less than 1.3 × 10 ¹² / cm ² , the dose amount at the time of ion implantation is desirably 1.0 × 10 ¹³ / cm ² or less.

FIGS. 12A and 12B show a case where the present invention is applied to an IGBT in different embodiments, wherein FIG. 12A is a reverse blocking IGBT, and FIG. 12B is a cross-sectional view of an NPT-IGBT and FS-IGBT. The reverse blocking IGBT is an element used for a matrix converter, and two reverse blocking IGBTs are connected in antiparallel to be used as a bidirectional switch. At this time, a reverse recovery operation mode of the PN junction PiN diode on the back surface side occurs. Therefore, by adopting the configuration of the present invention, this reverse recovery becomes soft recovery, and oscillation at the time of switching can be suppressed.
Further, when applied to NPT-IGBT and FS-IGBT, not only low loss but also turn-off with suppressed oscillation can be realized. At the time of turn-off, the space charge region expands from the PN junction on the front surface toward the back surface side, but by using the broad buffer structure, in the middle of the N ^- layer, as in the reverse recovery of the diode, Electric field intensity can be reduced and the expansion of the space charge region can be suppressed. As a result, since carriers remain on the back side and are not withered, a sharp increase in turn-off surge voltage can be suppressed.

  These reverse blocking IGBTs, NPT-IGBTs, and FS-IGBTs grind an inexpensive FZ bulk wafer to around 100 μm, and perform ion implantation and heat treatment processes on the back side. Therefore, by applying the manufacturing method of the present invention, it is possible to easily make an IGBT having a broad buffer structure. In a power converter such as a PWM inverter using an IGBT module, overvoltage breakdown or generation of EMI noise occurs. Can be suppressed.

13A and 13B show a semiconductor device (MOSFET) according to a third embodiment of the present invention, in which FIG. 13A is a cross-sectional view of the main part of the planar gate structure, FIG. 13B is a cross-sectional view of the main part of the trench gate structure, FIG. 4C is an impurity concentration distribution diagram. This is a case where the first embodiment (other embodiments may be used) is applied to the n drift layer of the MOSFET. When the diode built in the MOSFET operates and performs a reverse recovery operation, the reverse recovery can be performed more smoothly and faster than the conventional MOSFET. The same effect can be obtained whether the gate structure is a planar structure (FIG. 1A) or a trench structure (FIG. 1B).
In the figure, 31 is an n drift layer, 32a is a p well region, 32b is an n source region, 32c is a gate insulating film, 32d is a gate electrode, 32e is an interlayer insulating film, 32f is a trench, 33 is an n drain layer, Reference numeral 34 denotes a source electrode, and 35 denotes a drain electrode.

14A and 14B show the semiconductor device described with reference to FIG. 12A. FIG. 14A is a cross-sectional view of the main part, and FIG. 14B is an impurity concentration distribution diagram. This is the case of a reverse blocking IGBT in which an NPT (non-punch through) -IGBT has a reverse blocking capability. Since this reverse blocking IGBT has a diode operation, the diode operation can be improved by providing the buffer layer of the first embodiment (may be another embodiment). This n buffer layer may or may not reach the side surface p collector layer 43a.
In the figure, 41 is an n drift layer, 42a is a p well region, 42b is an n emitter region, 42c is a gate insulating film, 42d is a gate electrode, 42e is an interlayer insulating film, 43 is a p collector layer, 43a is a side surface p. A collector layer, 44 is an emitter electrode, and 45 is a collector electrode.

  As described above, the diode of the present invention is an element that is inexpensive and has reduced reverse recovery time and loss and improved soft recovery characteristics, and therefore considers environmental problems with low electrical loss and radiated electromagnetic noise. The present invention can be applied to an IGBT module and IPM (intelligent power module).

It is an Example which shows the best form of this invention, (a) is principal part sectional drawing, (b) is a distribution map of the impurity concentration in the cross section of the XX line of (a), (c) is XX. It is an electric field distribution map in the section of a line. It is a figure which shows the relationship between Np / Ndm and dV / dt of a reverse recovery voltage. FIG. 6 is a diagram showing the relationship between Np / Ndm, which is the ratio of the maximum net doping concentration Np and average net doping concentration Ndm of the n drift layer 1 (n buffer layer 1a), and dV / dt of the reverse recovery voltage in the product of the present invention. . In the present invention product, it is a figure which shows the dependence of element breakdown voltage (breakdown voltage) by effective buffer integral density | concentration (net doping). It is a figure which shows the reverse recovery current decreasing rate djr / dt, and the relationship between ratio of Xp and a position parameter | index. In the product of the present invention, it is a diagram showing the relationship between the integrated concentration (net doping) of the entire n drift layer, the reverse recovery loss Err, and the reverse recovery current decrease rate djr / dt. In the product of the present invention, it is a diagram showing the relationship between the ratio of the net doping concentration Nd (Xj) of the n drift layer 1 and the concentration index in the vicinity of the pn junction Xj between the p anode layer 2 and the n drift layer 1 and the device breakdown voltage. FIG. 2A is a first embodiment of the present invention, in which FIG. 1A is a cross-sectional view of a main part of a whole chip after dicing, and FIG. 2B is a distribution diagram of impurity concentration in a cross section along line A-A ′ of FIG. It is the distribution map which showed the net doping density | concentration by acceptor compensation of this invention. It is the figure which showed concentration distribution with respect to the depth direction of the Example of this invention. It is process drawing which shows the manufacturing method of the Example of this invention. This is a case where the present invention is applied to an IGBT in different embodiments, where (a) is a reverse blocking IGBT, and (b) is a cross-sectional view of an NPT-IGBT or FS-IGBT. The semiconductor device according to the third embodiment of the present invention is shown in (a) and (b), which are cross-sectional views of essential parts, and (c), which is an impurity concentration distribution diagram. It is a reverse blocking type NPT-IGBT, where FIG. It is principal part sectional drawing of the conventional product A, and the figure of an impurity profile. It is principal part sectional drawing of the conventional product B, and the figure of an impurity profile. It is principal part sectional drawing of the conventional product C, and the figure of an impurity profile. It is principal part sectional drawing of the conventional product D, and the figure of an impurity profile. It is a semiconductor device formed by the conventional manufacturing method, (a) is principal part sectional drawing, (b) is a distribution map of the impurity concentration of (a).

Explanation of symbols

1 N ⁻ drift layer 2 P anode layer 3 N ⁺ cathode layer 6 guard ring

Claims (10)

  One main surface and the other main surface of the semiconductor substrate are diffused into the first conductivity type semiconductor substrate having a uniform impurity concentration in the thickness direction of the substrate by diffusing the second conductivity type impurity having a concentration lower than the impurity concentration. A method of manufacturing a semiconductor device, wherein the semiconductor device is introduced from at least one of the surfaces.   2. The semiconductor device according to claim 1, wherein the first conductivity type semiconductor substrate is N-type silicon, and the second conductivity type impurity is a P-type impurity element having a diffusion coefficient larger than that of boron. Method.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the P-type impurity element uses at least one of aluminum, gallium, indium, and zinc.   3. The method of manufacturing a semiconductor device according to claim 2, wherein aluminum, indium or gallium is diffused from one main surface into the first conductivity type semiconductor substrate, and then zinc is diffused from the other main surface. . The method for manufacturing a semiconductor device according to claim 3, wherein the aluminum, gallium, or indium is ion-implanted with a dose of 1.0 × 10 ¹² cm ⁻² or less.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the ion-implanted aluminum or gallium is heat-treated at a temperature of 1000 ° C. or higher and 1200 ° C. or lower. The method for manufacturing a semiconductor device according to claim 3, wherein the zinc is ion-implanted at a dose of 1.0 × 10 ¹³ cm ⁻² or less.   The method of manufacturing a semiconductor device according to claim 7, wherein the ion-implanted zinc is heat-treated at a temperature of 400 ° C. or higher and 800 ° C. or lower.   A first-conductivity-type first semiconductor layer, and a second-conductivity-type impurity introduced into both main surfaces of the first-semiconductor layer to remain in the first-conductivity-type but have a low net doping amount, A second conductivity type second semiconductor layer having a higher concentration than the first semiconductor layer is provided on the main surface of the first semiconductor layer, and a first conductivity type third semiconductor layer having a concentration higher than that of the first semiconductor layer is provided on the other main surface. A semiconductor device characterized by the above.   A first-conductivity-type first semiconductor layer, and a second-conductivity-type impurity introduced into both main surfaces of the first-semiconductor layer to remain in the first-conductivity-type but have a low net doping amount, Having a second conductivity type second semiconductor layer having a higher concentration than the first semiconductor layer, a first conductivity type emitter layer selectively formed on the second semiconductor layer, A semiconductor device comprising a collector layer of a second conductivity type having a higher concentration than the first semiconductor layer on a main surface.

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