JP2007158320A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce reverse leakage current of a semiconductor device produced by grinding a semiconductor substrate to have a smaller thickness and performing ion implantation on the grinding surface. <P>SOLUTION: A diode 100 includes a P-anode layer 2 and an anode electrode 5, which are formed on the front side of an N<SP>-</SP>drift layer 1 and an N<SP>+</SP>cathode layer 3 and a cathode electrode 6 which are formed on the back side of the N<SP>-</SP>drift layer 1, wherein an N cathode buffer layer 4, having a higher density than the N<SP>-</SP>drift layer 1 and a lower density than the N<SP>+</SP>cathode layer 3, is formed between the N<SP>-</SP>drift layer 1 and the N<SP>+</SP>cathode layer 3, so that the N cathode buffer layer 4 has a larger thickness than that of the N<SP>+</SP>cathode layer 3. Thus, when a breakdown voltage is applied as a reverse-bias voltage, a depletion layer is stopped in the N cathode buffer layer 4 and is prevented from reaching the N<SP>+</SP>cathode layer 3, thereby suppressing leakage current. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device thinned by a back grinding process of a semiconductor substrate and a manufacturing method thereof.

  The following methods are known as methods for manufacturing power semiconductor devices such as diodes and insulated gate bipolar transistors (hereinafter referred to as IGBTs). First, a semiconductor element is manufactured using a wafer such as silicon while being thick. Thereafter, the wafer is thinned to the final thickness by grinding and etching, and then ion implantation and activation heat treatment are performed (see, for example, Patent Document 1). In recent years, such manufacturing methods are becoming mainstream.

  However, in this manufacturing method, in the activation heat treatment after grinding, since an electrode is already formed on the surface of the wafer opposite to the ground surface, the temperature is lower than the melting point of the electrode material, for example, the electrode material If aluminum is aluminum, heat treatment must be performed at a temperature of 450 ° C. or lower. For this reason, the impurities are not easily activated sufficiently.

  Therefore, in the above manufacturing method, the present applicant irradiates the ion-implanted impurity by irradiating the ion-implanted surface with high-energy laser light such as YAG second harmonic (YAG2ω) instead of heat treatment. A method of activation is proposed (see, for example, Patent Document 2 and Patent Document 3). According to this method, energy can be applied only to a region from the laser irradiation surface to an appropriate depth, so that impurities can be activated without adversely affecting the already formed electrodes.

  For example, a 1200V withstand voltage class diode is manufactured as follows. First, an aluminum electrode serving as a P-type anode layer and an anode electrode is formed on the front surface of an N-type FZ (floating zone) silicon wafer having a thickness of about 500 μm and a specific resistance of about 60 Ωcm. Next, grinding is performed from the back surface of the wafer to make the thickness of the wafer 140 μm. Next, wet grinding with hydrofluoric acid is performed to chemically polish the ground surface. Next, phosphorus is ion-implanted into the polished surface.

Then, the ion-implanted surface is irradiated with YAG2ω laser light with an energy density of 4 J / cm ² and a delay time of 300 nsec by a double pulse method to electrically activate phosphorus, thereby causing an N ⁺ cathode layer. Form. Here, the double pulse method is a method of continuously irradiating a plurality of pulse lasers by shifting the irradiation timing by a predetermined delay time from a plurality of laser irradiation apparatuses for each laser light irradiation area. The double pulse method is described in detail in Patent Document 2.

  In addition, the impurity concentration of the drift layer gradually decreases from the center to the anode and cathode layers, and the impurity concentration from the center of the drift layer to the emitter and collector layers. An IGBT having a profile that gradually decreases is known (see, for example, Patent Document 3 and Patent Document 4). A diode or IGBT having such an impurity concentration profile has both high speed and low loss characteristics and soft recovery characteristics.

  Further, a P-type anode layer is formed at one end of the low-concentration N-type semiconductor substrate, and a relatively high-concentration N-type cathode layer is formed at the other end, and the gap between the anode layer and the cathode layer is formed. A semiconductor element is known in which an i layer is formed and an N-type impurity layer having a lower concentration than the cathode layer is provided between the cathode layer and the i layer (see, for example, Patent Document 5). And an N-type internal zone, an N-type cathode zone having a higher doping concentration in the internal zone following the internal zone, and a P-type anode zone having a higher doping concentration in the internal zone following the internal zone. A power diode having an N-type floating region in the area having a higher doping concentration than in the inner area is known (see, for example, Patent Document 6).

Japanese translation of PCT publication No. 2002-52085 JP 2005-223301 A JP-A-2005-64429 JP 2003-318812 A JP 2000-223720 A JP 11-26779 A

However, in a diode or IGBT manufactured by a method in which one surface of a semiconductor substrate is ground and a cathode layer of the diode or an IGBT collector layer is formed on the ground surface, the electrical characteristics in the wafer state before being cut into individual chips are obtained. There is a problem that the probability of being a defective product in the measurement of characteristics is high, that is, the product yield is low. For example, the leakage current of the device in reverse bias voltage 1200V diodes in the wafer state (hereinafter, referred to as reverse leakage current) was measured, with respect to criterion that 1 .mu.A / cm ² or less, is 10 .mu.A / cm ² or more elements The product yield was 60% or less.

  Conventionally, the problem that such reverse leakage current occurs has not been pointed out. Therefore, as a matter of course, in Patent Documents 1 to 6, it is not assumed that a reverse leakage current is generated. For this reason, Patent Documents 1 to 6 do not include a description regarding the reverse leakage current and a description regarding countermeasures thereof.

  In order to eliminate the above-mentioned problems caused by the prior art, the present invention is manufactured by grinding and thinning a semiconductor substrate, and ion implantation and thermal activation of the implanted element on the ground surface. An object is to provide a semiconductor device with low current. Also provided is a method of manufacturing a semiconductor device in which a semiconductor device with low reverse leakage current is manufactured by grinding a semiconductor substrate to make it thin, and performing ion implantation and thermal implantation element activation on the ground surface. With the goal.

  In order to solve the above-described problems and achieve the object, the present inventor obtained the following knowledge as a result of intensive studies. If the ground surface (ion-implanted surface) of the semiconductor substrate is scratched or if particles due to grinding remain, ions such as phosphorus, which is an N-type impurity, are not normally ion-implanted into the ground surface. The layer may not be formed uniformly.

That is, if there are particles, phosphorus is shielded by the particles, and phosphorus is not sufficiently injected into the substrate, so that a high concentration cathode layer is not formed. In addition, if a scratch larger than the ion range is formed on the implanted surface after ion implantation, an exposed portion of the substrate is formed without forming an N ⁺ high-concentration layer at the scratched portion. When a high reverse bias voltage is applied to an element having such a defect, the depletion layer spreads to the N ⁻ drift layer and reaches the electrode at the defective portion, thereby increasing the reverse leakage current. The present invention has been made based on such knowledge.

  According to a first aspect of the present invention, there is provided a semiconductor device having a first conductivity type first semiconductor layer, a concentration higher than that of the first semiconductor layer, and the first semiconductor on one main surface side of the first semiconductor layer. A second conductivity type second semiconductor layer provided in contact with the layer; and a first conductivity type provided at a higher concentration than the first semiconductor layer and on the other main surface side of the first semiconductor layer. A third semiconductor layer having a higher concentration than the first semiconductor layer and a lower concentration than the third semiconductor layer, and the first semiconductor layer between the first semiconductor layer and the third semiconductor layer; And a fourth semiconductor layer of a first conductivity type provided in contact with both of the third semiconductor layer, a first electrode electrically connected to the second semiconductor layer, and electrically connected to the third semiconductor layer A second electrode to be connected, the first semiconductor layer of the fourth semiconductor layer going from one main surface of the first semiconductor layer to the other main surface Thickness at the direction, characterized in that larger than the thickness in the same direction of the third semiconductor layer.

  According to a second aspect of the present invention, there is provided a semiconductor device including a first conductive type first semiconductor layer made of an FZ semiconductor substrate, a higher concentration than the first semiconductor layer, and one main surface side of the first semiconductor layer. The second conductivity type second semiconductor layer provided in contact with the first semiconductor layer and the first conductivity formed by diffusion on the surface of the other main surface of the first semiconductor layer which has been reduced in thickness by grinding. A third semiconductor layer of a type and a fourth semiconductor layer of a first conductivity type, wherein the third semiconductor layer is higher in concentration than the first semiconductor layer, and the fourth semiconductor layer is It is located between the first semiconductor layer and the third semiconductor layer, has a higher concentration than the first semiconductor layer and a lower concentration than the third semiconductor layer, and is electrically connected to the second semiconductor layer A first electrode; and a second electrode electrically connected to the third semiconductor layer, the fourth semiconductor layer , The thickness in the direction from the one main surface of said first semiconductor layer on the other main surface, characterized in that larger than the thickness in the same direction of the third semiconductor layer.

  According to a third aspect of the present invention, there is provided a semiconductor device comprising: a first conductive type fourth semiconductor layer comprising an FZ semiconductor substrate or a CZ semiconductor substrate; and one of the fourth semiconductor layers having a lower concentration than the fourth semiconductor layer. A first conductivity type first semiconductor layer formed by epitaxial growth on the main surface side of the first semiconductor layer, and a higher concentration than the first semiconductor layer and the first semiconductor layer on one main surface side of the first semiconductor layer A second semiconductor layer of the second conductivity type provided in contact with the first semiconductor layer, and a third semiconductor layer of the first conductivity type formed by diffusion on the surface of the other main surface of the fourth semiconductor layer which has been reduced by grinding. The third semiconductor layer has a higher concentration than the fourth semiconductor layer, the fourth semiconductor layer is located between the first semiconductor layer and the third semiconductor layer, and A first electrode electrically connected to the second semiconductor layer, and an electric current connected to the third semiconductor layer. A thickness of the fourth semiconductor layer in a direction from one main surface of the first semiconductor layer to the other main surface in the same direction of the third semiconductor layer. It is characterized by being thicker than the thickness.

A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the concentration of the fourth semiconductor layer is 1 × 10 ¹⁴ atoms / cc or more and 1 × 10 ^15. It is characterized by being atoms / cc or less.

  A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the first semiconductor layer of the fourth semiconductor layer is changed from one main surface to the other main surface. The thickness in the direction of going is 0.1 μm or more.

  According to the first to fifth aspects of the present invention, when a withstand voltage that is the maximum voltage as the reverse bias voltage is applied, the depletion layer extends into the first semiconductor layer and reaches the fourth semiconductor layer. Since it stops in the middle of the layer, it does not reach the third semiconductor layer. Therefore, the leakage current can be suppressed.

  According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the third aspect, wherein the first conductive type first semiconductor layer is formed on the first conductive type fourth semiconductor layer. First conductivity having a stacked structure and having a concentration of an element indicating the first conductivity type in the fourth semiconductor layer having a solid solubility less than a solid solution limit of a semiconductor material constituting the fourth semiconductor layer. Forming a second conductive type second semiconductor layer on a surface layer of the first semiconductor layer, forming a first electrode in contact with the second semiconductor layer, and using the type semiconductor substrate, and the fourth semiconductor Grinding the surface layer of the layer to expose the fourth semiconductor layer to the desired thickness of the semiconductor substrate, and applying a first conductive material to the surface layer of the surface exposed by grinding of the fourth semiconductor layer Forming a third semiconductor layer of the mold, and a second in contact with the third semiconductor layer Characterized in that it comprises a step of forming a pole, the.

  According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the second aspect, wherein the first semiconductor layer of the first conductivity type and the first conductivity in the first semiconductor layer are formed. Using the first conductivity type semiconductor substrate in which the concentration of the element indicating the type is less than the solid solubility limit of the semiconductor material constituting the first semiconductor layer, the surface of the front surface of the first semiconductor layer Forming a second semiconductor layer of a second conductivity type on the layer, and grinding the surface layer on the back surface of the first semiconductor layer to expose the first semiconductor layer to a desired thickness A step of forming a first semiconductor layer of a first conductivity type on a surface layer of a surface exposed by grinding of the first semiconductor layer, and a step of forming a first electrode in contact with the second semiconductor layer. The surface layer of the surface exposed by grinding of the first semiconductor layer has a first conductivity type. 3 comprising the steps of the semiconductor layer is formed shallower than the fourth semiconductor layer, characterized in that it comprises a step of forming a second electrode in contact with said third semiconductor layer.

  The method of manufacturing a semiconductor device according to claim 8 is the method according to claim 7, wherein after the second semiconductor layer is formed and before the semiconductor substrate is ground, the semiconductor substrate is irradiated with protons. And a step of introducing a proton into the first semiconductor layer.

  A method of manufacturing a semiconductor device according to a ninth aspect of the present invention is the method according to any one of the sixth to eighth aspects, wherein in the step of forming the third semiconductor layer, the first conductive is formed on the surface exposed by grinding. A type impurity is ion-implanted, and the ion-implanted surface is irradiated with laser light to electrically activate the implanted impurity.

  According to a tenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to any one of the sixth to ninth aspects, wherein in the step of grinding the semiconductor substrate, wet etching is performed after the grinding and exposure is performed by grinding. The stress is removed by removing the processed surface with a thickness of 3 μm to 20 μm.

  According to invention of Claims 6-10, a 4th semiconductor layer is formed between a 1st semiconductor layer and a 3rd semiconductor layer. Therefore, it is possible to obtain a semiconductor device with little leakage current when a withstand voltage that is the maximum voltage as the reverse bias voltage is applied.

  According to the semiconductor device of the present invention, the semiconductor substrate is ground and thinned, and the reverse leakage current of the semiconductor device manufactured is reduced by performing ion implantation and thermal activation of the implanted element on the ground surface. There is an effect that can be. Further, according to the method for manufacturing a semiconductor device according to the present invention, a semiconductor device having a small reverse leakage current is thinned by grinding the semiconductor substrate, and ion implantation and thermal implantation element activation are performed on the ground surface. There exists an effect that it can produce by this.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in the layers and regions with N or P, respectively. Further, + and − attached to N mean that the impurity concentration is relatively high or low, respectively. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device of the first embodiment includes, for example, an N ⁻ drift layer 1 that is a first semiconductor layer, a P anode layer 2 that is a second semiconductor layer, and an N ⁺ cathode that is a third semiconductor layer. The diode 100 includes a layer 3, an N cathode buffer layer 4 that is a fourth semiconductor layer, an anode electrode 5 that is a first electrode, and a cathode electrode 6 that is a second electrode.

P anode layer 2 is provided in contact with N ⁻ drift layer 1 on one main surface side of N ⁻ drift layer 1. The N ⁺ cathode layer 3 is provided on the other main surface side of the N ⁻ drift layer 1. N cathode buffer layer 4, N ^- is provided between the drift layer 1 and the N ⁺ cathode layer 3, N ^- is in contact with both of the drift layer 1 and the N ⁺ cathode layer 3.

That is, the N ⁺ cathode layer 3, the N cathode buffer layer 4, the N ⁻ drift layer 1 and the P anode layer 2 are laminated in this order. Both the P anode layer 2 and the N ⁺ cathode layer 3 have a higher impurity concentration than the N ⁻ drift layer 1. The impurity concentration of the N cathode buffer layer 4 is higher than that of the N ⁻ drift layer 1 and lower than that of the N ⁺ cathode layer 3.

Also, N ^- concentration of the element showing the drift layer 1 and the N-type N cathode buffer layer 4, N ^- semiconductor material of the drift layer 1 and the N cathode buffer layer 4, for example, the solid solubility of less than the solid solubility limit of the silicon It is. For example, the concentration of the cathode buffer layer 4 is suitably 1 × 10 ¹⁴ atoms / cc or more and 1 × 10 ¹⁵ atoms / cc or less.

The thickness of the N cathode buffer layer 4 in the direction from one main surface of the N ⁻ drift layer 1 to the other main surface is larger than the thickness of the N ⁺ cathode layer 3 in the same direction. For example, the thickness of the N cathode buffer layer 4 is suitably 0.1 μm or more. Desirably, the thickness of the N cathode buffer layer 4 is 10 μm or more.

The anode electrode 5 is provided in contact with the surface of the P anode layer 2 and is electrically connected to the P anode layer 2. Anode electrode 5 and N ⁻ drift layer 1 are insulated by insulating film 7. The cathode electrode 6 is provided in contact with the surface of the N ⁺ cathode layer 3 is electrically connected to the N ⁺ cathode layer 3.

  Next, a method for manufacturing the diode according to the first embodiment will be described. FIG. 2 is a cross-sectional view of relevant parts showing a manufacturing process of the diode 100 according to the first embodiment. Here, as an example, a case will be described in which the chip size is set to 10 mm × 10 mm so that the rated voltage is 1200 A and the rated current is 150 A. The chip size can be variously changed according to the setting of the withstand voltage and the rated current.

First, as indicated by reference numeral 200 in FIG. 2, as a starting wafer, the concentration of phosphorus contained is 5 × 10 ¹⁴ atoms / cc and the specific resistance is 9.1 Ωcm, for example, N-type FZ or CZ having a diameter of 5 inches A wafer 201 is prepared. This N-type FZ or CZ wafer 201 becomes the N cathode buffer layer 4 of the diode 100. Hereinafter, the description is limited to the FZ wafer, but a CZ wafer may be used.

Next, as indicated by reference numeral 210, an N-type epitaxial layer 202 having a phosphorus concentration of 8.0 × 10 ¹³ atoms / cc and a specific resistance of 57 Ωcm is grown on the front side of the N-type FZ wafer 201. Let The N-type epitaxial layer 202 is the N ^{− of} the diode 100.
It becomes the drift layer 1. This epitaxial wafer is used as a semiconductor substrate. Reference numeral 220 indicates a profile of the impurity concentration of the semiconductor substrate.

Next, as indicated by reference numeral 230, a standard diode process step is performed, and an impurity concentration of 5 × 10 ¹⁶ atoms / cc and a depth are formed on the surface of the N ⁻ drift layer 1 (N-type epitaxial layer 202). A P anode layer 2 having a thickness of 3 μm and a guard ring edge structure (not shown) are formed. Further, an insulating film 7 is provided on the surface of the P anode layer 2, a contact hole is opened in the insulating film 7, and an anode electrode 5 in ohmic contact with the P anode layer 2 is formed of, for example, AlSi 1%.

  Thereafter, the semiconductor substrate is irradiated with an electron beam at an acceleration voltage of 4.8 MeV and a dose of 180 kGy, and heat treatment is performed at 357 ° C. for 1 hour. Next, the exposed surface of the N-type FZ wafer 201, that is, the surface on which the N-type epitaxial layer 202 is not laminated is ground to reduce the total thickness to 160 μm. Thereafter, the ground surface is wet-etched with hydrofluoric acid to a final thickness of 140 μm. By this wet etching, stress due to grinding is removed.

The thickness of the N ⁻ drift layer 1 and the N cathode buffer layer 4 at this stage is 120 μm and 20 μm, respectively. In this grinding and polishing process, it is necessary to leave the N cathode buffer layer 4 in a desired thickness after polishing. Here, the ground surface is removed by a thickness of 20 μm, but the thickness to be removed is suitably about 3 to 20 μm.

Next, phosphorus is ion-implanted into the surface layer of the N cathode buffer layer 4 exposed after polishing at an acceleration voltage of 45 keV and a dose of 1 × 10 ¹⁵ atoms / cm ² . Thereafter, YAG second harmonic laser light is irradiated to the ion implantation surface by a double pulse method. At that time, for each laser light irradiation area, the total energy density of the laser light is, for example, 4 J / cm ² , and the double pulse delay time is, for example, 300 nsec.

By this laser irradiation, phosphorus injected into the surface layer of the N cathode buffer layer 4 is activated, and the N ⁺ cathode layer 3 is formed. Finally, by forming a metal on the surface of the N ⁺ cathode layer 3 Ti, in order of Ni and Au, the cathode electrode 6 for ohmic contact is formed on the N ⁺ cathode layer 3, the diode 100 is completed. Reference numeral 240 indicates a profile of the impurity concentration of the completed diode 100.

Next, the dimension and doping concentration of each part of the diode according to the first embodiment will be described. FIG. 3 is an explanatory diagram showing an example of dimensions and doping concentration of a diode manufactured by the manufacturing process described above. FIG. 3 shows a cross-sectional view 300 of the main part of the diode, a distribution diagram 310 of the net doping concentration, and a distribution diagram 320 of the net doping integrated concentration. The net doping integrated concentration is obtained by integrating the net doping concentrations of the N ⁻ drift layer 1 and the N cathode buffer layer 4 from the PN junction of the P anode layer 2 and the N ⁻ drift layer 1 toward the N ⁺ cathode layer 3. It is. The horizontal axes of the distribution diagrams 310 and 320 correspond to the cross-sectional view 300 of the main part of the diode.

As shown in FIG. 3, on the basis of the PN junction between the P anode layer 2 and the N ⁻ drift layer 1, the distance to the interface between the N ⁻ drift layer 1 and the N cathode buffer layer 4 is X _1, and N ⁺ If the distance to the interface between the cathode layer 3 and the cathode electrode 6 is X _k , for example, X ₁ and X _k are 120 μm and 140 μm, respectively. Further, when the distance between the N ⁻ drift layer 1 and the N ⁺ cathode layer 3 is X ₄ , for example, X ₄ is 19.5 μm.

When a reverse bias voltage is applied between the anode and the cathode and the critical integrated concentration when the reverse bias voltage becomes the breakdown voltage value of the device is n _c , n _c is expressed by the following equation from Poisson's equation. Where ε _s is the dielectric constant of the semiconductor, q is the elementary charge, and E _c is the breakdown electric field strength of the semiconductor.
n _c = ε _s · E _c / q

As shown in the distribution diagram 320 of the net doping integrated concentration, the thickness and concentration (distribution) of the N cathode buffer layer 4 are adjusted so that the net doping integrated concentration becomes n _c in the N cathode buffer layer 4. The value of E _c is the silicon is about 3 × 10 ⁵ V / cm, a SiC at about 3 × 10 ⁶ V / cm, the diamond is about ^{5 × 10 6 V / cm,} GaN in about 3 × 10 ⁶ V / cm.

When the diode 100 is formed using a silicon semiconductor, the value of n _c is about 1.3 × 10 ¹² atoms / cm ² . Accordingly, in the middle of the N cathode buffer layer 4, the thickness and concentration (distribution) of the N cathode buffer layer 4 are adjusted so that the net doping integrated concentration becomes about 1.3 × 10 ¹² atoms / cm ² .

Here, in the manufacturing process in which the semiconductor substrate is thinly ground to a thickness of about 100 μm and the N ⁺ cathode layer 3 and the cathode electrode 6 are formed on the ground surface, impurities, defects, etc. do not affect the characteristics of the device. It is important to do so. For this purpose, when a breakdown voltage that is the maximum voltage as the reverse bias voltage is applied to the device, a region where depletion is not sufficient, that is, a neutral region remains on the N ⁻ drift layer 1 side of the N ⁺ cathode layer 3. Thus, the depletion layer may be prevented from reaching the N ⁺ cathode layer 3.

The thickness of the N ⁺ cathode layer 3 formed by the manufacturing process described above is a 1μm or less from the surface of the N ⁺ cathode layer 3 becomes thinner enough less than 1/100 of the thickness of the entire substrate. In the process of forming such a thin layer by impurity ion implantation and its activation treatment, for example, particles adhered to the ion implantation surface during ion implantation prevent the impurity implantation, or ions are formed during electrode formation or wafer transfer. When the injection surface is scratched, a portion where the N ⁺ cathode layer 3 is not completely formed tends to occur.

When the N ⁺ cathode layer 3 have such imperfections, the concentration of the N ⁺ cathode layer 3 is lowered. Therefore, in the case of an element without the N cathode buffer layer 4, when a reverse bias voltage having a high withstand voltage is applied to the element, the depletion layer cannot be stopped by the N ⁺ cathode layer 3, and the depletion layer becomes the cathode electrode. 6 is reached. Therefore, the reverse leakage current increases and the device manufacturing yield decreases.

On the other hand, in the case of the first embodiment, there is an N cathode buffer layer 4, and the integrated value of the impurity concentration from the N ⁻ drift layer 1 to the N cathode buffer layer 4 is in the middle of the N cathode buffer layer 4 as described above. it reaches a critical integral density n _c. Therefore, when the breakdown voltage, to a position where the integrated value of the impurity concentration reaches a critical integral density n _c is depleted, the distribution of the net doping concentration in the region (Figure 3 between from there to N ⁺ cathode layer 3 diagram 310 The region indicated by a thick arrow in FIG. 5 becomes a neutral region without being depleted. In other words, since the N cathode buffer layer 4 can stop the depletion layer from extending on the anode side by a certain distance from the N ⁺ cathode layer 3, the depletion layer can be prevented from reaching the N ⁺ cathode layer 3.

Next, the thickness of the diode according to the first embodiment will be described. FIG. 4 is a characteristic diagram showing the relationship of the yield rate to the device final thickness of the diode according to the first embodiment. 4, X _c is a distance from the PN junction surface of the diode 100 to a position where the integrated value of the impurity concentration reaches the critical integrated concentration n _c , and is 127 μm in the example shown in FIG. 3, for example. Although the device thickness is X _c ～1.4X _c in N cathode buffer layer 4, 0.8X _c and 0.9X N cathode buffer layer 4, _c is not.

Further, in FIG. 4, when a reverse bias of 1200 V is applied between the anode electrode 5 and the cathode electrode 6 and the current density of the reverse leakage current is 1 μA / cm ² or less, it is regarded as a non-defective product and exceeds 1 μA / cm ² . The product is defective. From FIG. 4, when the device thickness is at least X _c is sufficiently high and almost 99% yield rate, compared to that, when the device thickness is less than X _c, the non-defective rate. 46 It can be seen that it is extremely low at 68%.

This result shows that the presence of the N cathode buffer layer 4 is not affected by the above-described shielding of the dopant at the time of ion implantation and scratches on the ion implantation surface. If the device thickness is _Xc or more, that is, if the N cathode buffer layer 4 is present, a non-defective product ratio of 90% or more can be obtained even if the thickness is, for example, about 1 μm, but preferably the N cathode buffer layer having a thickness of 10 μm or more. 4 may be formed.

In the conventional example disclosed in Patent Document 4, the N cathode buffer layer 4 is not formed. Even if the N cathode buffer layer 4 is not formed, the expansion of the depletion layer can be stopped before reaching the N ⁺ cathode layer 3 if the device is somewhat thick. However, in this case, loss characteristics become a problem.

  Then, next, the results of comparing the diode according to the first embodiment (hereinafter referred to as an example) and three conventional diodes (hereinafter referred to as conventional example 1, conventional example 2 and conventional example 3). explain. The example is a diode 100 having the dimensions and concentration shown in FIG. 3, and the diode of the example was manufactured by the manufacturing process of FIG. Conventional example 1 and conventional example 2 are diodes having a conventional configuration as disclosed in Patent Document 4 above. Conventional Example 3 is a diode having a conventional configuration using a wafer obtained by diffusing high-concentration phosphorus in an FZ wafer as a substrate.

The dimensions and doping concentration of the diode of Conventional Example 1 are shown in FIG. In FIG. 5, reference numerals 500, 501, 502, and 503 denote the diode, the N ⁻ drift layer, the P anode layer, and the N ⁺ cathode layer of Conventional Example 1, respectively. In Conventional Example 1, an N-type FZ wafer having a concentration lower than that of the example having a concentration of 8 × 10 ¹³ atoms / cc was used as a starting wafer. Then, using this FZ wafer as a semiconductor substrate, the front surface forming process of the semiconductor substrate was performed in the same manner as in the example, and electron beam irradiation and heat treatment were performed. Thereafter, the back surface of the semiconductor substrate was ground to a substrate thickness of 160 μm, and wet etching with hydrofluoric acid was performed to manufacture a diode 500 having a final thickness of 140 μm.

The dimensions and doping concentrations of the diode of Conventional Example 2 are shown in FIG. In FIG. 6, reference numerals 600, 601, 602, and 603 denote the diode, N ⁻ drift layer, P anode layer, and N ⁺ cathode layer of Conventional Example 2, respectively. In Conventional Example 2, an N-type CZ (Czochralski) wafer containing antimony was used as a starting wafer containing antimony up to a solid solution limit of 2 × 10 ¹⁸ atoms / cc or more.

Then, a first epitaxial layer having a phosphorus concentration of 1.5 × 10 ¹⁴ atoms / cc is grown on the front surface of the CZ wafer to a thickness of 70 μm, and the phosphorus concentration is further 8 × 10 ¹³ atoms / cc. The second epitaxial layer, which is cc, was grown to a thickness of 70 μm, so that the total thickness of the epitaxial layers was 140 μm. This epitaxial wafer was used as a semiconductor substrate, and the structure of the front surface of the semiconductor substrate was produced by the same method and the same conditions as in the example and the conventional example 1.

However, before depositing AlSi 1.0% as an anode electrode on the front surface of the semiconductor substrate, the back surface of the substrate was ground to a total thickness of 350 μm. Thereafter, arsenic was ion-implanted into the ground surface at a dose of 1.0 × 10 ¹⁵ atoms / cm ² and heat treatment was performed at 1000 ° C. for 30 minutes. This is to reduce the contact resistance between the N ⁺ cathode layer 603 and a cathode electrode (not shown). Finally, a metal film was formed on the surface of the N ⁺ cathode layer 603 in the order of Ti, Ni, and Au to form a cathode electrode.

Conventionally, the reason why an N-type CZ wafer containing antimony or arsenic at a concentration limit of solid solution as in Conventional Example 2 is used as a substrate is as follows. In the diode 600 of Conventional Example 2, the N-type CZ wafer portion remains as the N ⁺ cathode layer 603 with a thickness of 200 μm or more. At the time of current conduction, electrons as majority carriers flow through the N ⁺ cathode layer 603 in the thickness direction, so that a voltage drop occurs due to the resistance component of this portion.

Since the resistance value when the concentration of antimony is 2 × 10 ¹⁸ atoms / cc or more is about 0.05 mΩ, a voltage drop of 10 mV or more occurs at the rated current of 150 A. In order to minimize this voltage drop, it is necessary to reduce the resistance of the N ⁺ cathode layer 603, that is, the resistance of the CZ wafer. For this reason, in the conventional device, a wafer containing antimony or the like having a concentration of the solid solution limit is used.

Here, regarding the concentration of the solid solution limit, theoretically, this concentration is uniquely determined. However, in actual manufacturing, the process concentration such as temperature at the time of manufacturing is reflected, and the concentration does not become constant but has a certain width. For example, in the case of a CZ silicon wafer containing antimony, the actual antimony concentration (room temperature) in the substrate has a width of about 5 × 10 ¹⁷ to 2 × 10 ¹⁸ atoms / cc. This is because the segregation coefficient of antimony is much lower than 0.023 and 1, and the antimony concentration distribution in the CZ wafer tends to be non-uniform. Therefore, the solid solution limit concentration (solid solubility) is broadly defined as having a width of about 50% and showing a concentration of about 5 × 10 ¹⁷ atoms / cc or more. Therefore, in the case of the present invention, the concentration of the N-type element in the fourth semiconductor layer is preferably lower than this broadly defined solution limit concentration, and in the case of antimony, it is at least lower than 5 × 10 ¹⁷ atoms / cc. Is desirable.

The dimensions and doping concentration of the diode of Conventional Example 3 are shown in FIG. In FIG. 7, reference numerals 700, 701, 702, and 703 denote the diode, the N ⁻ drift layer, the P anode layer, and the N ⁺ cathode layer of Conventional Example 3, respectively. In Conventional Example 3, an N-type FZ wafer having a phosphorus concentration of 5 × 10 ¹³ atoms / cc and a thickness of 250 μm was used as the semiconductor substrate. Then, high-concentration phosphorus was diffused deeply from the back surface of the semiconductor substrate at 1300 ° C. for 100 hours. At this time, the surface concentration of phosphorus on the back side of the substrate was about 1 × 10 ²⁰ atoms / cc, and the diffusion depth was 170 μm.

Next, the structure of the front surface of the semiconductor substrate was produced in the same manner as in Example and Conventional Example 1. Finally, a metal film was formed in the order of Ti, Ni and Au on the surface of the N ⁺ cathode layer 703 to form a cathode electrode (not shown). At that time, in Conventional Example 3, the cathode electrode was formed while the thickness of the semiconductor substrate was kept at 250 μm without grinding the back surface of the substrate.

  In Conventional Example 1, since the thickness of the wafer is as thin as about 100 μm at the final stage of the manufacturing process and handling is difficult, the structure of Conventional Example 2 or Conventional Example 3 is generally used. However, in recent years, with the improvement of thin wafer handling technology and processing technology, Conventional Example 1, which is advantageous in terms of switching loss, has come to be frequently used.

FIG. 8 is a characteristic diagram showing a trade-off characteristic of forward voltage-reverse recovery loss in the above-described embodiment and conventional examples 1-3. As is apparent from FIG. 8, the embodiment has the best loss characteristics. The loss in Conventional Example 1 and Conventional Example 2 is lower than that in Conventional Example 3, but is about 5 to 10% higher than the loss in Example. This is because the N cathode buffer layer 4 having a higher concentration than the average concentration of the N ⁻ drift layer 1 is provided in the embodiment.

  FIG. 9 is a diagram showing a simulation result showing the carrier distribution during conduction in the above-described embodiment and conventional examples 1 to 3. In FIG. 9, the thick solid line, the broken line, the alternate long and short dash line, and the dotted line are the carrier distribution during conduction in the embodiment, the carrier distribution during conduction in Conventional Example 1, the carrier distribution during conduction in Conventional Example 2, and the conduction in Conventional Example 3, respectively. The carrier distribution at the time is shown. In FIG. 9, the thin solid line, the broken line, the alternate long and short dash line, and the dotted line are the concentration distribution of FIG. 3 of the embodiment, the concentration distribution of FIG. 5 of the conventional example 1, the concentration distribution of FIG. This corresponds to the concentration distribution of FIG.

As shown in FIG. 9, in the diode 500 of Conventional Example 1, surplus carriers during conduction are modulated by almost 140 μm of the substrate thickness. On the other hand, in the diode 100 of the embodiment, since the thickness of 20 μm of the N cathode buffer layer 4 (not shown in the upper diode 100 in FIG. 9) is high, the concentration modulation region is substantially In addition, the N ⁻ drift layer 1 has only a thickness of 120 μm. As described above, the effective thickness of the N ⁻ drift layer 1 is reduced, so that the loss of the example is about 10% smaller than the loss of the conventional example 1.

In the diode 600 of the conventional example 2, since the N ⁺ cathode layer 603 has a high concentration (about 2 × 10 ¹⁸ atoms / cc), it is the low concentration epitaxial layer, that is, the N ⁻ , that determines the loss characteristics during conduction and switching. The drift layer 601 has a thickness of 120 μm. However, since there is a region where excess carriers remain on the cathode electrode side (not shown) from the boundary between the N ⁻ drift layer 601 and the N ⁺ cathode layer 603, the loss of the conventional example 2 is larger than the loss of the example. Is about 5% larger.

In the diode 700 of Conventional Example 3, the reverse recovery loss is about 44% larger than that of the example. This is because, as shown in FIG. 9, the concentration distribution of the high-concentration diffusion layer, that is, the N ⁺ cathode layer 703 changes more slowly than the concentration distributions of the example, conventional example 1 and conventional example 2. This is because the modulation region of the surplus carrier is about 20% longer than those of the example, the conventional example 1 and the conventional example 2.

  10 and 11 are waveform diagrams showing the minute current reverse recovery waveforms of Example and Conventional Example 3, respectively. In any case, the breaking current was set to 20 A, which is 1/10 of the rated current. As shown in FIG. 10, the diode 100 of the example has soft recovery characteristics without oscillation when the DC bus voltage is 900V (about 75% of the rated voltage 1200V).

  On the other hand, as shown in FIG. 11, the diode 700 of Conventional Example 3 oscillates with a steep surge voltage. The reason why such a snappy waveform is obtained is that in the conventional example 3, the 80 μm thick portion on the anode side has a high resistance, and the expansion width of the space charge region at the time of reverse recovery is about 20% larger than that in the example. This is because the carrier is swept away and exhausted. Note that the minute current reverse recovery waveforms of Conventional Example 1 and Conventional Example 2 are the same as those of the example.

Next, since it is necessary to carefully adjust the concentration of the N cathode buffer layer 4, the concentration of the N cathode buffer layer 4 will be described. FIG. 12 is a characteristic diagram showing the relationship between the breakdown voltage and the average concentration of the N cathode buffer layer 4 in the diode 100 of the example, and FIG. 13 is a schematic diagram thereof. In FIG. 13, the average concentration N _4m in the width X ₄ portion of the N cathode buffer layer 4 is increased from N _d (about 8 × 10 ¹³ atoms / cc) to 20 N _d (about 1.6 × 10 ¹⁵ atoms / cc). It is changing.

Here, N _d is, N ^- the integrated value of the concentration of the drift layer 1 from the PN junction to a distance X _1, is a value obtained by averaging by X _1. In the diode 100 of the example, N _d is 8 × 10 ¹³ atoms / cc which is the same as the concentration of the N ⁻ drift layer 1. When the average concentration N _4m of the N cathode buffer layer 4 is the same N _d as that of the drift layer, it corresponds to the conventional example 1, and its breakdown voltage is B as shown in FIG.
Vk (= 1430V).

As the average concentration N _4m of the N cathode buffer layer ₄ is increased, the breakdown voltage decreases when N _4m exceeds 20 N _d and decreases to BV ₀ . This BV ₀ is a withstand voltage value when the concentration of the N cathode buffer layer 4 is sufficiently high, and is 1250V. When the concentration of the N cathode buffer layer 4 is sufficiently high, this corresponds to Conventional Example 2. That is, when the concentration of N cathode buffer layer 4 is more than 20 N _d, breakdown voltage to the same level as the conventional example 2 is reduced. Therefore, the concentration of the N cathode buffer layer 4 is desirably N _d or more and 20 N _d or less.

  Next, the process of thinning the substrate by grinding the back surface of the substrate will be described in detail. First, the back surface of the silicon substrate is mechanically shaved using an abrasive slurry (back grind), so that the total thickness is about 160 μm. Next, either chemical etching (wet etching), chemical mechanical polishing (CMP), or dry polishing is performed, or an appropriate combination thereof is performed, and the ground surface on the back surface of the substrate is removed to a thickness of 3 to 20 μm. As a result, a stress layer such as a grinding strain formed by grinding the back surface of the substrate is removed. In the diode 100 of the above embodiment, the ground surface is removed with a thickness of 20 μm to remove stress, and the total thickness is finally made 140 μm.

  In the case of performing chemical etching at the time of removing stress, the silicon substrate is adsorbed and held on a turntable, and etching is performed by applying a hydrofluoric acid or nitric acid-based etching solution whose etching rate is controlled while rotating the silicon substrate. At that time, the etching solution is circulated and used.

  The relationship between the rate of non-defective products with respect to the etching rate at the time of stress removal by chemical etching was examined, and the result will be described. FIG. 14 is a characteristic diagram showing the relationship of the reverse breakdown voltage non-defective rate to the etching rate. As shown in FIG. 14, when the etching process is performed at an etching rate of 0.25 to 0.45 μm / sec, the state of the etched surface is improved, and the reverse breakdown voltage non-defective rate (above the rated voltage) is 90%. That's it. On the other hand, when the etching rate is 0.25 μm / sec or less, sharp unevenness is generated on the etched surface, so that the reverse breakdown voltage non-defective rate decreases.

  On the other hand, when the etching rate is 0.45 μm / sec or more, unevenness occurs on the etched surface, the flatness (flatness) of the surface is not uniform, and the yield rate decreases. Therefore, in the initial stage of the etching solution, it is preferable to set the etching rate to about 0.45 μm / sec and replace the etching solution when the etching rate reaches 0.25 μm / sec.

  Moreover, since the relationship of the reverse pressure | voltage resistant good product rate with respect to the etching amount at the time of the stress removal by chemical etching was investigated, the result is demonstrated. FIG. 15 is a characteristic diagram showing the relationship of the reverse breakdown voltage non-defective rate to the etching amount. As shown in FIG. 15, when the etching amount is 3 μm or more, the reverse breakdown voltage non-defective product rate becomes 90% or more. On the other hand, when the etching amount is less than 3 μm, the stress layer generated by grinding the back surface of the substrate cannot be sufficiently removed, and the yield rate is reduced. Therefore, when removing the stress layer generated by grinding, the ground surface on the back surface of the substrate may be removed with a thickness of 3 to 20 μm.

According to the first embodiment, when a reverse bias is applied to the diode 100, the depletion layer extends to the N ⁻ drift layer 1 and reaches the N cathode buffer layer 4, but stops in the middle of the N cathode buffer layer 4. Therefore, it does not reach the N ⁺ cathode layer 3. Therefore, it is possible to suppress the reverse leakage current from flowing through the diode 100. Further, the semiconductor substrate is ground and thinned, and ion implantation and thermal implantation element activation are performed on the ground surface, whereby the diode 100 with less reverse leakage current can be manufactured.

Embodiment 2. FIG.
In the second embodiment, the diode 100 shown in FIG. 1 is manufactured by a procedure different from that of the first embodiment. The configuration of the diode of the second embodiment is the same as that of the diode 100 of the first embodiment shown in FIG. In the following description, descriptions overlapping with those of the first embodiment are omitted.

FIG. 16 is an explanatory diagram showing an example of the doping concentration of the diode of the second embodiment. As shown in FIG. 16, in the second embodiment, the concentration distribution of the N cathode buffer layer 4 is not uniform as in the first embodiment, and gradually decreases from the cathode side toward the anode side, for example. The N cathode buffer layer 4 having such a concentration distribution is formed, for example, by diffusing selenium (Se) from the cathode side, as will be described later. In FIG. 16, Se with an arrow indicates that the dopant (N cathode buffer layer 4) is selenium. Similarly, the dopant of the portion (N ⁺ cathode layer 3) indicated by P with an arrow is phosphorus.

17 and 18 are cross-sectional views of relevant parts showing the manufacturing process according to the second embodiment. First, as indicated by reference numeral 1700 in FIG. 17, an N-type FZ wafer 1701 having a diameter of, for example, 5 inches and having a phosphorus concentration of 8 × 10 ¹³ atoms / cc is prepared as a starting wafer. Next, as indicated by reference numeral 1710, an N-type epitaxial layer 1702 is grown on the front side of the N-type FZ wafer 1701. This N type epitaxial layer 1702 becomes the N ⁻ drift layer 1 of the diode 100. This epitaxial wafer is used as a semiconductor substrate. Reference numeral 1720 indicates a profile of the impurity concentration of the semiconductor substrate.

  Next, as indicated by reference numeral 1730, standard diode process steps are performed to form a P anode layer 2 and a guard ring edge structure (not shown) on the surface of the N-type epitaxial layer 1702. Further, an insulating film 7 is provided on the surface of the P anode layer 2, and a contact hole is opened in the insulating film 7. Reference numeral 1740 indicates a profile of the impurity concentration of the semiconductor substrate in this state.

Thereafter, heat treatment is performed by irradiating the semiconductor substrate with an electron beam. Next, as indicated by reference numeral 1800 in FIG. 18, the surface of the N-type FZ wafer 1701 where the N-type epitaxial layer 1702 is not laminated, that is, the back surface of the substrate is ground to a total thickness of 150 μm. To do. Thereafter, the ground surface is wet-etched with hydrofluoric acid to make the final thickness 130 μm. In the second embodiment, the N ⁻ drift layer 1 is exposed by this wet etching. Reference numeral 1810 indicates a profile of the impurity concentration of the semiconductor substrate in this state.

Next, as indicated by reference numeral 1820, selenium is ion-implanted into the back surface of the substrate at a dose of 1 × 10 ¹² atoms / cm ² . In the cross-sectional view denoted by reference numeral 1820, a circle denoted by reference numeral 1801 represents injected selenium. Reference numeral 1830 indicates a profile of the impurity concentration of the semiconductor substrate in this state.

Next, as indicated by reference numeral 1840, heat treatment is performed at 600 ° C. for 1 hour. As a result, the injected selenium 1801 diffuses to a depth of about 10 μm from the back surface of the substrate to the anode side. Therefore, the thickness of the N ⁻ drift layer 1 and the N cathode buffer layer 4 at this stage is 120 μm and 10 μm, respectively. Reference numeral 1850 indicates a profile of the impurity concentration of the semiconductor substrate in this state.

Next, as indicated by reference numeral 1860, an AlSi 1% anode electrode 5 is formed on the surface of the P anode layer 2. Thereafter, phosphorus is ion-implanted on the back surface of the substrate with an acceleration voltage of 45 keV and a dose of 1 × 10 ¹⁵ atoms / cm ² . The ion implantation surface is irradiated with a YAG second harmonic laser at an energy density of 4 J / cm ² to activate the implanted phosphorus to form the N ⁺ cathode layer 3.

Finally, a metal film is formed in the order of Ti, Ni and Au on the surface of the N ⁺ cathode layer 3 to form the cathode electrode 6, thereby completing the diode 100. Reference numeral 1870 denotes a profile of the impurity concentration of the completed diode 100.

According to the second embodiment, since the dopant is introduced into the N cathode buffer layer 4 by the ion implantation method, the concentration of the N cathode buffer layer 4 can be accurately controlled. If the dopant of the N cathode buffer layer 4 is selenium, the diffusion coefficient at 1000 ° C. is as high as 3 × 10 ⁻¹¹ cm ² / sec, which is desirable because it diffuses about 10 μm. However, instead of selenium, phosphorus is used as a dopant. It may be used.

In that case, phosphorus may be ion-implanted with an acceleration voltage of 720 keV and a dose of 1 × 10 ¹² atoms / cm ² . Then, the phosphorus range is 0.8 μm, the depth of the concentration distribution is about 1.0 μm, and the peak concentration of the distribution is about 3 × 10 ¹⁶ atoms / cc. Since the integral value of the impurity concentration of the N cathode buffer layer 4 at this time is 1.5 × 10 ¹² atoms / cm ² , the depletion layer at the time of reverse bias can be sufficiently stopped by the N cathode buffer layer 4.

Embodiment 3 FIG.
In the third embodiment, the diode 100 shown in FIG. 1 is manufactured by a procedure different from that of the first embodiment. The configuration of the diode of the third embodiment is the same as that of the diode 100 of the first embodiment shown in FIG. In the following description, descriptions overlapping with those of the first embodiment are omitted.

FIG. 19 is an explanatory diagram showing an example of the doping concentration of the diode of the third embodiment. As shown in FIG. 19, in the third embodiment, as in the second embodiment, the concentration distribution of the N cathode buffer layer 4 gradually decreases from, for example, the cathode side toward the anode side. In addition, a broad buffer layer is formed in the N ⁻ drift layer 1 such that the impurity concentration decreases from the center toward the anode side and the cathode side. Such a broad buffer layer and its effect are as disclosed in the above-mentioned Patent Document 4.

In FIG. 19, Se with an arrow indicates that the dopant (N cathode buffer layer 4) is selenium. Similarly, the dopant of the portion (N ⁺ cathode layer 3) indicated by P with an arrow is phosphorus. Further, the dopant (broad buffer layer) indicated by H by an arrow is a light ion, for example, a proton.

20-22 is principal part sectional drawing which shows the manufacturing process concerning Embodiment 3. FIG. First, as indicated by reference numeral 2000 in FIG. 20, an N-type FZ wafer 2001 having a diameter of 5 inches, for example, having a phosphorus concentration of 5 × 10 ¹³ atoms / cc is prepared as a starting wafer. Next, as indicated by reference numeral 2010, standard diode process steps are performed to form a P anode layer 2 and a guard ring edge structure (not shown) on the front surface of the N-type FZ wafer 2001. Further, an insulating film 7 is provided on the surface of the P anode layer 2, and a contact hole is opened in the insulating film 7. Reference numeral 2020 indicates a profile of the impurity concentration of the semiconductor substrate in this state.

Next, as indicated by reference numeral 2100 in FIG. 21, protons are irradiated from the P anode layer 2 side at a dose of 2 × 10 ¹¹ atoms / cm ² . In the cross-sectional view denoted by reference numeral 2100, a cross with a reference numeral 2002 represents a proton introduced into the N-type FZ wafer 2001. Reference numeral 2110 denotes a profile of the impurity concentration of the semiconductor substrate in this state.

  Next, as indicated by reference numeral 2120, the surface of the N-type FZ wafer 2001 on which the P anode layer 2 is not formed, that is, the back surface of the substrate is ground to a total thickness of 150 μm. Thereafter, the ground surface is wet-etched with hydrofluoric acid to make the final thickness 130 μm. Reference numeral 2130 indicates a profile of the impurity concentration of the semiconductor substrate in this state.

Next, as indicated by reference numeral 2140, selenium 1801 is ion-implanted into the back surface of the substrate at a dose of 1 × 10 ¹² atoms / cm ² . Reference numeral 2150 indicates a profile of the impurity concentration of the semiconductor substrate in this state.

Next, as shown by reference numeral 2200 in FIG. 22, heat treatment is performed at 600 ° C. for 1 hour. As a result, the injected selenium 1801 diffuses to a depth of about 10 μm from the back surface of the substrate to the anode side. In addition, protons introduced into the N-type FZ wafer 2001 become donors, and a broad buffer layer is formed. Therefore, at this stage, the thickness of the broad buffer layer serving as the N ⁻ drift layer 1 is 120 μm, and the thickness of the N cathode buffer layer 4 is 10 μm. Reference numeral 2210 indicates a profile of the impurity concentration of the semiconductor substrate in this state.

Next, as indicated by reference numeral 2220, the anode electrode 5 of AlSi 1% is formed on the surface of the P anode layer 2. Thereafter, phosphorus is ion-implanted on the back surface of the substrate with an acceleration voltage of 45 keV and a dose of 1 × 10 ¹⁵ atoms / cm ² . In the cross-sectional view indicated by reference numeral 2220, a circle indicated by reference numeral 2003 represents injected phosphorus. Reference numeral 2230 indicates a profile of the impurity concentration of the semiconductor substrate in this state.

Next, as indicated by reference numeral 2240, the ion implantation surface is irradiated with a YAG second harmonic laser at an energy density of 4 J / cm ² to activate the implanted phosphorus 2003 to form the N ⁺ cathode layer 3. Finally, a metal film is formed in the order of Ti, Ni and Au on the surface of the N ⁺ cathode layer 3 to form the cathode electrode 6, thereby completing the diode 100. Reference numeral 2250 indicates an impurity concentration profile of the completed diode 100.

  According to Embodiment 3, since the dopant is introduced into the N cathode buffer layer 4 by the ion implantation method, the concentration of the N cathode buffer layer 4 can be accurately controlled. Further, the broad buffer layer can be formed without performing epitaxial growth. As in the second embodiment, phosphorus may be used as a dopant for the N cathode buffer layer 4.

  In Embodiments 1 to 3 described above, examples in which the present invention is applied to a diode have been described. However, the present invention can also be applied to an IGBT. For example, when Embodiment 3 is applied to an FS-IGBT (Field Stop IGBT), not only low loss but also turn-off with suppressed oscillation can be realized.

This is because the space charge region extends from the PN junction on the front side of the device toward the back side at turn-off, but by applying a broad buffer structure, the N ⁻ drift is similar to the reverse recovery of the diode. This is because the electric field strength can be once reduced in the middle of the layer and the spread of the space charge region can be suppressed. As a result, carriers remain on the back side and the carrier is not depleted, so that a sharp increase in turn-off surge voltage can be suppressed.

  In a normal NPT-IGBT (non-punch-through IGBT) or FS-IGBT manufacturing process, an FZ bulk wafer is ground to a thickness of about 100 μm, ion implantation is performed on the ground surface, and heat treatment is performed. There is a process to perform. Therefore, by applying the manufacturing process of Embodiment 3 to such a manufacturing process, an IGBT having a broad buffer structure can be easily manufactured. Therefore, in a power converter such as a PWM inverter using an IGBT module, it is possible to suppress overvoltage breakdown and EMI noise.

  FIG. 23 and FIG. 24 are diagrams showing application examples of the diodes and FS-IGBTs of the first to third embodiments described above. An AC-AC inverter-converter 2300 shown in FIG. 23 can efficiently control an induction motor, a servo motor, and the like, and is widely used in industries, electric railways, and the like. A power factor correction circuit (PFC circuit) 2400 shown in FIG. 24 is a circuit that improves the waveform by controlling the input current of AC-AC conversion in a sine wave shape, and is used for a switching power supply.

  As described above, according to each embodiment, it is possible to manufacture a diode having a reverse recovery time and a loss that are significantly reduced as compared with the prior art and improved soft recovery characteristics with a high product yield. In addition, an IGBT module or IPM that takes into consideration environmental problems with low electrical loss and radiated electromagnetic noise can be realized.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions and concentrations described in the embodiments are examples, and the present invention is not limited to these values. In each embodiment, the first conductivity type is N-type and the second conductivity type is P-type. However, in the present invention, the first conductivity type is P-type and the second conductivity type is N-type. It holds.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for power semiconductor devices, and are particularly suitable for diodes or IGBTs that have high speed and low loss and have soft recovery characteristics.

1 is a cross-sectional view of a semiconductor device according to a first embodiment. FIG. 6 is a main-portion cross-sectional view of the semiconductor device manufacturing process according to the first exemplary embodiment; 6 is an explanatory diagram of a doping concentration of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a characteristic diagram of a non-defective product ratio—device final thickness of the semiconductor device according to the first embodiment; It is explanatory drawing of the dimension and doping concentration of the prior art example 1. FIG. It is explanatory drawing of the dimension and doping concentration of the prior art example 2. FIG. It is explanatory drawing of the dimension and doping concentration of the prior art example 3. FIG. It is a trade-off characteristic figure of reverse recovery loss to a forward voltage of an example and conventional examples 1-3. It is a figure which shows the simulation result of the carrier distribution of an Example and the prior art examples 1-3. It is a minute electric current reverse recovery waveform figure of an Example. It is a minute electric current reverse recovery waveform figure of the prior art example 3. It is a characteristic view of the withstand voltage with respect to the average concentration of the cathode buffer layer of the example. It is a schematic diagram of the characteristic of the withstand voltage with respect to the average density | concentration of the cathode buffer layer of an Example. It is a characteristic view of the reverse pressure | voltage resistant good product rate with respect to the etching rate at the time of stress removal. It is a characteristic view of the reverse pressure | voltage resistant good product rate with respect to the etching amount at the time of stress removal. 6 is an explanatory diagram of a doping concentration of a semiconductor device according to a second embodiment; FIG. FIG. 10 is a main-portion cross-sectional view of the semiconductor device manufacturing process according to the second embodiment; FIG. 18 is a fragmentary cross-sectional view of the manufacturing process following FIG. 17. FIG. 6 is an explanatory diagram of a doping concentration of a semiconductor device according to a third embodiment. FIG. 10 is a main-portion cross-sectional view of the semiconductor device manufacturing process according to the third embodiment; It is principal part sectional drawing of the manufacturing process following FIG. FIG. 22 is a fragmentary cross-sectional view of the manufacturing process following FIG. 21. It is a circuit diagram of an AC-AC inverter-converter. It is a circuit diagram of a power factor improvement circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st semiconductor layer 2 2nd semiconductor layer 3 3rd semiconductor layer 4 4th semiconductor layer 5 1st electrode 6 2nd electrode

Claims (10)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type having a higher concentration than the first semiconductor layer and provided in contact with the first semiconductor layer on one main surface side of the first semiconductor layer;
A third semiconductor layer of a first conductivity type having a higher concentration than the first semiconductor layer and provided on the other main surface side of the first semiconductor layer;
The first semiconductor layer and the third semiconductor layer that are higher in concentration than the first semiconductor layer and lower in concentration than the third semiconductor layer, and between the first semiconductor layer and the third semiconductor layer. A fourth semiconductor layer of the first conductivity type provided in contact with both,
A first electrode electrically connected to the second semiconductor layer;
A second electrode electrically connected to the third semiconductor layer;
With
A thickness of the fourth semiconductor layer in a direction from one main surface to the other main surface of the first semiconductor layer is larger than a thickness of the third semiconductor layer in the same direction. . A first semiconductor layer of a first conductivity type made of an FZ semiconductor substrate;
A second semiconductor layer of a second conductivity type having a higher concentration than the first semiconductor layer and provided in contact with the first semiconductor layer on one main surface side of the first semiconductor layer;
A third semiconductor layer of the first conductivity type formed by diffusion on a surface obtained by reducing the thickness of the other main surface of the first semiconductor layer by grinding;
A fourth semiconductor layer of the first conductivity type,
The third semiconductor layer has a higher concentration than the first semiconductor layer;
The fourth semiconductor layer is located between the first semiconductor layer and the third semiconductor layer, and is higher in concentration than the first semiconductor layer and lower in concentration than the third semiconductor layer;
A first electrode electrically connected to the second semiconductor layer;
A second electrode electrically connected to the third semiconductor layer;
With
A thickness of the fourth semiconductor layer in a direction from one main surface to the other main surface of the first semiconductor layer is larger than a thickness of the third semiconductor layer in the same direction. . A fourth semiconductor layer of the first conductivity type composed of an FZ semiconductor substrate or a CZ semiconductor substrate;
A first conductivity type first semiconductor layer formed by epitaxial growth at a lower concentration than the fourth semiconductor layer and on one main surface side of the fourth semiconductor layer;
A second semiconductor layer of a second conductivity type having a higher concentration than the first semiconductor layer and provided in contact with the first semiconductor layer on one main surface side of the first semiconductor layer;
A third semiconductor layer of the first conductivity type formed by diffusion on a surface obtained by reducing the thickness of the other main surface of the fourth semiconductor layer by grinding;
The third semiconductor layer has a higher concentration than the fourth semiconductor layer;
The fourth semiconductor layer is located between the first semiconductor layer and the third semiconductor layer;
A first electrode electrically connected to the second semiconductor layer;
A second electrode electrically connected to the third semiconductor layer;
With
A thickness of the fourth semiconductor layer in a direction from one main surface to the other main surface of the first semiconductor layer is larger than a thickness of the third semiconductor layer in the same direction. . 4. The semiconductor device according to claim 1, wherein the concentration of the fourth semiconductor layer is 1 × 10 ¹⁴ atoms / cc or more and 1 × 10 ¹⁵ atoms / cc or less.   5. The thickness of the fourth semiconductor layer in a direction from one main surface of the first semiconductor layer to the other main surface is 0.1 μm or more. 6. A semiconductor device according to 1. In manufacturing the semiconductor device according to claim 3,
The first conductive type first semiconductor layer is stacked on the first conductive type fourth semiconductor layer, and the concentration of the element indicating the first conductive type in the fourth semiconductor layer is the same as the fourth semiconductor layer. Forming a second conductivity type second semiconductor layer on a surface layer of the first semiconductor layer using a first conductivity type semiconductor substrate having a solid solubility less than a solid solubility limit of a semiconductor material constituting the layer;
Forming a first electrode in contact with the second semiconductor layer;
Grinding the surface layer of the fourth semiconductor layer to expose the fourth semiconductor layer to a desired thickness of the semiconductor substrate;
Forming a third semiconductor layer of a first conductivity type on a surface layer of a surface exposed by grinding of the fourth semiconductor layer;
Forming a second electrode in contact with the third semiconductor layer;
A method for manufacturing a semiconductor device, comprising: In manufacturing the semiconductor device according to claim 2,
The first semiconductor layer of the first conductivity type, and the concentration of the element showing the first conductivity type in the first semiconductor layer is a solid solubility less than the solid solution limit of the semiconductor material constituting the first semiconductor layer. Forming a second conductive type second semiconductor layer on a front surface layer of the first semiconductor layer using a first conductive type semiconductor substrate;
Grinding the surface layer on the back surface of the first semiconductor layer to expose the first semiconductor layer to a desired thickness;
Forming a first conductive type fourth semiconductor layer on a surface layer of a surface exposed by grinding of the first semiconductor layer;
Forming a first electrode in contact with the second semiconductor layer;
Forming a third semiconductor layer of a first conductivity type shallower than the fourth semiconductor layer on a surface layer of a surface exposed by grinding of the first semiconductor layer;
Forming a second electrode in contact with the third semiconductor layer;
A method for manufacturing a semiconductor device, comprising:   The method further comprises introducing protons into the first semiconductor layer by irradiating the semiconductor substrate with protons after forming the second semiconductor layer and before grinding the semiconductor substrate. 8. A method for producing a semiconductor device according to 7.   In the step of forming the third semiconductor layer, a first conductivity type impurity is ion-implanted into a surface exposed by grinding, and the ion-implanted surface is irradiated with laser light to electrically activate the implanted impurity. The method for manufacturing a semiconductor device according to claim 6, wherein the method is performed.   10. The step of grinding the semiconductor substrate includes removing the stress by performing wet etching after grinding and removing a surface exposed by grinding with a thickness of 3 μm or more and 20 μm or less. The manufacturing method of the semiconductor device as described in any one.

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