JP2013247248A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which improves a withstanding voltage and reduces a leakage current.SOLUTION: A semiconductor device manufacturing method comprises: forming a surface element structure of an RC-IGBT having a MOS gate structure on a surface side of a semiconductor substrate to become a drift region 1; subsequently polishing the semiconductor substrate from a rear face side to obtain a thin plate of the semiconductor substrate; subsequently, performing first ion implantation of selenium into a rear face of the semiconductor substrate; subsequently, diffusing selenium by furnace annealing to form a field stop region 11; subsequently, selectively performing second ion implantation of phosphorous into the field stop region 11; subsequently selectively performing third ion implantation of boron into the field stop region 11; and diffusing phosphorous and boron by laser annealing to form an ntype region of a diode and a ptype region of an IGBT.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  As a semiconductor device in which an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor) and a diode (Diode) are formed on the same semiconductor substrate, for example, a reverse conducting IGBT (RC-IGBT: Reverse Conducting IGBT) is known.

In the RC-IGBT, for example, the p ⁺ type region of the IGBT and the n ⁺ type region of the diode are provided on the back surface of the n type semiconductor substrate serving as the drift region. An n-type field stop region having an impurity concentration higher than that of the drift region is provided between the p ⁺ -type region and the n ⁺ -type region and the drift region. The field stop region prevents a depletion layer extending from the emitter region from reaching the collector region during forward bias.

The following method has been proposed as a method for forming the RC-IGBT. The back surface of the semiconductor wafer is ground, and an n ⁺ type region is formed on the entire back surface of the ground semiconductor wafer. Thereafter, ion implantation is performed on the entire back surface of the semiconductor wafer on which the n ⁺ -type region is formed, thereby forming a p ⁺ -type region in the surface layer portion of the n ⁺ -type region. Then, patterning is performed by irradiating a laser beam to the diode portion of the p ⁺ type region and performing laser annealing to selectively form an n ⁺ type region in the p ⁺ type region (see, for example, Patent Document 1 below). .

As another method, the following method has been proposed. After forming the FS region in the surface layer on the back surface of the n ⁻ support substrate by ion implantation, the FS region is activated by annealing treatment. Next, a p collector region is formed in the surface layer of the FS region by ion implantation. Then, n ⁺ high concentration region of the formation region of the resist mask having an opening as a mask for example, phosphorus ions are implanted into part of the surface layer of the p collector region, forming the n ⁺ high concentration region. Next, laser annealing is performed to activate the p collector region and the n ⁺ high concentration region. In forming the FS layer, for example, phosphorus (P) is used as a dopant (see, for example, Patent Document 2 below).

Further, the following method has been proposed as a method of forming an IGBT having a field stop region alone. Selenium (Se) or phosphorus is ion-implanted from the back surface of the FZ wafer. Then, for example, heat treatment is performed at 1000 ° C. for 1 hour to diffuse the implanted ions to form an n ⁺ buffer layer. Subsequently, boron (B) is ion-implanted from the back surface of the FZ wafer. Then, for example, heat treatment is performed at 450 ° C. for 1 hour to diffuse the implanted boron ions. Further, instead of heat treatment, boron ions may be activated by irradiating laser light such as YAG laser by a double pulse method. The activated boron ions form a p ⁺ collector layer (see, for example, Patent Document 3 below).

As another method, the following method has been proposed. Selenium (or sulfur) is ion-implanted to form a field stop (FS) layer on the back surface of the semiconductor substrate. Then, a heat treatment with a temperature profile in the temperature range of 700 ° C. to 950 ° C. is applied for ion activation and drive diffusion. Thereafter, boron ions are implanted into the back surface of the semiconductor substrate, and a heat treatment at 350 ° C. to 500 ° C. is performed as an activation process to form a p ⁺ collector layer (see, for example, Patent Document 4 below).

Further, the following method has been proposed as a method of forming a diode having a field stop region alone. Selenium ions are implanted into the back surface of the substrate. Next, heat treatment is performed at 600 ° C. for 1 hour. Thereby, the injected selenium diffuses from the back surface of the substrate to the anode side, and an n cathode buffer layer is formed. Thereafter, phosphorus is ion-implanted into the back surface of the substrate. The ion implantation surface is irradiated with a YAG second harmonic laser to activate the implanted phosphorus to form an n ⁺ cathode layer (see, for example, Patent Document 5 below).

JP 2008-004867 A JP 2010-129697 A JP 2008-227414 A JP 2008-103562 A JP 2007-158320 A

  However, as a result of repeated studies by the present inventors, it has been newly found that the following problems occur. Since the field stop region of the conventional RC-IGBT is as shallow as about 1 μm, it is formed by laser annealing using phosphorus (P) as a dopant. This is because the diffusion coefficient of phosphorus is small, and laser annealing increases the temperature of the laser-irradiated part locally and instantaneously and activates the phosphorus implanted into the back surface of the semiconductor substrate with little diffusion. Because it can.

  Thus, in order to form the field stop region of the conventional RC-IGBT, first, a MOS gate structure and a termination structure region are formed on the front surface of the semiconductor substrate (hereinafter referred to as a front surface process). ). Next, the wafer is ground to a thickness of 200 μm or less to thin the wafer. Next, phosphorus is ion-implanted into the back surface of the semiconductor substrate and activated by laser irradiation. Thereby, a field stop region is formed on the back surface of the semiconductor substrate.

  However, in the conventional RC-IGBT having the field stop region formed in this way, the diffusion depth of the field stop region formed by phosphorus is as shallow as about 1 μm. The problem that is likely to occur occurs. In particular, the yield may be reduced by 10% or more compared to the IGBT alone. The reason is that the process of forming the back element structure of the RC-IGBT (hereinafter referred to as the back surface process) takes longer than the back surface process of the IGBT alone.

  Specifically, in the back surface process of RC-IGBT, an n cathode layer is formed in addition to forming a p collector layer on the back surface of the semiconductor substrate. For this reason, the number of times of the ion implantation process and the photolithography process is increased as compared with the back surface process of the IGBT alone forming only the p collector layer. As a result, the time during which the back surface of the semiconductor substrate is exposed is longer than the back surface process of the IGBT alone, and there arises a problem that the back surface of the semiconductor substrate is easily contaminated with scratches and particles.

  In order to solve such a problem, it is desirable to form a field stop region as deep as about 30 μm from the back surface of the semiconductor substrate. However, when a field stop region deeper than the conventional RC-IGBT is formed using phosphorus as a dopant as in the technique shown in Patent Document 2 described above, the diffusion coefficient of phosphorus is small, so that it is formed on the back surface of the semiconductor substrate. It is necessary to thermally diffuse the injected phosphorus at a temperature of 1100 ° C. or more for several hours or more.

  In this case, heat treatment is also applied to the gate structure and termination structure region of the MOSFET formed in the front surface process before the field stop region. For this reason, a deeper field stop region cannot be formed after the front surface process. Further, when the front surface process is performed after the field stop region is formed, the front surface process is performed in a state where the wafer is thinned, so that there is a possibility that the wafer is cracked or chipped.

Further, in the above-mentioned Patent Document 2, when the field stop region is formed using selenium having a diffusion coefficient larger than that of phosphorus, after the field stop region is formed, the p ⁺ type region of the IGBT is formed on the entire surface layer of the field stop region. After that, the n ⁺ type region of the diode is selectively formed on the surface layer of the p ⁺ type region of the IGBT. At this time, the n ⁺ type region of the diode is formed by ion implantation of phosphorus, for example, with a dose high enough to compensate the p ⁺ type region of the IGBT with the n-type impurity. Therefore, field stop region formed before the n ⁺ -type region of the diode is damaged by the ion implantation of phosphorus for forming the n ⁺ -type region of the diode. As a result, the carrier concentration in a shallow region from the back surface of the semiconductor substrate decreases, and the breakdown voltage of the RC-IGBT decreases.

  In addition, when the technology for forming the IGBT simple substance shown in Patent Document 4 described above is applied to the RC-IGBT, the heat treatment at about 500 ° C. for forming the IGBT single p-collector layer is performed by changing the RC collector IGBT p-collector layer. Although it can be activated, the n cathode layer of the RC-IGBT cannot be activated sufficiently. The reason is that the n cathode layer needs to be formed with an impurity concentration 10 times or more higher than that of the p collector layer, so that the heat treatment at about 500 ° C. cannot sufficiently recover defects caused by ion implantation.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device having a high breakdown voltage in order to solve the above-described problems caused by the conventional technology. It is another object of the present invention to provide a method for manufacturing a semiconductor device capable of reducing leakage current. It is another object of the present invention to provide a method for manufacturing a semiconductor device with a high yield.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention includes a semiconductor in which an insulated gate bipolar transistor and a diode are provided on the same first conductivity type semiconductor substrate. A device manufacturing method, wherein a first dopant of a first conductivity type is ion-implanted into a back surface of the semiconductor substrate, and a first conductivity type first semiconductor region having an impurity concentration higher than that of the semiconductor substrate by heat treatment. After the first formation step and the first formation step, a second conductivity type second dopant having a diffusion coefficient smaller than that of the first dopant and a second conductivity type second are formed on the back surface of the semiconductor substrate. And a second forming step of forming a first conductivity type second semiconductor region and a second conductivity type third semiconductor region by ion implantation of each of the three dopants and heat treatment. And features.

  In the semiconductor device manufacturing method according to the present invention, in the above-described invention, in the first forming step, the first dopant is ion-implanted into the entire back surface of the semiconductor substrate, and then heat treatment is performed using a heat treatment furnace. It is characterized by that.

  In the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, in the second forming step, after the second dopant is selectively ion-implanted into the back surface of the semiconductor substrate, The third dopant is ion-implanted in a region different from the region where the second dopant is ion-implanted, and then heat treatment is performed using a laser.

  In the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, in the second forming step, the third dopant is ion-implanted over the entire back surface of the semiconductor substrate, and then selectively applied to the back surface of the semiconductor substrate. The second dopant is ion-implanted and then heat treatment is performed using a laser.

  In addition, the semiconductor device manufacturing method according to the present invention is characterized in that, in the above-described invention, in the second formation step, the second semiconductor region constituting the diode is formed.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, in the second forming step, the third semiconductor region constituting the insulated gate bipolar transistor is formed.

  In addition, the semiconductor device manufacturing method according to the present invention is characterized in that, in the above-described invention, a grinding step of grinding a back surface of the semiconductor substrate is performed before the first forming step.

  The semiconductor device manufacturing method according to the present invention is characterized in that, in the above-described invention, the first dopant is selenium.

  In the semiconductor device manufacturing method according to the present invention, the second dopant is phosphorus in the above-described invention.

  The semiconductor device manufacturing method according to the present invention is characterized in that, in the above-described invention, the third dopant is boron.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention includes an insulated gate bipolar transistor and a diode provided on the same first conductivity type semiconductor substrate. A method of manufacturing a semiconductor device, comprising: a first implantation step of ion-implanting a first dopant of a first conductivity type into the back surface of the semiconductor substrate; and a first annealing for performing furnace annealing after the first implantation step. A first mask forming step of covering a back surface of the semiconductor substrate with a first mask in which a formation region of the first conductive type second semiconductor region of the diode is opened after the first annealing step; Using the one mask as a mask, a second implantation step of ion-implanting a second dopant of the first conductivity type into the back surface of the semiconductor substrate; a first removal step of removing the first mask; A second mask forming step of covering the back surface of the semiconductor substrate with a second mask in which a formation region of a second conductive type third semiconductor region of the insulated gate bipolar transistor is opened after the removing step; Using the mask as a mask, a third implantation step of ion-implanting a second dopant of the second conductivity type into the back surface of the semiconductor substrate, a second removal step of removing the second mask, and after the second removal step And a second annealing step of performing laser annealing on the back surface of the semiconductor substrate.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention includes an insulated gate bipolar transistor and a diode provided on the same first conductivity type semiconductor substrate. A method of manufacturing a semiconductor device, comprising: a first implantation step of ion-implanting a first dopant of a first conductivity type into the back surface of the semiconductor substrate; and a first annealing for performing furnace annealing after the first implantation step. And a third implantation step of ion-implanting a second dopant of a second conductivity type into the back surface of the semiconductor substrate after the first annealing step, and a first conductivity of the diode after the third implantation step. A first mask forming step of covering the back surface of the semiconductor substrate with a first mask in which a formation region of the second semiconductor region of the mold is opened, and a second mask of the first conductivity type using the first mask as a mask A second implantation step of ion-implanting a dopant, a first removal step of removing the first mask, and a second annealing step of performing laser annealing on the back surface of the semiconductor substrate after the first removal step. It is characterized by that.

  According to the above-described invention, after the first dopant is ion-implanted into the back surface of the semiconductor substrate to diffuse the first dopant to form the first semiconductor region, the second diffusion coefficient is smaller than that of the first dopant. The dopant is ion-implanted. For this reason, the second dopant does not hinder the formation of the first semiconductor region. Thereby, it can avoid that the carrier concentration of a 1st semiconductor region falls.

  The first semiconductor region is diffused at a depth of 1 μm or more from the back surface of the semiconductor substrate by furnace annealing. For this reason, even if the second dopant and the third dopant are ion-implanted at a dose amount higher than the dose amount of the first dopant on the back surface of the semiconductor substrate, the second dopant and the third dopant form the first semiconductor region. There is no inhibition. Thereby, it can avoid that the carrier concentration of a 1st semiconductor region falls.

  The second dopant and the third dopant are diffused by laser annealing. For this reason, the influence on the first semiconductor region of the thermal energy by the laser annealing for forming the second semiconductor region and the third semiconductor region is about 1 μm from the back surface of the semiconductor substrate. Thereby, it can be avoided that the impurity concentration distribution of the first semiconductor region is changed by thermal diffusion for forming the second semiconductor region and the third semiconductor region.

  The method for manufacturing a semiconductor device according to the present invention produces an effect that the breakdown voltage can be improved. In addition, there is an effect that the leakage current can be reduced. In addition, the yield can be increased.

It is sectional drawing which shows the semiconductor device concerning this invention. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. 6 is a characteristic diagram showing a carrier concentration distribution of the semiconductor device according to Example 1. FIG. 6 is a characteristic diagram showing electrical characteristics of the semiconductor device according to Example 2. FIG.

  Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
FIG. 1 is a sectional view showing a semiconductor device according to the present invention. A semiconductor device 100 shown in FIG. 1 includes an insulated gate bipolar transistor (IGBT) 110 and a diode 120 provided on the same semiconductor substrate. The diode 120 may be, for example, a free wheeling diode (FWD).

A p-type (second conductivity type) base region 2 is provided on the surface layer of the front surface of the semiconductor substrate which becomes the n ⁻ type (first conductivity type) drift region 1. Base region 2 has an impurity concentration that gradually decreases from the surface toward the inside of the semiconductor substrate. A p-type contact region 3 and an n ⁺ -type emitter region 4 are selectively provided on the surface layer of the base region 2. Contact region 3 and emitter region 4 are in contact with each other. A trench 5 that penetrates the base region 2 and reaches the drift region 1 is provided.

  A first electrode 6 is provided inside the trench 5 via a gate insulating film. The first electrode 6 functions as a gate electrode of the IGBT 110. The second electrode 8 is in contact with the contact region 3 and the emitter region 4. The second electrode 8 is electrically insulated from the first electrode 6 by the interlayer insulating film 7. The second electrode 8 functions as an emitter electrode of the IGBT 110 and an anode electrode of the diode 120. A passivation film (not shown) is provided on the surface of the second electrode 8.

An n ⁺ type field stop region (first semiconductor region) 11 is provided on the front surface layer of the semiconductor substrate. Field stop region 11 has a higher impurity concentration than drift region 1. In the surface layer of the field stop region 11, a p ⁺ type region (third semiconductor region) 9 is provided in the formation region of the IGBT 110. Further, an n ⁺ -type region (second semiconductor region) 10 is provided in the formation region of the diode 120. The p ⁺ type region 9 is a collector region of the IGBT 110. The n ⁺ type region 10 is a cathode region of the diode 120. The width of the p ⁺ type region 9 is preferably 288 μm or more. The width of the n ⁺ -type region 10 is preferably 96 μm or more. The reason is that since the snapback does not occur, the operation of the IGBT can be stabilized.

A third electrode 12 is provided on the surfaces of the p ⁺ type region 9 and the n ⁺ type region 10. The third electrode 12 functions as a collector electrode of the IGBT 110. Further, the third electrode 12 functions as a cathode electrode of the diode 120.

  Next, a method for manufacturing the semiconductor device 100 described above will be described. 2 to 10 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment. First, as shown in FIG. 2, a MOS gate structure such as a base region 2, a contact region 3, an emitter region 4, and a first electrode 6, or a base region 2 is formed on the front surface side of the semiconductor substrate to be the drift region 1. Further, a front surface element structure of the semiconductor device 100 such as a contact between the contact region 3 and the second electrode 8 is formed.

  Next, as shown in FIG. 3, after the front surface side of the semiconductor substrate is protected by, for example, a protective film (not shown), the back surface of the semiconductor substrate is ground until the thickness of the semiconductor substrate becomes 200 μm or less, for example. (Grinding process). In the case of etching, although it is not strictly grinding, in this specification, any means for thinning the semiconductor substrate is used, and therefore grinding including etching is performed.

Next, as shown in FIG. 4, the n-type first dopant is formed on the back surface of the ground semiconductor substrate, that is, on the surface opposite to the surface on which the front surface element structure of the drift region 1 is formed. For example, selenium (Se) is ion-implanted (first implantation step). At this time, the first dopant is ion-implanted into the entire back surface of the semiconductor substrate. In FIG. 4, a dotted line near the front surface of the back surface of the semiconductor substrate represents the implanted first dopant. The region where the first dopant is implanted is a region where the field stop region 11 is formed. The dose amount of the first dopant may be, for example, 1 × 10 ¹⁴ / cm ² or more.

  Next, a semiconductor substrate is placed in a processing chamber of a heat treatment furnace and heat treatment (furnace annealing) is performed to activate the first dopant implanted into the drift region 1 in the first implantation process (first annealing process). The furnace annealing treatment conditions may be, for example, a temperature of 900 ° C. or higher and 950 ° C. or lower and 30 minutes or longer and 2 hours or shorter. Thereby, as shown in FIG. 5, the field stop region 11 is formed in the surface layer of the drift region 1 over the entire back surface of the semiconductor substrate. The first implantation process and the first annealing process correspond to the first formation process.

The n-type first dopant may be a dopant having the following characteristics. For example, the first dopant is sufficiently deep at a temperature of, for example, 900 ° C. or more and 950 ° C. or less as compared to the depth of the p ⁺ -type region (third semiconductor region) 9 formed in a step after the first formation step. Any n-type dopant that has a diffusion coefficient that diffuses to the upper limit may be used. As such an n-type dopant, for example, sulfur (S) may be used in addition to selenium.

  Next, the protective film for protecting the front surface side of the semiconductor substrate is removed, and the second electrode 8 containing, for example, aluminum (Al) as a main component is formed on the front surface side of the semiconductor substrate. Next, a passivation film (not shown) is formed on the surface of the second electrode 8.

Next, as shown in FIG. 6, a resist mask (first mask) 21 in which the formation region of the n ⁺ -type region 10 is opened is formed on the back surface of the semiconductor substrate, that is, the surface of the field stop region 11 by photolithography. (First mask forming step).

  Next, as shown in FIG. 7, n-type second dopant is ion-implanted from the back surface side of the semiconductor substrate into the field stop region 11 using the resist mask 21 as a mask (second implantation step). As a result, the second dopant is implanted only into the field stop region 11 exposed at the opening of the resist mask 21.

  The second dopant used in the second implantation step preferably has a smaller diffusion coefficient than the first dopant. For example, the second dopant may be phosphorus (P). The reason is that the second dopant does not diffuse to the portion that becomes the field stop region 11 after the completion of the semiconductor device 100, and the impurity concentration distribution of the field stop region 11 can be prevented from changing. Alternatively, the second dopant may be arsenic (As).

In FIG. 7, a dotted line (rough dotted line than FIG. 4) in the vicinity of the surface of the field stop region 11 represents the implanted second dopant. That is, the second dopant is implanted only into the formation region of the n ⁺ -type region 10 and is not implanted into the formation region of the p ⁺ -type region 9. The dose amount of the second dopant may be, for example, 1 × 10 ¹⁴ / cm ² or more. Next, the resist mask 21 is removed (first removal step).

Next, as shown in FIG. 8, a resist mask (second mask) 22 having an opening for forming the p ⁺ -type region 9 is formed on the back surface of the semiconductor substrate, that is, the surface of the field stop region 11 by photolithography. (Second mask forming step).

  Next, as shown in FIG. 9, using the resist mask 22 as a mask, a p-type third dopant is ion-implanted from the back surface side of the semiconductor substrate into the field stop region 11 (hereinafter referred to as a third implantation step). As a result, the third dopant is implanted only into the surface of the field stop region 11 exposed at the opening of the resist mask 22.

The third dopant used in the third implantation step may be boron (B), for example. In FIG. 9, a dotted line (dotted line smaller than those in FIGS. 4 and 7) in the vicinity of the surface of the field stop region 11 exposed at the opening of the resist mask 22 represents the implanted third dopant. That is, the third dopant is implanted only into the formation region of the p ⁺ -type region 9 and is not implanted into the formation region of the n ⁺ -type region 10. The dose amount of the third dopant may be, for example, 1 × 10 ¹⁴ / cm ² or more. Next, the resist mask 22 is removed (second removal step).

Next, heat treatment (laser annealing) is performed by irradiating the back surface of the semiconductor substrate with laser light to activate the second dopant and the third dopant implanted in the field stop region 11 in the second implantation step and the third implantation step, respectively. (Hereinafter referred to as a second annealing step). The laser annealing treatment condition in the second annealing step may be, for example, a laser irradiation density of ² J / cm ² or less. Thereby, as shown in FIG. 10, n ⁺ type region 10 of diode 120 and p ⁺ type region 9 of IGBT 110 are selectively formed in the surface layer of field stop region 11. The processes from the first mask forming process to the second annealing process correspond to the second forming process.

Next, the third electrode 12 is formed on the surfaces of the p ⁺ type region 9 and the n ⁺ type region 10. Thereby, as shown in FIG. 1, the semiconductor device 100 is completed.

In the manufacturing method of the semiconductor device 100 described above, the second implantation step may be performed after the third implantation step. That is, after the first implantation step for forming the field stop region 11 and the furnace annealing (first annealing step), the second dopant that becomes the n ⁺ type region 10 and the third dopant that becomes the p ⁺ type region 9 are activated. Before performing laser annealing (second annealing step) to be performed, a second implantation step of ion-implanting a second dopant that becomes the n ⁺ -type region 10 and a third dopant that becomes the p ⁺ -type region 9 are ion-implanted. The third injection step may be performed.

The order of the second implantation step of ion-implanting the second dopant to be the n ⁺ -type region 10 and the third implantation step of ion-implanting the third dopant to be the p ⁺ -type region 9 is preferably the n ⁺ -type region 10. In addition, it is preferable to perform the dopant implantation step of forming deeper than the surface of the field stop region 11 in the p ⁺ -type region 9 first. For example, in the first embodiment, assuming that the n ⁺ type region 10 is formed deeper than the p ⁺ type region 9, the third implantation step is performed after the second implantation step. The reason is as follows.

In the first embodiment, the second dopant implanted into the formation region of the n ⁺ -type region 10 (cathode region) in the second implantation step is used as the formation region of the p ⁺ -type region 9 (collector region) in the third implantation step. The third dopant is implanted deeper than the third dopant. For this reason, if the dopant implantation process is performed in the order of the third implantation process and the second implantation process, the p ⁺ -type region is present when there is pattern unevenness in the resist mask 21 used when the second dopant is ion-implanted. In the p-type impurity region of the third dopant formed in the formation region 9, an n-type impurity region due to the second dopant deeper than the p-type impurity region is formed. Thus, p ⁺ n ⁺ -type region extending from the rear surface of the semiconductor substrate to a field stop region 11 in the mold region 9 will be partially formed, it is impossible to form a uniform p ⁺ -type region 9.

In contrast, the second implantation step, if performed in the order of the third implantation step, as the impurity region of the n-type by the second dopant is formed in the formation region of the p ⁺ -type region 9, then, the p ⁺ -type region 9 A p-type impurity region by the third dopant can be uniformly formed on the surface layer of the formation region. In this manner, avoids the n ⁺ -type region to the p ⁺ -type region 9 extending from the rear surface of the semiconductor substrate to a field stop region 11 is partially formed, since the p ⁺ -type region 9 can be formed uniformly is there.

Even if the resist mask 22 used for ion implantation of the third dopant has pattern unevenness, the n-type impurity region formed by the second dopant formed in the formation region of the n ⁺ -type region 10 is This is because the p ⁺ -type region reaching the field stop region 11 from the rear surface of the semiconductor substrate is not partially formed in the n ⁺ -type region 10 because it is formed deeper than the p-type impurity region of 3 dopants. 1 to 10, the difference in thickness between the p ⁺ -type region 9 and the n ⁺ -type region 10 is not shown (the same applies to FIGS. 11 to 13).

The depths of ion implantation of the second dopant and the third dopant in the second implantation process and the third implantation process are controlled by adjusting the acceleration energy at the time of ion implantation. That is, in the n ⁺ -type region 10 and the p ⁺ -type region 9, the acceleration energy at the time of ion implantation of the deeper dopant may be made larger than the acceleration energy at the time of ion implantation of the shallower dopant. . For example, the acceleration energy at the time of ion implantation of the second dopant (phosphorus) may be 100 keV, and the acceleration energy at the time of ion implantation of the third dopant (boron) may be 50 keV.

  As described above, according to the first embodiment, after the first ion implantation of selenium (first dopant) is performed on the back surface of the semiconductor substrate and the selenium is diffused to form the field stop region 11, Phosphorus (second dopant) having a smaller diffusion coefficient than selenium is second ion-implanted. For this reason, the phosphorus implanted with the second ions does not hinder the formation of the field stop region 11. Thereby, it can avoid that the carrier concentration of the field stop area | region 11 falls. Therefore, the breakdown voltage of the RC-IGBT can be improved by 10% or more.

  The field stop region 11 is sufficiently diffused at a depth of 1 μm or more from the back surface of the semiconductor substrate by furnace annealing. Therefore, even if phosphorus and boron (third dopant) are implanted at the back surface of the semiconductor substrate at a dose higher than that of selenium, the phosphorus and boron inhibit the formation of the field stop region 11. Never do. Thereby, it can avoid that the carrier concentration of the field stop area | region 11 falls. Therefore, the breakdown voltage of the RC-IGBT can be improved by 10% or more.

The phosphorus and boron implanted with the second and third ions are diffused by laser annealing. Therefore, the influence of the thermal energy by the laser annealing for forming the n ⁺ type region 10 and the p ⁺ type region 9 on the field stop region 11 is about 1 μm from the back surface of the semiconductor substrate. Thereby, it can be avoided that the impurity concentration distribution of the field stop region 11 is changed by thermal diffusion for forming the n ⁺ -type region 10 and the p ⁺ -type region 9. Therefore, the leakage current can be reduced by 10% or more. Thereby, a yield can be made high.

(Embodiment 2)
11 to 13 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the second embodiment. The second embodiment is different from the first embodiment in that the third implantation step is performed before the second implantation step, and that the third dopant is ion-implanted into the entire back surface of the semiconductor substrate in the third implantation step. In the second embodiment, the case where n ⁺ type region 10 is formed shallower than p ⁺ type region 9 will be described.

  The semiconductor device 100 according to the second embodiment has the same configuration as the semiconductor device according to the first embodiment (see FIG. 1). The semiconductor device 100 according to the second embodiment is manufactured as follows. First, similarly to the first embodiment, the processes up to the formation of the front surface element structure, the field stop region 11, the second electrode 8, and the passivation film (not shown) of the semiconductor device 100 are performed (FIGS. 2 to 2). 5).

Next, as shown in FIG. 11, p-type third dopant (for example, boron) is ion-implanted into the back surface of the semiconductor substrate, that is, the surface of the field stop region 11 (third implantation step). At this time, the third dopant is ion-implanted into the entire back surface of the semiconductor substrate. In FIG. 11, the dotted line near the surface of the field stop region 11 represents the implanted third dopant. That is, the third dopant is implanted into both the p ⁺ -type region 9 formation region and the n ⁺ -type region 10 formation region.

Next, as shown in FIG. 12, a resist mask in which a region where the n ⁺ -type region 10 is formed is opened on the back surface of the semiconductor substrate, that is, the surface where the third dopant in the field stop region 11 is ion-implanted by photolithography. 23 is formed.

  Next, as shown in FIG. 13, n-type second dopant (for example, phosphorus) is ion-implanted into the back surface of the semiconductor substrate using the resist mask 23 as a mask (second implantation step). As a result, the second dopant is implanted only into the surface of the field stop region 11 exposed at the opening of the resist mask 23.

In FIG. 13, a dotted line near the surface of the field stop region 11 exposed at the opening of the resist mask 23 represents the implanted second dopant. That is, the second dopant is implanted only into the formation region of the n ⁺ -type region 10 and is not implanted into the formation region of the p ⁺ -type region 9. At this time, the dose amount of the second dopant is higher than the dose amount of the first dopant and higher than the dose amount of the third dopant.

Also in the second embodiment, the order of the second implantation step and the third implantation step is preferably formed deeper than the surface of the field stop region 11 in the n ⁺ -type region 10 and the p ⁺ -type region 9. One of the dopant implantation steps may be performed first. For example, in the second embodiment, the third dopant (boron) is ion-implanted first at an acceleration energy of 100 keV as the third implantation step. Then, a second dopant (phosphorus) may be ion-implanted at an acceleration energy of 50 keV as a second implantation step (described later) in a step after the third implantation step.

  Next, the resist mask 23 is removed. Next, in the same manner as in the first embodiment, the back surface of the semiconductor substrate is irradiated with laser light to perform heat treatment (laser annealing), and the third implantation injected into the field stop region 11 in the third implantation step and the second implantation step, respectively. The dopant and the second dopant are activated (second annealing step).

As described above, the dose amount of the second dopant is higher than the dose amount of the first dopant and higher than the dose amount of the third dopant. Therefore, even when subjected to a second injection step after the third implantation step, the formation region of the n ⁺ -type region 10, n-type impurity concentration by ion implantation of the second dopant is compensated n ⁺ -type region 10 (Hereinafter referred to as n ⁺ -type region 10 by compensation) is formed. Therefore, as in the first embodiment, n ⁺ type region 10 and p ⁺ type region 9 are formed by the second annealing step (see FIG. 10).

  Next, as in the first embodiment, the following steps are performed to complete the semiconductor device 100 as shown in FIG. Other manufacturing methods and processing conditions of the second embodiment are the same as those of the first embodiment.

  As described above, according to the second embodiment, since the same semiconductor device as that of the first embodiment is manufactured (manufactured), the same effect as that of the first embodiment can be obtained.

Example 1
Next, the carrier concentration distribution in the field stop region 11 of the semiconductor device 100 according to the first embodiment will be described. FIG. 14 is a characteristic diagram illustrating the carrier concentration distribution of the semiconductor device according to the first example. The horizontal axis of FIG. 14 shows the depth from the back surface of the semiconductor substrate. The vertical axis in FIG. 14 indicates the carrier concentration of the n-type impurity. First, RC-IGBT was manufactured according to Embodiment 1. Specifically, selenium was ion-implanted into the back surface of the semiconductor substrate to be the drift region 1 (first implantation step) and furnace annealing (first annealing step) was performed to form the field stop region 11. Thereafter, phosphorus and boron are ion-implanted into the surface of the field stop region 11 (second and third implantation steps), respectively, and laser annealing (second annealing step) is performed, and p ⁺ -type region 9 (collector region) and n ⁺ -type Region 10 (cathode region) was formed.

  For comparison, two types of RC-IGBTs prepared by a manufacturing method different from the RC-IGBT according to Example 1 were prepared (hereinafter referred to as first and second comparative examples). In the first comparative example, phosphorus and boron are respectively ion-implanted after selenium is implanted into the back surface of the semiconductor substrate, and then furnace annealing is performed to collectively collect the selenium, phosphorus and boron ions implanted into the back surface of the semiconductor substrate. The field stop region, the collector region, and the cathode region were formed by activation. Other manufacturing methods, ion implantation conditions, and annealing conditions of the first comparative example are the same as those of the RC-IGBT manufacturing method according to the first example. In the second comparative example, phosphorus is ion-implanted into the back surface of the semiconductor substrate, and furnace annealing is performed to activate phosphorus to form a field stop region. Other manufacturing methods, ion implantation conditions, and annealing conditions are the same as those of the RC-IGBT manufacturing method according to the first example.

In the results shown in FIG. 14, the measurement points 31, 32, and 33 are respectively the field stop region and the n ⁺ -type region (cathode region) of the RC-IGBT according to Example 1, the first comparative example, and the second comparative example. The carrier concentration in the field stop region at the interface is shown. From the results shown in FIG. 14, in the RC-IGBT according to Example 1 and the first comparative example, the carrier concentration in the field stop region is about the same as the measurement points 31 and 32 in the depth direction from the measurement points 31 and 32. It is measured by carrier concentration. That is, it can be seen that in the RC-IGBT and the first comparative example according to Example 1, the field stop region is formed with a thickness from the measurement points 31 and 32 to a depth not shown. On the other hand, in the second comparative example, the carrier concentration in the field stop region is measured only from the measurement point 33 to a depth of about 2.5 μm. That is, in the second comparative example, it can be seen that the field stop region is formed only from the measurement point 33 to a depth of about 2.5 μm.

  Moreover, it turns out that the carrier concentration of the field stop area | region 11 in the measurement point 31 of RC-IGBT concerning Example 1 is higher than the carrier concentration of the field stop area | region in the measurement point 32 of a 1st comparative example. The reason is estimated as follows. In the first comparative example, selenium for forming the field stop region and phosphorus for forming the cathode region are continuously injected, and then the selenium and phosphorus are activated together to form the field stop region and the cathode region. Form at the same time. For this reason, when selenium and phosphorus are activated collectively, phosphorus inhibits diffusion of selenium. On the other hand, in the RC-IGBT according to the first embodiment, first, field annealing is performed by performing furnace annealing (first annealing step) after ion implantation (first implantation step) of selenium into the back surface of the semiconductor substrate. Only the stop region 11 is formed. For this reason, diffusion of selenium is not inhibited by phosphorus implanted into the back surface of the semiconductor substrate in the subsequent second implantation step.

  In the first comparative example, phosphorus for forming the cathode region is activated by furnace annealing. On the other hand, in the RC-IGBT according to the first embodiment, the phosphorus ion-implanted in the second implantation process is activated by laser annealing (second annealing process). Laser annealing can raise the temperature of a semiconductor substrate faster than furnace annealing, and can raise the temperature of the part which irradiated the laser locally and instantaneously. For this reason, in the RC-IGBT according to the first embodiment, the implanted phosphorus hardly diffuses, and the diffusion depth is, for example, about 1 μm from the back surface of the semiconductor substrate. Thereby, in the RC-IGBT according to Example 1, it is estimated that the carrier concentration of the field stop region 11 at the measurement point 31 is higher than that of the first comparative example (measurement point 32).

  From the above results, it was found that the RC-IGBT according to Example 1 can form the field stop region 11 thicker than the second comparative example. Further, in the RC-IGBT according to the first embodiment, diffusion of selenium that is ion-implanted to form the field stop region 11 is not inhibited. For this reason, it was found that the field stop region 11 having a desired carrier concentration and a desired thickness can be formed.

(Example 2)
Next, electrical characteristics of the semiconductor device 100 according to the second embodiment will be described. FIG. 15 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the second example. First, according to the first embodiment, four types of RC-IGBTs were manufactured by changing the widths of the p ⁺ -type region 9 (collector region) and the n ⁺ -type region 10 (cathode region) in various ways (hereinafter referred to as a first type). To the fourth sample). The widths of the p ⁺ type region 9 and the n ⁺ type region 10 of the first sample were 96 μm and 32 μm, respectively. The widths of the p ⁺ type region 9 and the n ⁺ type region 10 of the second sample were 144 μm and 48 μm, respectively. The widths of the p ⁺ type region 9 and the n ⁺ type region 10 of the third sample were 288 μm and 96 μm, respectively. The widths of the p ⁺ type region 9 and the n ⁺ type region 10 of the fourth sample were 432 μm and 144 μm, respectively. Then, in the first to fourth samples, the relationship (IV characteristics) between the collector-emitter voltage Vce and the collector current Ic was examined.

  From the results shown in FIG. 15, it can be seen that in the first and second samples, the snapback 41 having the IV characteristic, which is generated from the transient period until the RC-IGBT shifts from the MOSFET operation to the bipolar operation, is generated. For example, even when the RC-IGBT is manufactured by using the technology for forming the IGBT shown in Patent Documents 3 to 5 described above and the technology for forming the diode alone, as in the first and second samples, the snap It is estimated that a back will occur.

On the other hand, snapback does not occur in the third and fourth samples. Accordingly, it was found that the width of the p ⁺ -type region 9 is preferably 288 μm or more, and the width of the n ⁺ -type region 10 is preferably 96 μm or more. More preferably, the width of the p ⁺ type region 9 is preferably 288 μm, and the width of the n ⁺ type region 10 is preferably 96 μm (third sample). The reason is that the reverse recovery tolerance is reduced in the fourth sample.

  In Examples 1 and 2 described above, the RC-IGBT according to the first embodiment has been described as an example, but it is assumed that the same result is obtained also in the RC-IGBT according to the second embodiment. The reason is that both the first and second embodiments perform the first annealing process (furnace annealing) after the first implantation process, and then perform the second implantation process and the second annealing process (laser annealing). Because.

In the above, the present invention has been described with respect to a method of manufacturing a semiconductor device in which an IGBT and a diode having a trench gate structure are formed on the same semiconductor substrate. However, the present invention is not limited to the above-described embodiment. It can be applied when manufacturing a semiconductor device provided with an IGBT and a diode. That is, the present invention can be applied to manufacturing a semiconductor device having an n ⁺ type region provided on the surface of an n type field stop region. Further, the present invention may be applied to a semiconductor device in which one semiconductor element is provided on a semiconductor substrate when an n ⁺ type region is formed on the surface of the n type region. Further, the present invention may be applied when a semiconductor device having a configuration in which the n type and the p type are reversed and the p ⁺ type region is provided on the surface of the p type field stop region.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for a power semiconductor device used for motor control or engine control for industrial or automobile use, for example.

1 Drift region 2 Base region 3 Contact region 4 Emitter region 5 Trench 6 Electrode (first)
7 Interlayer insulation film 8 Electrode (second)
9 p ⁺ type region 10 n ⁺ type region 11 Field stop region 12 Electrode (third)
100 Semiconductor device 110 IGBT
120 diode

Claims (12)

A method of manufacturing a semiconductor device in which an insulated gate bipolar transistor and a diode are provided on the same first conductivity type semiconductor substrate,
A first forming step of ion-implanting a first conductivity type first dopant on the back surface of the semiconductor substrate and forming a first conductivity type first semiconductor region having an impurity concentration higher than that of the semiconductor substrate by a heat treatment; ,
After the first formation step, a second conductivity type second dopant and a second conductivity type third dopant having a diffusion coefficient smaller than that of the first dopant are ion-implanted into the back surface of the semiconductor substrate, respectively, and heat treatment is performed. A second forming step of forming a second semiconductor region of the first conductivity type and a third semiconductor region of the second conductivity type by:
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the first formation step, after the first dopant is ion-implanted into the entire back surface of the semiconductor substrate, heat treatment is performed using a heat treatment furnace.   In the second forming step, the second dopant is selectively ion-implanted into the back surface of the semiconductor substrate, and then the third dopant is implanted into a region different from the region where the second dopant is ion-implanted on the back surface of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 1, wherein ion implantation is performed, and thereafter heat treatment is performed using a laser.   In the second forming step, the third dopant is ion-implanted into the entire back surface of the semiconductor substrate, and then the second dopant is selectively ion-implanted into the back surface of the semiconductor substrate, and then heat treatment is performed using a laser. The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed.   5. The method of manufacturing a semiconductor device according to claim 1, wherein, in the second formation step, the second semiconductor region constituting the diode is formed. 6.   4. The method of manufacturing a semiconductor device according to claim 1, wherein in the second formation step, the third semiconductor region constituting the insulated gate bipolar transistor is formed. 5.   The method for manufacturing a semiconductor device according to claim 1, wherein a grinding step of grinding a back surface of the semiconductor substrate is performed before the first forming step.   The method for manufacturing a semiconductor device according to claim 1, wherein the first dopant is selenium.   The method for manufacturing a semiconductor device according to claim 1, wherein the second dopant is phosphorus.   The method for manufacturing a semiconductor device according to claim 1, wherein the third dopant is boron. A method of manufacturing a semiconductor device in which an insulated gate bipolar transistor and a diode are provided on the same first conductivity type semiconductor substrate,
A first implantation step of ion-implanting a first dopant of a first conductivity type into the back surface of the semiconductor substrate;
A first annealing step for performing furnace annealing after the first implantation step;
A first mask forming step of covering the back surface of the semiconductor substrate with a first mask in which a formation region of the first conductive type second semiconductor region of the diode is opened after the first annealing step;
Using the first mask as a mask, a second implantation step of ion-implanting a second dopant of the first conductivity type into the back surface of the semiconductor substrate;
A first removal step of removing the first mask;
A second mask forming step of covering the back surface of the semiconductor substrate with a second mask in which the formation region of the second conductive type third semiconductor region of the insulated gate bipolar transistor is opened after the first removing step;
A third implantation step of ion-implanting a second dopant of a second conductivity type into the back surface of the semiconductor substrate using the second mask as a mask;
A second removal step of removing the second mask;
A second annealing step of performing laser annealing on the back surface of the semiconductor substrate after the second removing step;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device in which an insulated gate bipolar transistor and a diode are provided on the same first conductivity type semiconductor substrate,
A first implantation step of ion-implanting a first dopant of a first conductivity type into the back surface of the semiconductor substrate;
A first annealing step for performing furnace annealing after the first implantation step;
A third implantation step of ion-implanting a second dopant of a second conductivity type into the back surface of the semiconductor substrate after the first annealing step;
A first mask forming step of covering a back surface of the semiconductor substrate with a first mask in which a formation region of the first conductive type second semiconductor region of the diode is opened after the third implantation step;
A second implantation step of ion-implanting a first dopant of a first conductivity type using the first mask as a mask;
A first removal step of removing the first mask;
A second annealing step of performing laser annealing on the back surface of the semiconductor substrate after the first removing step;
A method for manufacturing a semiconductor device, comprising:

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