CN113053746A - Preparation method of low-voltage IGBT device - Google Patents
Preparation method of low-voltage IGBT device Download PDFInfo
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- CN113053746A CN113053746A CN201911374549.6A CN201911374549A CN113053746A CN 113053746 A CN113053746 A CN 113053746A CN 201911374549 A CN201911374549 A CN 201911374549A CN 113053746 A CN113053746 A CN 113053746A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 55
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 14
- 238000002513 implantation Methods 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 10
- 238000005224 laser annealing Methods 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 claims description 2
- 239000012634 fragment Substances 0.000 abstract description 10
- 238000002347 injection Methods 0.000 abstract description 9
- 239000007924 injection Substances 0.000 abstract description 9
- 235000012431 wafers Nutrition 0.000 description 48
- 239000000758 substrate Substances 0.000 description 12
- 238000005530 etching Methods 0.000 description 11
- 239000012535 impurity Substances 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/263—Bombardment with radiation with high-energy radiation
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention discloses a preparation method of a low-voltage IGBT device, which comprises the following steps: s1, completing an IGBT front structure on the front side of a wafer; s2, thinning the back of the wafer obtained in the step S1 to a first thickness; s3, forming a buffer layer on the back of the wafer obtained in the step S2; s4, thinning the back of the wafer obtained in the step S3 to a final thickness; and S5, forming an anode layer on the back surface of the wafer obtained in the step S4, and depositing metal on the anode layer to form a collector. The high-temperature process is carried out under the condition of thicker sheet thickness, so that the risk of fragments caused by excessive warping can be avoided, and the fragment rate is reduced; and proton injection is carried out from the back side, so that damage to the front structure of the IGBT can be avoided, and the product quality is improved.
Description
Technical Field
The invention relates to a preparation method of a low-voltage IGBT device, and belongs to the technical field of semiconductor manufacturing.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a device formed by combining a MOSFET and a Bipolar Transistor, and has an input electrode which is a MOSFET and an output electrode which is a PNP Transistor. Therefore, the IGBT can be considered as a darlington transistor with MOS input. The IGBT not only has the advantages of voltage driving of the MOSFET device, high voltage resistance, simple driving and high switching speed, but also has the advantages of strong current capability and low conduction voltage drop of the bipolar device, thereby being widely applied to modern power electronic technology.
The preparation of the IGBT comprises the formation of a substrate, a front surface process and a back surface process. In the IGBT preparation process, PN junctions, gate electrodes and emitter patterns on the front side are formed through a front side process, then grinding and etching are carried out on the back side, and a back buffer layer, an anode layer and a collector are formed. The thickness of the Si substrate after final thinning varies according to the structure of the device and the voltage class applied.
After the back surface of the conventional low-voltage IGBT is thinned, protons are activated through back surface proton implantation and furnace tube annealing, and a buffer layer/field stop layer/soft punch-through layer structure of the IGBT is formed. The thickness of the 750V IGBT is 60-90 μm usually because the low-voltage IGBT is thick and thin. Such thin sheet thicknesses are highly susceptible to warping during high temperatures and greatly increase the risk of chipping in subsequent process steps.
Before thinning, a buffer layer/a field stop layer/a soft punch-through layer can be formed from the front surface through high-energy proton injection and thermal processes, so that the thin sheet can be prevented from being subjected to excessive thermal processes, and the fragment rate is reduced. However, the front side injection may cause injection damage to the IGBT front side structure, and there is not enough thermal budget to repair the damage.
Disclosure of Invention
The invention aims to provide a preparation method of a low-voltage IGBT device, which is used for thinning a wafer to a set sheet thickness for the first time after the front process of the IGBT is finished. And then carrying out back high-energy proton implantation and furnace tube annealing to form a back buffer layer/a field stop layer/a soft through layer. And then carrying out secondary back thinning until the final thickness is reached. And then completing the low thermal budget anode process, metal deposition and other processes. The high-temperature process is carried out under the condition of thicker sheet thickness, so that the risk of fragments caused by excessive warping can be avoided, and the fragment rate is reduced; and proton injection is carried out from the back side, so that damage to the front structure of the IGBT can be avoided, and the product quality is improved.
According to one aspect of the invention, a preparation method of a low-voltage IGBT device is provided, which comprises the following steps:
s1, completing an IGBT front structure on the front side of a wafer;
s2, thinning the back of the wafer obtained in the step S1 to a first thickness;
s3, forming a buffer layer on the back of the wafer obtained in the step S2;
s4, thinning the back of the wafer obtained in the step S3 to a final thickness;
and S5, forming an anode layer on the back surface of the wafer obtained in the step S4, and depositing metal on the anode layer to form a collector.
According to a preferred embodiment of the present invention, the wafer may be any kind of wafer, such as an N or P type wafer.
According to a preferred embodiment of the present invention, the step S1 includes: a series of process IGBT processes are performed on the front side of the silicon wafer, typically including: forming an N well and a P well, etching a groove, forming gate oxide, depositing polycrystalline silicon and etching back to form a grid electrode, injecting an N + source region, depositing a dielectric layer, etching an emitter contact hole, and depositing metal to form an emitter.
According to an embodiment of the present invention, the step S1 includes the following steps:
forming a first oxide layer on the upper surface of the wafer substrate;
injecting N-type impurities into the wafer substrate, and diffusing the N-type impurities into a first junction depth to form an N well;
injecting P-type impurities into the N well, and diffusing the P-type impurities to a second junction depth to form a P well;
forming an active groove and a gate groove on a wafer substrate;
removing the rest first oxidation layer, and forming a second oxidation layer on the upper surface of the P well, the inner surfaces of the active groove and the virtual gate groove;
filling polycrystalline silicon in the active trench and the virtual gate trench to form a trench gate and a trench gate;
etching the polycrystalline silicon in the active groove and the gate accompanying groove, so that the highest point of the polycrystalline silicon in the active groove and the gate accompanying groove is lower than the preset height difference of the upper surface of the wafer substrate;
injecting N-type impurities into a first preset position on the upper surface of the P trap between the trench gates to form an N + region with a third junction depth, wherein the N + region is in contact with the trench gates;
forming insulating medium layers on the upper surface of the wafer substrate and the groove grid and the groove auxiliary grid;
etching the insulating medium layer at a second preset position above the N + region between the trench gates to form an emitter contact window; and depositing metal on the surface of the wafer to form an emitter.
According to a preferred embodiment of the present invention, the wafer has a diameter of 6 to 12 inches; the first thickness is the sum of the final thickness of the IGBT device + the implantation depth of the energetic protons-the anode depth.
According to a preferred embodiment of the present invention, the step S3 includes:
and performing high-energy proton implantation and furnace tube annealing treatment on the back of the wafer obtained in the step S2 to form a back buffer layer.
According to a preferred embodiment of the invention, the high-energy protons comprise high-energy H protons.
According to a preferred embodiment of the invention, the implantation depth of the energetic protons is determined by the IGBT voltage class. Generally, the depth is 45-75 μm for 750V, 80-120 μm for 1200V, and 190 μm for 130-1700V.
According to a preferred embodiment of the present invention, the process conditions of the annealing treatment include: the temperature is 350 ℃ and 450 ℃, the time is 10min-10h, for example, the treatment is carried out for 1h at 400 ℃.
Because the thickness after the first thinning is thicker than that of the final wafer, the influence of furnace tube annealing on the wafer warping is limited, and the warping of the wafer can be improved.
According to a preferred embodiment of the present invention, step S5 includes:
5A, performing a low thermal budget anode process on the back surface of the wafer obtained in the step S4 to form an anode layer;
depositing metal on the anode layer to form a collector.
According to a preferred embodiment of the present invention, the step 5A includes:
the anode layer is formed by performing anode implantation and laser annealing on the back surface of the wafer obtained in step S4.
According to a preferred embodiment of the invention, the thinning process comprises a conventional thinning process and/or a Taiko thinning process.
According to a preferred embodiment of the invention, said conventional thinning process refers to a full face thinning without taiko rings.
According to another aspect of the invention, a low-voltage IGBT device prepared according to the method is provided.
According to the preferred embodiment of the invention, the low-voltage IGBT device is in a trench gate structure and/or a planar gate structure.
According to the preferred embodiment of the invention, the voltage grade of the low-voltage IGBT device is less than 3300V, and the thickness is less than 375 μm.
According to another aspect of the invention, the application of the low-voltage IGBT device in the fields of automobiles, wind power, photovoltaics, industrial transmission or household appliances and the like is provided.
The invention has the following advantages and beneficial effects:
1. the thermal budget of the process performed after the wafer is thinned to the final thickness is very low, the stress and warpage of the IGBT can be effectively controlled, the fragment rate is reduced, and particularly the fragment rate of large-size wafers such as 8-12 inches can be reduced.
2. The high-energy proton injection from the back can avoid damaging the front structure of the IGBT, thereby improving the product quality.
3. The process is simple and convenient to implement.
4. The method can save the process time, improve the production efficiency and have strong practicability by combining the front metal contact alloy process and the proton injection activation process and canceling the back metal contact alloy process.
Drawings
FIG. 1 is a process flow diagram for conventional low voltage IGBT fabrication in the prior art;
FIG. 2 is a process flow diagram of a prior art low voltage IGBT fabrication based on front side high energy proton implantation;
FIG. 3 is a process flow diagram of a method according to an embodiment of the invention;
fig. 4-9 are schematic flow charts of a method for manufacturing a low-voltage trench gate IGBT according to an embodiment of the invention.
Detailed Description
The invention is further described with reference to the following figures and specific examples.
In view of the problem that warpage and fragments are easily generated when a low-voltage IGBT device with a thin sheet thickness is prepared in the prior art, the invention provides a preparation method of the low-voltage IGBT device. And then carrying out back high-energy proton implantation and furnace tube annealing to form a back buffer layer/a field stop layer/a soft through layer. And then carrying out secondary back thinning until the final thickness is reached. And then completing the low thermal budget anode process, metal deposition and other processes. The high-temperature process is carried out under the condition of thicker sheet thickness, so that the risk of fragments caused by excessive warping can be avoided, and the fragment rate is reduced; and proton injection is carried out from the back side, so that damage to the front structure of the IGBT can be avoided, and the product quality is improved.
The invention provides a preparation method of a low-voltage IGBT device, which comprises the following steps:
s1, completing an IGBT front structure on the front side of a wafer;
s2, thinning the back of the wafer obtained in the step S1 to a first thickness;
s3, forming a buffer layer on the back of the wafer obtained in the step S2;
s4, thinning the back of the wafer obtained in the step S3 to a final thickness;
and S5, forming an anode layer on the back surface of the wafer obtained in the step S4, and depositing metal on the anode layer to form a collector.
Wherein the step S1 includes: a series of process IGBT processes are performed on the front side of the silicon carbide wafer, typically including: forming an N well and a P well, etching a groove, forming gate oxide, depositing polycrystalline silicon and etching back to form a grid electrode, injecting an N + source region, depositing a dielectric layer, etching an emitter contact hole, and depositing metal to form an emitter.
The method specifically comprises the following steps:
forming a first oxide layer on the upper surface of the wafer substrate;
injecting N-type impurities into the wafer substrate, and diffusing the N-type impurities into a first junction depth to form an N well;
injecting P-type impurities into the N well, and diffusing the P-type impurities to a second junction depth to form a P well;
forming an active groove and a gate groove on a wafer substrate;
removing the rest first oxidation layer, and forming a second oxidation layer on the upper surface of the P well, the inner surfaces of the active groove and the virtual gate groove;
filling polycrystalline silicon in the active trench and the virtual gate trench to form a trench gate and a trench gate;
etching the polycrystalline silicon in the active groove and the gate accompanying groove, so that the highest point of the polycrystalline silicon in the active groove and the gate accompanying groove is lower than the preset height difference of the upper surface of the wafer substrate;
injecting N-type impurities into a first preset position on the upper surface of the P trap between the trench gates to form an N + region with a third junction depth, wherein the N + region is in contact with the trench gates;
forming insulating medium layers on the upper surface of the wafer substrate and the groove grid and the groove auxiliary grid;
etching the insulating medium layer at a second preset position above the N + region between the trench gates to form an emitter contact window;
and depositing metal on the surface of the wafer to form an emitter.
Wherein the first thickness is the sum of the final thickness of the IGBT device + the implantation depth of the energetic protons-the anode depth.
Wherein the step S3 includes:
and performing high-energy proton implantation and furnace tube annealing treatment on the back of the wafer obtained in the step S2 to form a back buffer layer.
Wherein the energetic protons include energetic H protons.
The injection depth of the high-energy protons is determined by the IGBT voltage class. Generally, the depth is 45-75 μm for 750V, 80-120 μm for 1200V, and 190 μm for 130-1700V.
Wherein the process conditions of the annealing treatment comprise: the temperature is 350 ℃ and 450 ℃, the time is 10min-10h, for example, the treatment is carried out for 1h at 400 ℃.
Wherein, step S5 includes:
5A, performing a low thermal budget anode process on the back surface of the wafer obtained in the step S4 to form an anode layer;
depositing metal on the anode layer to form a collector.
Wherein, the step 5A comprises the following steps:
the anode layer is formed by performing anode implantation and laser annealing on the back surface of the wafer obtained in step S4.
Wherein the thinning process comprises a conventional thinning process and/or a Taiko thinning process.
Example 1
Fig. 4 to 9 are schematic flow charts of the preparation method of the low-voltage trench gate IGBT according to the present embodiment.
As shown in FIG. 4, at N-And completing an IGBT front structure on the front surface of the wafer, wherein the diameter of the wafer is 8 inches, and the thickness of the wafer is 725 mu m.
As shown in fig. 5, the wafer with the completed IGBT front surface structure is thinned for the first time (conventional thinning process) to a first thickness of 320 μm.
As shown in FIG. 6, high-energy H proton implantation and furnace annealing (at 400 deg.C for 1H) are performed from the back side of the wafer to a depth of 200 μm to form N-A buffer layer.
As shown in fig. 7, the wafer is thinned for the second time to a final thickness of 70 μm.
As shown in fig. 8, P + implantation and laser annealing are performed on the back side of the wafer to form an anode layer;
as shown in fig. 9, metal Al/Ti/Ni/Ag is deposited on the back side of the wafer to form a back side collector.
Any numerical value mentioned in this specification, if there is only a two unit interval between any lowest value and any highest value, includes all values from the lowest value to the highest value incremented by one unit at a time. For example, if it is stated that the amount of a component, or a value of a process variable such as temperature, pressure, time, etc., is 50 to 90, it is meant in this specification that values of 51 to 89, 52 to 88 … …, and 69 to 71, and 70 to 71, etc., are specifically enumerated. For non-integer values, units of 0.1, 0.01, 0.001, or 0.0001 may be considered as appropriate. These are only some specifically named examples. In a similar manner, all possible combinations of numerical values between the lowest value and the highest value enumerated are to be considered to be disclosed in this application.
It should be noted that the above-mentioned embodiments are only for explaining the present invention, and do not constitute any limitation to the present invention. The present invention has been described with reference to exemplary embodiments, but the words which have been used herein are words of description and illustration, rather than words of limitation. The invention can be modified, as prescribed, within the scope of the claims and without departing from the scope and spirit of the invention. Although the invention has been described herein with reference to particular means, materials and embodiments, the invention is not intended to be limited to the particulars disclosed herein, but rather extends to all other methods and applications having the same functionality.
Claims (10)
1. A preparation method of a low-voltage IGBT device comprises the following steps:
s1, completing an IGBT front structure on the front side of a wafer;
s2, thinning the back of the wafer obtained in the step S1 to a first thickness;
s3, injecting high-energy protons into the back of the wafer obtained in the step S2 to form a buffer layer;
s4, thinning the back of the wafer obtained in the step S3 to a final thickness;
and S5, forming an anode layer on the back surface of the wafer obtained in the step S4, and depositing metal on the anode layer to form a collector.
2. The method of claim 1, wherein the wafer diameter is 6 inches to 12 inches, and the first thickness is a sum of a final thickness of the IGBT device + an implantation depth of the energetic protons — an anode depth.
3. The method according to claim 1 or 2, wherein the step S3 includes:
and performing high-energy proton implantation and furnace tube annealing treatment on the back of the wafer obtained in the step S2 to form a back buffer layer.
4. The method according to any one of claims 1-3, wherein step S5 includes:
5A, performing a low thermal budget anode process on the back surface of the wafer obtained in the step S4 to form an anode layer;
depositing metal on the anode layer to form a collector.
5. The method according to any one of claims 1-4, wherein step 5A comprises:
the anode layer is formed by performing anode implantation and laser annealing on the back surface of the wafer obtained in step S4.
6. Method according to any one of claims 1 to 5, characterized in that the thinning process comprises a conventional thinning process and/or a Taiko thinning process.
7. A low voltage IGBT device prepared according to the method of any one of claims 1 to 6.
8. The device of claim 7, wherein the low voltage IGBT device is a trench gate structure and/or a planar gate structure.
9. The device of claim 7 or 8, wherein the low voltage IGBT device has a voltage rating of less than 3300V and a thickness of less than 375 μm.
10. Use of a low voltage IGBT device according to any of claims 7-9 in the automotive, wind power, photovoltaic, industrial transmission or household appliance field.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007158320A (en) * | 2005-11-10 | 2007-06-21 | Fuji Electric Device Technology Co Ltd | Semiconductor device and method of manufacturing the same |
| US20090224284A1 (en) * | 2008-02-08 | 2009-09-10 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device and method of producing the same |
| CN107431087A (en) * | 2015-03-13 | 2017-12-01 | 三菱电机株式会社 | Semiconductor device and its manufacture method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007158320A (en) * | 2005-11-10 | 2007-06-21 | Fuji Electric Device Technology Co Ltd | Semiconductor device and method of manufacturing the same |
| US20090224284A1 (en) * | 2008-02-08 | 2009-09-10 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device and method of producing the same |
| CN107431087A (en) * | 2015-03-13 | 2017-12-01 | 三菱电机株式会社 | Semiconductor device and its manufacture method |
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