CN103489775A - Novel field cut-off type insulated gate bipolar transistor manufacturing method - Google Patents
Novel field cut-off type insulated gate bipolar transistor manufacturing method Download PDFInfo
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- 230000007797 corrosion Effects 0.000 claims description 6
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- 229920005591 polysilicon Polymers 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
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- 239000011248 coating agent Substances 0.000 description 5
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- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
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- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 206010019133 Hangover Diseases 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
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Abstract
The invention belongs to the semiconductor process technology, and particularly relates to a novel field cut-off type insulated gate bipolar transistor manufacturing method. A basic metal oxide semiconductor field effect transistor structure is formed on the obverse side of a Si single wafer, wherein the metal oxide semiconductor field effect transistor structure comprises a grid electrode composed of polycrystalline silicon and silicon oxide, a p base region, an n+ emitter region and a front metal electrode above the grid electrode and the emitter region; the Si single wafer is an n-type single-crystal Si slice. The novel field cut-off type insulated gate bipolar transistor manufacturing method solves the problem that conventional materials and traditional technologies cannot be used for forming an FS layer in an IGBT easily, realizes technological compatibility between an FS-IGBT and a conventional IGBT, and combines innovative means such as material selection, technology adjustment and combination and compatibility of equipment.
Description
Technical field
The invention belongs to power electronic device insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT) new technique and manufacture of semiconductor technique, relate in particular to a kind of manufacture method of New Type Field cut-off type insulated gate bipolar transistor.
Background technology
The IGBT(insulated gate bipolar transistor) by the BJT(bipolar junction transistor) and the MOSFET(insulated-gate type field effect transistor) the compound full-control type voltage driven type power electronic device that forms, both had that MOSFET input impedance is high, operating rate is fast, speed-sensitive switch and the simple characteristic of drive circuit, have advantages of that again low, the withstand voltage height of BJT on-state voltage drop and current handling capability are strong, therefore be the desirable switching device of field of power electronics, range of application is very extensive.IGBT develops into now, technically experienced important several times update.The mainstream technology of IGBT is the trench gate(trench gate that is called as the 5th generation technique at present)+cut-off of FS(field) technology.Wherein, the FS technology is one of the core technology in the 5th generation and the 6th generation, and the FS-IGBT device is the main flow of high-power IGBT.The effect of FS layer mainly contains 3 points: the first, and the cut-off positive field, compare with the structure that there is no the FS layer, and same thickness can bear larger pressure drop; The second, reduce the thickness of drift region, realize sheet, reduce conduction loss; The 3rd, reduce the memory space that injects few sub-hole, reduce turn-off time and loss.So the FS technology is for the device performance that promotes IGBT and reduce the wastage very important.
To take N-shaped Si substrate be main IGBT for common, and the key that realizes the FS technology is to form one deck n+ resilient coating between P+ collector region and n-drift region overleaf, the device internal electric field is distributed and be trapezoidal, optimizes the Static and dynamic loss.For form the N-shaped zone in the Si wafer, traditional semiconductor technology generally adopts the donor element of Si material to be adulterated, as P(phosphorus) element etc.But due to the FS layer not at chip surface, its degree of depth at least need to be from the effect of the above competence exertion cut-off of the surperficial 4 μ m of back of the body electric field, and the conventional diffusion coefficient of donor element in Si is lower, therefore, by the difficult FS layer that forms of conventional donor element doping, this is one of maximum difficult point realized the FS technology.
In addition, the FS technology relates generally to back process, and if conventional IGBT process compatible, preferably do not destroy original technological process order, complete all positive technique, comprise that the front metal electrode fabrication carries out back process after completing again best.In this case, if adopt conventional donor element doping to form the FS layer, owing to conventional Elements Diffusion need to being arrived to certain degree of depth, push away trap with regard to needing higher temperature (higher than 600 ℃) to anneal after Implantation, and in the situation that the positive technique of device completed, the metal electrode of positive deposition, more than 450 ℃, just likely with Si, reacting or spread in the Si matrix, has a strong impact on the performance of device.For avoiding this phenomenon to occur, the techniques such as pushing away after trap technique the evaporation of carrying out again the front metal electrode and photoetching of just need to annealing overleaf, and now the Si sheet has carried out thinning back side, thin slice is very easily chipping in the technical processs such as photoetching, so need to introduce the interim bonding technology of thin slice, this has increased again the complexity of technique.Therefore, if select a kind of element, activate and just can form the FS layer of distance back of the body case depth more than 4 μ m in the annealing below 450 ℃, not only can with conventional IGBT process compatible, complete all positive technique before technique overleaf, can also save the thin slice bonding technology, for realization and the volume production of FS-IGBT provides great exploitativeness.
Existing number of patent application is CN201210439400.3, open day is 2013.4.10, name is called the patent of invention of " a cut-off type igbt and manufacture method thereof ", its technical scheme is: the invention discloses a kind of cut-off type igbt, comprise mos field effect transistor, N-type light dope base, N+ type resilient coating, back side P type doped region, also comprise an additional N-type light doping section; The following of mos field effect transistor is N-type light dope base, and the following of N-type light dope base is N+ type resilient coating, and additional N-type light doping section, between N+ type resilient coating and back side P type doped region; The N-type doping content of N-type light dope base is less than the N-type doping content that the N-type doping content of adding the N-type light doping section is less than N+ type resilient coating.
Above-mentioned patent has been listed basic structure and the basic manufacturing process of a cutoff layer IGBT, but do not introduce the formation of cutoff layer FS, because not on the surface of device, need the certain degree of depth of diffusion, thus donor element commonly used (as P, As, Sb) because diffusion coefficient in Si is less, be difficult to the degree of depth that diffusion is enough, the cut-off that plays a part to show up, this Focal point and difficult point that also FS realizes just.Above-mentioned patent does not provide concrete solution at this point, even to using yet not specified (NS) of which kind of material doped formation FS layer.
Summary of the invention
For overcome existing manufacture method exist with conventional material be difficult to form in IGBT the FS layer and with the processing compatibility problem of FS-IGBT and conventional IGBT, the manufacture method of a kind of New Type Field cut-off type insulated gate bipolar transistor of special proposition now.
For realizing above-mentioned technique effect, technical scheme of the present invention is as follows:
A kind of manufacture method of New Type Field cut-off type insulated gate bipolar transistor, it is characterized in that: step 1: at the basic MOSFET structure of the positive formation of Si single-chip, described MOSFET structure comprises the front metal electrode of the grid, p base, n+ emitter region and the grid that are comprised of polysilicon and silica and top, emitter region, the single crystalline Si sheet that described Si single-chip is N-shaped, n-drift region one side of described Si single-chip is defined as the front of Si single-chip, and its relative one side is defined as the back side;
N-drift region in described step 1 is substrate, in device architecture as drift region, the alloy that described metal electrode is Al or Al.
Step 2: attenuate is carried out at the back side to the Si single-chip, and the method by mechanical means or chemical corrosion is thinned to 80 μ m to 150 μ m by the Si single-chip, then the Si single-chip is cleaned.
Concrete use SC-3 solution in described step 2 is cleaned the Si single-chip.
Step 3: the back side of carrying out proton by the energetic ion implanter is injected, and by proton Implantation Energy and dosage, at chip back surface, injects one deck ion, and described source ion implantation is H in this example
+, described Implantation Energy is 200KeV to 10MeV, described implantation dosage is 1E10 to 1E15, Si wafer after by diffusion furnace or light irradiation method, the back side being injected is at 200 ℃ to 450 ℃ temperature, annealing 5min to 12h, complete the activation of back side Proton Implantation and push away trap, forms the FS layer of n+.
Step 4: by the technique of Implantation, take conventional recipient element as the injection source, inject one deck ion at the Si single-chip back side;
Described conventional recipient element is boron element, and the energy of Implantation is 10KeV to 500KeV, and the dosage of Implantation is 1E12 to 1E15, injects one deck B ion at the Si single-chip back side.
Step 5: the Si wafer after conventional recipient element is injected is the 5min to 24h that annealed under 200 ℃ to 900 ℃ in temperature, completes to the back side is injected the activation of ion and pushed away trap, forms the p+ layer.
Step 6: by the method for sputter or evaporated metal, make Si chip back surface electrode, the metal material of backplate is Al-V-Ni-Ag or Al-Ti-Ni-Ag, now obtains complete FS-IGBT device.
The invention has the beneficial effects as follows:
1, the invention solves the processing compatibility problem that conventional material and traditional handicraft are difficult to form FS layer and FS-IGBT and conventional IGBT in IGBT.Combine the adjustment of selection, technique of material and equipment in conjunction with the innovative means such as compatibility.
2, compare utilize conventional donor element as the source material of Implantation to form the FS layer process of n+, there is following advantage: after completing the Implantation at the back side, the ion injected all is distributed in the back of the body near surface position of Si wafer mostly, need to carry out the annealing of uniform temperature and certain hour, ion is spread to complete activation and to push away trap in the Si wafer, form the FS layer of certain depth.If adopt conventional donor element as the injection source, because the diffusion coefficient of P element in Si is lower, the degree of depth that the P ion on Si surface will be diffused to more than 6 μ m forms the n+ layer, annealing temperature need to be more than 1200 ℃, annealing time need to be over 24 hours, the equipment such as the Implantation of these process conditions utilization routines and diffusion furnace are difficult to reach, even can reach, make the wafer that completes positive technique for a long time in hot environment, for performance or the equipment of device, all adverse influence can be arranged.The present invention selects H
+proton injects, utilize energetic ion implanter and diffusion furnace, after injection completes, the activation of only need to annealing within lower temperature and shorter time, just can form the above FS layer of distance back of the body case depth 4 μ m, can effectively solve the above-mentioned series of problems produced as source material with conventional donor element.
3. utilize proton to inject, by energetic ion, inject and low-temp activation, do not need high-temperature annealing activation can form the FS layer, complete overleaf all positive technique before technique, can avoid needing the thin slice bonding technology of introducing after conventional donor element doping, technological process and conventional IGBT device fabrication processes are fully compatible, are a kind of practicable manufacture methods, and can effectively control cost.
4. the FS layer carrier concentration profile of utilizing the proton high energy ion implantation to form more is conducive to realize an effect of cut-off.Utilize conventional donor element doping to form the FS layer, after Implantation, donor element is mainly concentrated and is distributed in back of the body surface, after annealing activates, element is to Si matrix diffusion inside, so the FS layer carrier concentration formed is the highest on Si sheet back of the body surface, along with the increase of the degree of depth, FS layer carrier concentration reduces (as Fig. 2) gradually; And utilize after proton carries out high energy ion implantation to Si sheet back of the body surface, high-energy will be directly injected into proton the zone of carrying on the back surperficial certain distance apart from the Si sheet, so the carrier concentration of FS layer reaches maximum (as Fig. 3) in FS inside, so just can more effectively stop the depletion region diffusion of drift region, can more effectively end the front electric field.
5. utilize proton to inject, inject and low-temp activation by energetic ion, form the above FS layer of distance back of the body case depth 4 μ m, compare the IGBT device without the FS layer, can reduce significantly thickness of detector in the situation that device electric breakdown strength is identical, thereby reduce the conduction loss of device.
6. utilize proton to inject, by energetic ion, inject and low-temp activation, form the above FS layer of distance back of the body case depth 4 μ m, compare the IGBT device without the FS layer, can reduce the memory space of the few son injected from collector region, reduce turn-off time and the hangover electric current of device, thereby reduce the turn-off power loss of device.
The accompanying drawing explanation
Fig. 1-Fig. 4 is the technical process figure of the inventive method.Because the positive technique of device is identical with conventional plane IGBT, so save detailed front processing step in flow chart.
Fig. 5 is that conventional donor element injects the carrier concentration profile schematic diagram that forms the FS layer.
Fig. 6 is that proton of the present invention injects the carrier concentration profile schematic diagram that forms the FS layer.
Embodiment
The present invention will address the above problem adopted new technical scheme and be achieved in that the mentality of designing of this invention is: adulterate and obtain the n+ zone in the back of the body surface that utilizes proton to be infused in the Si wafer, and under the condition of lower temperature, annealing activates and forms the FS layer; Main processes of the present invention comprises: complete after the positive technique (comprising the formation of grid electrode front, emitter and metal electrode) of basic device and thinning back side the Si wafer cleaning; Utilize high energy (200KeV to 10MeV) ion implantor the proton of suitable dosage to be injected into to the back of the body surface of Si wafer; Process annealing activates the FS layer that forms n+; By the injection of recipient element (as boron) and the P+ collector electrode at the activation formation back side; Deposit backplate, complete the technical process of FS-IGBT device.
Embodiment 1
A kind of manufacture method of New Type Field cut-off type insulated gate bipolar transistor, it is characterized in that: step 1: at the basic MOSFET structure of the positive formation of Si single-chip, described MOSFET structure comprises the front metal electrode of the grid, p base, n+ emitter region and the grid that are comprised of polysilicon and silica and top, emitter region, the single crystalline Si sheet that described Si single-chip is N-shaped, n-drift region one side of described Si single-chip is defined as the front of Si single-chip, and its relative one side is defined as the back side;
N-drift region in described step 1 is substrate, in device architecture as drift region, the alloy that described metal electrode is Al or Al.
Step 2: to the back side of Si single-chip, carry out attenuate, the method by mechanical means or chemical corrosion is thinned to 100 μ m by the Si single-chip, then the Si single-chip is cleaned.
Concrete use SC-3 solution in described step 2 is cleaned the Si single-chip.
Step 3: the back side of carrying out proton by the energetic ion implanter is injected, and by proton Implantation Energy and dosage, at chip back surface, injects one deck ion, and described source ion implantation is H in this example
+, described Implantation Energy is 5MeV, and described implantation dosage is 1E13, and the Si wafer after by diffusion furnace, the back side being injected is at 200 ℃ to 450 ℃ temperature, and annealing 30min, complete the activation of back side Proton Implantation and push away trap, forms the FS layer of n+.
Step 4: by the technique of Implantation, take conventional recipient element as the injection source, inject one deck ion at the Si single-chip back side;
Described conventional recipient element is boron element, and the energy of Implantation is 10KeV to 500KeV, and the dosage of Implantation is 1E13, injects one deck B ion at the Si single-chip back side.
Step 5: the Si wafer after conventional recipient element is injected is the 12h that annealed under 500 ℃ in temperature, completes to the back side is injected the activation of ion and pushed away trap, forms the p+ layer.
Step 6: by the method for sputter or evaporated metal, make Si chip back surface electrode, the metal material of backplate is Al-V-Ni-Ag or Al-Ti-Ni-Ag, now obtains complete FS-IGBT device.
Embodiment 2
A kind of manufacture method of New Type Field cut-off type insulated gate bipolar transistor, it is characterized in that: step 1: at the basic MOSFET structure of the positive formation of Si single-chip, described MOSFET structure comprises the front metal electrode of the grid, p base, n+ emitter region and the grid that are comprised of polysilicon and silica and top, emitter region, the single crystalline Si sheet that described Si single-chip is N-shaped, n-drift region one side of described Si single-chip is defined as the front of Si single-chip, and its relative one side is defined as the back side;
N-drift region in described step 1 is substrate, in device architecture as drift region, the alloy that described metal electrode is Al or Al.
Step 2: to the back side of Si single-chip, carry out attenuate, the method by mechanical means or chemical corrosion is thinned to 150 μ m by the Si single-chip, then the Si single-chip is cleaned.
Concrete use SC-3 solution in described step 2 is cleaned the Si single-chip.
Step 3: the back side of carrying out proton by the energetic ion implanter is injected, and by proton Implantation Energy and dosage, at chip back surface, injects one deck ion, and described source ion implantation is H in this example
+, described Implantation Energy is 10MeV, and described implantation dosage is 1E15, and the Si wafer after by diffusion furnace, the back side being injected is at 450 ℃ of temperature, and annealing 15min, complete the activation of back side Proton Implantation and push away trap, forms the FS layer of n+.
Step 4: by the technique of Implantation, take conventional recipient element as the injection source, inject one deck ion at the Si single-chip back side;
Described conventional recipient element is boron element, and the energy of Implantation is 500KeV, and the dosage of Implantation is 1E15, injects one deck B ion at the Si single-chip back side.
Step 5: the Si wafer after conventional recipient element is injected is the 16h that annealed under 450 ℃ in temperature, completes to the back side is injected the activation of ion and pushed away trap, forms the p+ layer.
Step 6: by the method for sputter or evaporated metal, make Si chip back surface electrode, the metal material of backplate is Al-Ti-Ni-Ag, now obtains complete FS-IGBT device.
Embodiment 3
A kind of manufacture method of New Type Field cut-off type insulated gate bipolar transistor, it is characterized in that: step 1: at the basic MOSFET structure of the positive formation of Si single-chip, described MOSFET structure comprises the front metal electrode of the grid, p base, n+ emitter region and the grid that are comprised of polysilicon and silica and top, emitter region, the single crystalline Si sheet that described Si single-chip is N-shaped, n-drift region one side of described Si single-chip is defined as the front of Si single-chip, and its relative one side is defined as the back side;
N-drift region in described step 1 is substrate, in device architecture as drift region, the alloy that described metal electrode is Al or Al.
Step 2: to the back side of Si single-chip, carry out attenuate, the method by mechanical means or chemical corrosion is thinned to 80 μ m by the Si single-chip, then the Si single-chip is cleaned.
Concrete use SC-3 solution in described step 2 is cleaned the Si single-chip.
Step 3: the back side of carrying out proton by the energetic ion implanter is injected, and by proton Implantation Energy and dosage, at chip back surface, injects one deck ion, and described source ion implantation is H in this example
+, described Implantation Energy is 200KeV, and described implantation dosage is 1E10, and the Si wafer after by diffusion furnace, the back side being injected is at 200 ℃ to 450 ℃ temperature, and annealing 5min, complete the activation of back side Proton Implantation and push away trap, forms the FS layer of n+.
Step 4: by the technique of Implantation, take conventional recipient element as the injection source, inject one deck ion at the Si single-chip back side;
Described conventional recipient element is boron element, and the energy of Implantation is 10KeV, and the dosage of Implantation is 1E12, injects one deck B ion at the Si single-chip back side.
Step 5: the Si wafer after conventional recipient element is injected is the 5min to 24h that annealed under 200 ℃ in temperature, completes to the back side is injected the activation of ion and pushed away trap, forms the p+ layer.
Step 6: by the method for sputter or evaporated metal, make Si chip back surface electrode, the metal material of backplate is Al-V-Ni-Ag, now obtains complete FS-IGBT device.
Embodiment 4
Refer to shown in accompanying drawing, a kind of process of cut-off type insulated gate bipolar transistor (FS-IGBT) that realizes of the present invention comprises following committed step in this example:
Step 1: the side at Si single-chip (the n-zone in Fig. 1) forms basic MOSFET structure (MOSFET), comprises the grid (poly-Si in figure and the SiO that are comprised of polysilicon and silica
x), the front metal electrode ((metal in Fig. 1)) of p base (p-base in Fig. 1), n+ emitter region (n+ in Fig. 1) and grid and top, emitter region.The single crystalline Si sheet that described Si single-chip is N-shaped, described Si single-chip one side is defined as the front of Si single-chip.
Because the realization of FS layer is to complete by back process, back process is emphasis of the present invention, and literary composition specific as follows is introduced.Positive basic MOSFET structure (MOSFET), so detailed positive technique does not repeat them here.Complete all positive technique device architecture afterwards as shown in Figure 1.In figure, n-is substrate, and in device architecture, as drift region, n+ is emitter region, SiO
xform grid with poly-Si, metal is the positive metal deposited, and is generally the alloy of Al or Al.
Step 2: the opposite side to the Si single-chip carries out attenuate, and the method by mechanical means or chemical corrosion is thinned to certain thickness by the Si single-chip, then with solution, the Si single-chip is cleaned.The opposite side of described Si single-chip is defined as the back side of Si single-chip, and described certain thickness is 80 μ m to 150 μ m, the SC-3 solution that described solution is the manufacture of semiconductor Plays.
Step 3: complete by the energetic ion implanter technique that proton injects, choose suitable proton Implantation Energy and dosage, at chip back surface, inject one deck ion.Described source ion implantation is H in this example
+, described Implantation Energy is 200KeV to 10MeV, and described implantation dosage is 1E10 to 1E15, and described ion is H in this example
+ion.Si wafer after by heating or the method for light radiation, the back side being injected is annealed in proper temperature and appropriate time, completes the activation of back side Proton Implantation and pushes away trap, forms the FS layer of n+.The degree of depth that pushes away trap is determined jointly by the temperature and time of annealing.Described annealing temperature is 200 ℃ to 450 ℃, and described annealing time is 5min to 12h.The device architecture now obtained as shown in Figure 2.
Step 4: by the technique of Implantation, take conventional recipient element as the injection source, choose suitable ion implantation energy and dosage, at chip back surface, inject one deck B ion.Described conventional recipient element is boron element etc., and described Implantation Energy is 10KeV to 500KeV, and described implantation dosage is 1E12 to 1E15.
Step 5: the Si wafer after conventional recipient element is injected is annealed in proper temperature and appropriate time, completes to the back side is injected the activation of ion and pushed away trap, forms the p+ layer.Described annealing temperature is 200 ℃ to 900 ℃, and described annealing time is 5min to 24h.The device architecture now obtained as shown in Figure 3.
Step 6: by the method for sputter or evaporated metal, make Si chip back surface electrode.The material of described back metal is Al-V-Ni-Ag or Al-Ti-Ni-Ag.Now obtain complete FS-IGBT device, device architecture as shown in Figure 4.
Claims (4)
1. the manufacture method of a New Type Field cut-off type insulated gate bipolar transistor, it is characterized in that: step 1: at the basic MOSFET structure of the positive formation of Si single-chip, described MOSFET structure comprises the front metal electrode of the grid, p base, n+ emitter region and the grid that are comprised of polysilicon and silica and top, emitter region, the single crystalline Si sheet that described Si single-chip is N-shaped, n-drift region one side of described Si single-chip is defined as the front of Si single-chip, and its relative one side is defined as the back side; Step 2: attenuate is carried out at the back side to the Si single-chip, and the method by mechanical means or chemical corrosion is thinned to 80 μ m to 150 μ m by the Si single-chip, then the Si single-chip is cleaned; Step 3: the back side of carrying out proton by the energetic ion implanter is injected, and by proton Implantation Energy and dosage, at chip back surface, injects one deck ion, and described source ion implantation is H
+, described Implantation Energy is 200KeV to 10MeV, described implantation dosage is 1E10 to 1E15, Si wafer after by diffusion furnace, the back side being injected is at 200 ℃ to 450 ℃ temperature, annealing 5min to 12h, complete the activation of back side Proton Implantation and push away trap, forms the FS layer of n+; Step 4: by the technique of Implantation, take conventional recipient element as the injection source, inject one deck ion at the Si single-chip back side; Step 5: the Si wafer after conventional recipient element is injected is the 5min to 24h that annealed under 200 ℃ to 900 ℃ in temperature, completes to the back side is injected the activation of ion and pushed away trap, forms the p+ layer; Step 6: by the method for sputter or evaporated metal, make Si chip back surface electrode, the metal material of backplate is Al-V-Ni-Ag or Al-Ti-Ni-Ag, now obtains complete FS-IGBT device.
2. the manufacture method of a kind of New Type Field cut-off type insulated gate bipolar transistor according to claim 1, it is characterized in that: the n-drift region in described step 1 is substrate, the alloy that described metal electrode is Al or Al.
3. the manufacture method of a kind of New Type Field cut-off type insulated gate bipolar transistor according to claim 1, it is characterized in that: the concrete use SC-3 solution in described step 2 is cleaned the Si single-chip.
4. the manufacture method of a kind of New Type Field cut-off type insulated gate bipolar transistor according to claim 1, it is characterized in that: the described conventional recipient element in described step 4 is boron element, the energy of Implantation is 10KeV to 500KeV, the dosage of Implantation is 1E12 to 1E15, injects one deck B ion at the Si single-chip back side.
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| CN115078431A (en) * | 2022-06-16 | 2022-09-20 | 中国核动力研究设计院 | Preparation method of transmission electron microscope sample based on zirconium alloy after self-ion irradiation |
| CN116072530A (en) * | 2022-12-01 | 2023-05-05 | 北京核力同创科技有限公司 | Preparation method of FS-IGBT back electrode |
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