CN204332965U - A kind of planar gate IGBT - Google Patents
A kind of planar gate IGBT Download PDFInfo
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- CN204332965U CN204332965U CN201420761169.4U CN201420761169U CN204332965U CN 204332965 U CN204332965 U CN 204332965U CN 201420761169 U CN201420761169 U CN 201420761169U CN 204332965 U CN204332965 U CN 204332965U
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Abstract
The utility model relates to a kind of planar gate IGBT with hole bypass and the integrated flows resistance composite construction of emitter.On traditional plane grid-type IGBT basis, by adjusting shape and the area in N+ dopant implant region, form the integrated flows resistance composite construction of hole current bypass and N+ doping emitter region, this structure effectively can suppress the saturation current of IGBT device, avoids super-high-current to impact; Effectively can suppress the Latch-up phenomenon under the current state of IGBT device, reduce the resistance in hole current path; Emitter current can be made more even, avoid the electric current of regional area in IGBT device excessive; The less changing value of conduction voltage drop can also be maintained simultaneously.
Description
Technical field
The utility model relates to a kind of power semiconductor, specifically relates to a kind of planar gate IGBT.
Background technology
Igbt (Insulate-Gate Bipolar Transistor-IGBT) combines the advantage of power transistor (GiantTransistor-GTR) and field of electric force effect transistor (Power MOSFET), have good characteristic, application is very extensive; IGBT is also three terminal device: grid, collector and emitter.
Insulated gate bipolar transistor IGBT (InsulatedGateBipolarTransistor) is MOS structure bipolar device, belongs to the power device of high speed performance and the bipolar low resistance performance with power MOSFET.The range of application of IGBT is general is all the region of more than 1kHz in withstand voltage more than 600V, more than electric current 10A, frequency.Be used in the field such as stroboscope, induction heating (InductionHeating) electric rice cooker of industrial motor, civilian small-capacity motor, converter (inverter), camera more.According to the difference of encapsulation, IGBT is roughly divided into two types, and a kind of three end monomer encapsulation types being mold pressing resin and sealing, form series from TO-3P all to small-sized surface mount.Another kind is IGBT and FWD (FleeWheelDiode) (2 or 6 groups) modular type of being encapsulated in couples, is mainly used in industrial.The type of module, according to the difference of purposes, is divided into various shape and packaged type, all forms seriation.
IGBT is the natural evolution of heavy current, high-voltage applications and fast terminal equipment vertical power mosfet.MOSFET needs a source and drain passage owing to realizing a higher puncture voltage BVDSS, and this passage has very high resistivity, thus cause power MOSFET to have the high feature of RDS (on) numerical value, IGBT eliminates these major defects of existing power MOSFET.Although latest generation power MOSFET device significantly improves RDS (on) characteristic, when high level, conducting power loss still exceeds much than IGBT.The pressure drop that IGBT is lower, converts the ability of a low VCE (sat) to, and the structure of IGBT, compared with same standard bipolar device, can support more high current density, and simplify the schematic diagram of IGBT driver.IGBT (igbt) has the advantage of unipolar device and bipolar devices simultaneously, and drive circuit is simple, control circuit power consumption and cost low, on-state voltage drop is low, and device own loss is little, is the developing direction of following high-voltage great-current.
IGBT device active area is made up of the Yuan Bao unit of many surperficial MOSFET structure, the N+ dopant implant district of traditional planar gate bar sources born of the same parents structure is continuous elongate in shape, the N+ dopant implant district of continuous elongate in shape does not suppress the saturation current of IGBT device, generation super-high-current impacts, and damages IGBT device.
Utility model content
For the deficiencies in the prior art, the purpose of this utility model is to provide a kind of planar gate IGBT, by adjusting shape and the area in N+ dopant implant region, form the integrated flows resistance composite construction of hole current bypass and N+ doping emitter region, this structure effectively can suppress the saturation current of IGBT device, avoids super-high-current to impact; Effectively can suppress breech lock (Latch-up) phenomenon under the current state of IGBT device, reduce the resistance in hole current path; Emitter current can be made more even, avoid the electric current of regional area in IGBT device excessive; The less changing value of conduction voltage drop can also be maintained simultaneously.
The purpose of this utility model adopts following technical proposals to realize:
The utility model provides a kind of planar gate IGBT, described planar gate IGBT comprises substrate, is successively set on front metal electrode, isolated oxide film on substrate from top to bottom, and planar gate, P well region between planar gate and substrate, be set in turn in N+ type doped region and P+ type doped region in P well region from top to bottom, be set in turn in P+ doped region, the back side and the back metal electrode of substrate back; Its improvements are, described N+ type doped region is interrupted N+ doped region, described interrupted N+ doped region shape is rectangle, length and width ratio are 3:2, area is 20 to 30 square microns, and described P+ type doped region and interrupted N+ doped region form the bypass of planar gate IGBT hole and the integrated flows resistance composite construction of emitter jointly.
Further, the width range of the interval region of described interrupted N+ doped region is 2 to 6 microns, and area is 10 to 20 square microns; The shape of its interval region is rectangle; The P+ Implantation Energy of described P+ type doped region is greater than the N+ Implantation Energy of N+ type doped region, formation hole, described P+ type doped region bypass structure, and described interrupted N+ doped region forms the integrated flows resistance structure of emitter.
Further, described n type single crystal silicon sheet substrate comprises: electric field cut-off FS type substrate and non-break-through NPT type substrate.
Further, when n type single crystal silicon sheet substrate adopts soft break-through SPT type or electric field cut-off FS type, described planar gate IGBT comprises the N-type low concentration buffering area being positioned at n type single crystal silicon sheet substrate back; If when n type single crystal silicon sheet substrate adopts non-break-through NPT type, then do not need N-type low concentration buffering area.
Further, the forward conduction voltage drop of described planar gate IGBT is 600V to 6500V.
Compared with the prior art, the beneficial effect that the utility model reaches is:
1, the planar gate IGBT that the utility model provides passes through shape and the area in adjustment N+ dopant implant region, form the integrated flows resistance composite construction of hole current bypass and N+ doping emitter region, this structure effectively can suppress the saturation current of IGBT device, avoids super-high-current to impact; Effectively can suppress breech lock (Latch-up) phenomenon under the current state of IGBT device, reduce the resistance in hole current path; Emitter current can be made more even, avoid the electric current of regional area in IGBT device excessive; The less changing value of conduction voltage drop can also be maintained simultaneously.
2, the manufacturing processing technic adopted is igbt chip common processes, easily realizes.
Accompanying drawing explanation
Fig. 1 is the planar gate IGBT generalized section with hole bypass and the integrated flows resistance composite construction of emitter that the utility model provides;
Fig. 2 is the planar gate IGBT schematic surface with hole bypass and the integrated flows resistance composite construction of emitter that the utility model provides;
Wherein: 01-N type monocrystalline silicon piece substrate, 02-N type low concentration doping buffering area, 04-P well region, 05-N+ type doped region, 06-P+ type adulterates, 07-P+ doped region, 08-isolated oxide film, 09-front metal electrode, 10-back metal electrode.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in further detail.
The utility model provides a kind of planar gate IGBT with hole bypass and the integrated flows resistance composite construction of emitter, its generalized section and schematic surface are respectively as illustrated in fig. 1 and 2, planar gate IGBT comprises substrate 01, is successively set on front metal electrode 09, isolated oxide film 08 and planar gate 03 on substrate from top to bottom, P well region 04 between planar gate 03 and substrate 01, be set in turn in N+ type doped region 05 and P+ type doped region 06 in P well region 04 from top to bottom, be set in turn in P+ doped region, the back side 07 and the back metal electrode 10 of substrate back; Described N+ type doped region is interrupted N+ doped region, interrupted N+ doped region shape is rectangle, and length and width ratio are 3:2, and area is 20 to 30 square microns, the width range stating the interval region of interrupted N+ doped region is 2 to 6 microns, and area is 10 to 20 square microns; The shape of its interval region is rectangle; The P+ Implantation Energy of described P+ type doped region is greater than the N+ Implantation Energy of N+ type doped region, formation hole, described P+ type doped region bypass structure, and described interrupted N+ doped region forms the integrated flows resistance structure of emitter; Described P+ type doped region and interrupted N+ doped region form the bypass of planar gate IGBT hole and the integrated flows resistance composite construction of emitter jointly; Described substrate is the n type single crystal silicon sheet substrate of Uniform Doped, and described n type single crystal silicon sheet substrate comprises the substrate N-layer and substrate N+ layer that distribute successively from top to bottom.
Described n type single crystal silicon sheet substrate comprises:
A, electric field cut-off FS type substrate: generation type first the n type single crystal silicon sheet of Uniform Doped is carried out substrate thinning to required substrate thickness; Front adopts the mode growth protecting sacrifice layer of oxidation and deposit, adulterates in the N-type low concentration buffering area then adopting ion implantation mode to carry out silicon chip back side; Adopt the impurity of high temperature Long Time Thermal annealing way to N-type low concentration buffering area to activate and knot, form N-type low concentration doping buffering area; Finally form terminal structure and active area structure cell; Inject finally by doping and form substrate back P type conductivity modulation layer;
The most high-dopant concentration of described N-type low concentration doping buffering area be the 5e2 to 1e4 of n type single crystal silicon sheet substrate concentration doubly;
B, non-break-through NPT type substrate: generation type first carries out the formation of terminal structure and source, active area born of the same parents' structure; After IGBT device surface texture is formed, the n type single crystal silicon sheet carrying out Uniform Doped is thinned to required substrate thickness; Finally form the doping of substrate back P type conductivity modulation layer to inject.
When n type single crystal silicon sheet substrate adopts soft break-through SPT type or electric field cut-off FS type, described planar gate IGBT comprises the N-type low concentration buffering area being positioned at n type single crystal silicon sheet substrate back; If when n type single crystal silicon sheet substrate adopts non-break-through NPT type, then do not need N-type low concentration buffering area.
The utility model also provides a kind of manufacture method with the planar gate IGBT of hole bypass and the integrated flows resistance composite construction of emitter, comprises the steps:
(1) to the preliminary treatment of n type single crystal silicon sheet substrate 01: N impurity doping concentration and the thickness of described n type single crystal silicon sheet substrate need to select according to the different puncture voltage of planar gate IGBT and forward conduction voltage drop demand (600V to 6500V), and by acid, alkali, deionized water ultrasonic cleaning operation, chemical treatment is carried out to n type single crystal silicon sheet substrate surface;
(2) N-type low concentration doping buffering area 02 is made: adopt the mode growth protecting of oxidation or deposit to sacrifice film quality to the n type single crystal silicon sheet substrate face of Uniform Doped, the impurity generation that N-type low concentration doping sends out buffering area is carried out in silicon chip back side employing ion implantation mode, carrying out temperature is again 1100 degree to 1150 degree, time is the high temperature long term annealing technique of 600 minutes to 1800 minutes, carry out activation and the knot of ion, knot is to the required degree of depth, front protecting sacrifice layer film quality is removed after forming N-type low concentration doping buffering area, if need N-type low concentration doping buffering area when soft break-through SPT type or electric field cut-off FS type, if when substrate is non-break-through NPT type, do not need N-type low concentration doping buffering area,
(3) planar gate 03 is made: the mode of the n type single crystal silicon sheet substrate of Uniform Doped being carried out to high-temperature oxydation, at the oxide-film of silicon chip surface growth 0.1 to 0.2 micron, and adopt deposit mode growing polycrystalline silicon electrode, then carry out photoetching and etching formation planar gate;
(4) make P well region 04: by injection mode, the doping of P type is carried out to the gate openings that planar gate is formed, then carries out high annealing, by P type doping knot to 4 to 6 microns, form P well region;
(5) make N+ type doped region 05: form mask by photoetching, adopt injection mode to carry out N+ doping to the polycrystalline opening of P well region, form interrupted N+ doped region, form N+ type doped region, ensure the formation of hole bypass and integrated flows resistance structure; N+ type doped region of the present utility model changes interrupted injection shape into by traditional continuous injection shape, and the width range of interruption is at 2 to 6 microns, and the centre position of the bar shaped N-type injection slab region of opposite side will be aimed in the position of interruption; Subsequently through deposition oxidation film, carry out anti-carving formation Spacer, then carry out self aligned P+ dopant implant, P+ Implantation Energy is greater than N+ Implantation Energy; The discontiguous area that N+ injects is mainly P+ injection zone and forms hole bypass structure, and the N+ injection zone be interrupted defines the integrated flows resistance structure of emitter;
(6) make P+ type doped region 06, planar gate IGBT surface: grow isolation from oxygen SiClx by deposit mode, anti-carve comprehensively and form Spacer structure, ensure contact hole break-through N+ but can not carve to wear P+; Adopt autoregistration ion implantation mode to carry out P+ doping, form P+ type doped region;
(7) P+ doped region, the planar gate IGBT back side 07 is made: if substrate adopts soft break-through SPT type or electric field cut-off FS type, the impurity adopting ion implantation mode to carry out P+ doped region at silicon chip back side generates, carry out annealing process again, carry out activation and the knot of ion, knot is in 0.5 to 1 micrometer range; If substrate adopts non-break-through NPT type, then metal electrode structure is front overleaf makes P+ doped region, the back side;
(8) isolated oxide film 08 and front metal electrode, 09 is made: use chemical deposition mode to grow boron phosphorus doping glass film quality, carry out the isolation of planar gate IGBT device, photoetching and the etching of carrying out contact hole form isolation oxidation membrane structure, use physical deposition or evaporation mode growth aluminium alloy, carry out photoetching and the etching of metal, remove unwanted metallic member, form front metal electrode, complete planar gate IGBT front electrode and connect;
(9) back metal electrode 10 is made: the thinning or wet etching of grinding is carried out to n type single crystal silicon sheet substrate and cleans, adopt physical deposition or evaporation to form back metal electrode, complete the electrical characteristics connection of the planar gate IGBT back side.
A kind of planar gate IGBT with hole bypass and the integrated flows resistance composite construction of emitter that the utility model provides.On traditional plane grid-type IGBT basis, by adjusting shape and the area in N+ dopant implant region, form the integrated flows resistance composite construction of hole current bypass and N+ doping emitter region, this structure effectively can suppress the saturation current of IGBT device, avoids super-high-current to impact; Effectively can suppress the Latch-up phenomenon under the current state of IGBT device, reduce the resistance in hole current path; Emitter current can be made more even, avoid the electric current of regional area in IGBT device excessive; The less changing value of conduction voltage drop can also be maintained simultaneously.
Finally should be noted that: above embodiment is only in order to illustrate that the technical solution of the utility model is not intended to limit; although be described in detail the utility model with reference to above-described embodiment; those of ordinary skill in the field still can modify to embodiment of the present utility model or equivalent replacement; these do not depart from any amendment of the utility model spirit and scope or equivalent replacement, are all applying within the claims of the present utility model awaited the reply.
Claims (5)
1. a planar gate IGBT, described planar gate IGBT comprises substrate, is successively set on front metal electrode, isolated oxide film on substrate from top to bottom, and planar gate, P well region between planar gate and substrate, be set in turn in N+ type doped region and P+ type doped region in P well region from top to bottom, be set in turn in P+ doped region, the back side and the back metal electrode of substrate back; It is characterized in that, described N+ type doped region is interrupted N+ doped region, described interrupted N+ doped region shape is rectangle, length and width ratio are 3:2, area is 20 to 30 square microns, and described P+ type doped region and interrupted N+ doped region form the bypass of planar gate IGBT hole and the integrated flows resistance composite construction of emitter jointly.
2. planar gate IGBT as claimed in claim 1, it is characterized in that, the width range of the interval region of described interrupted N+ doped region is 2 to 6 microns, and area is 10 to 20 square microns; The shape of its interval region is rectangle; The P+ Implantation Energy of described P+ type doped region is greater than the N+ Implantation Energy of N+ type doped region, formation hole, described P+ type doped region bypass structure, and described interrupted N+ doped region forms the integrated flows resistance structure of emitter.
3. planar gate IGBT as claimed in claim 1, it is characterized in that, described substrate is n type single crystal silicon sheet substrate, and described n type single crystal silicon sheet substrate comprises: electric field cut-off FS type substrate and non-break-through NPT type substrate.
4. planar gate IGBT as claimed in claim 3, is characterized in that, when n type single crystal silicon sheet substrate adopts soft break-through SPT type or electric field cut-off FS type, described planar gate IGBT comprises the N-type low concentration buffering area being positioned at n type single crystal silicon sheet substrate back; If when n type single crystal silicon sheet substrate adopts non-break-through NPT type, then do not need N-type low concentration buffering area.
5. the planar gate IGBT according to any one of claim 1-4, is characterized in that, the forward conduction voltage drop of described planar gate IGBT is 600V to 6500V.
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| CN201420761169.4U CN204332965U (en) | 2014-12-04 | 2014-12-04 | A kind of planar gate IGBT |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104393032A (en) * | 2014-12-04 | 2015-03-04 | 国家电网公司 | Plane gate insulated gate bipolar transistor (IGBT) and manufacturing method thereof |
| TWI794647B (en) * | 2019-09-27 | 2023-03-01 | 加拿大商萬國半導體國際有限合夥公司 | Device of improving igbt light load efficiency |
-
2014
- 2014-12-04 CN CN201420761169.4U patent/CN204332965U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104393032A (en) * | 2014-12-04 | 2015-03-04 | 国家电网公司 | Plane gate insulated gate bipolar transistor (IGBT) and manufacturing method thereof |
| TWI794647B (en) * | 2019-09-27 | 2023-03-01 | 加拿大商萬國半導體國際有限合夥公司 | Device of improving igbt light load efficiency |
| TWI827449B (en) * | 2019-09-27 | 2023-12-21 | 加拿大商萬國半導體國際有限合夥公司 | Device of improving igbt light load efficiency |
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