CN106298897A - A kind of planar gate IGBT with separate type colelctor electrode and preparation method thereof - Google Patents
A kind of planar gate IGBT with separate type colelctor electrode and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title description 5
- 239000000758 substrate Substances 0.000 claims abstract description 107
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 14
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 46
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- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 230000005684 electric field Effects 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 9
- 230000008020 evaporation Effects 0.000 claims description 9
- 238000001704 evaporation Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 claims description 5
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 3
- 239000003513 alkali Substances 0.000 claims description 3
- 238000005234 chemical deposition Methods 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims description 3
- 238000005289 physical deposition Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000013049 sediment Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000002203 pretreatment Methods 0.000 claims description 2
- 230000001934 delay Effects 0.000 claims 1
- 230000001629 suppression Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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Abstract
nullThe present invention relates to a kind of planar gate IGBT with separate type colelctor electrode，Including substrate、The front metal electrode being successively set on substrate、Isolated oxide film and planar gate，P-well region between planar gate and substrate，It is set in turn in N+ type doped region and P+ type doped region in p-well region，It is set in turn in the low-doped relief area of back side N-type and the back side P+ collecting zone of substrate back，P+ collecting zone is provided with the back side groove using dielectric to fill overleaf，Back side depth of groove is more than、Thickness equal to or less than back side P+ collecting zone，Dielectric fills groove wholly or in part，Dielectric has overlapping with P+ collecting zone，The present invention is on the basis of traditional plane grid-type IGBT，Separate type colelctor electrode is formed by increasing shallow grooves or oxide layer isolation structure，This structure effectively suppresses the hole injection efficiency of IGBT device，Avoid excessive QRR；Effectively the tail currents in suppression IGBT device turn off process, reduces turn-off power loss so that switching speed is faster.
Description
Technical field
The present invention relates to a kind of power semiconductor and preparation method thereof, a kind of have the flat of separate type colelctor electrode
Face grid IGBT and preparation method thereof.
Background technology
Igbt (Insulate-Gate Bipolar Transistor IGBT) combines power transistor (Giant
Transistor GTR) and the advantage of field of electric force effect transistor (Power MOSFET), there is good characteristic, application
Field is the most extensive；IGBT is also three terminal device: grid, collector and emitter.
Insulated gate bipolar transistor IGBT (InsulatedGateBipolarTransistor) is MOS structure bipolar device, belongs to and has
The high speed performance of power MOSFET and the power device of bipolar low resistance performance.The range of application of IGBT is general all pressure
More than 600V, more than electric current 10A, frequency are the region of more than 1kHz.Many uses are at industrial motor, civilian low capacity electricity
The fields such as machine, changer (inverter), the stroboscope of photographing unit, sensing heating (InductionHeating) electric cooker.
According to the difference of encapsulation, IGBT is roughly divided into two types, and a kind of three end monomer encapsulation types being mold pressing resin and sealing, from TO
-3P has formed series the most to small-sized surface mount.Another kind is IGBT Yu FWD (FleeWheelDiode) in couples
The modular type that (2 or 6 groups) are encapsulated, is mainly used in industrial.The type of module, according to the difference of purposes, is divided into many
Plant shape and packaged type, the most form seriation.
IGBT is heavy current, high-voltage applications and the natural evolution of fast terminal equipment vertical power MOSFET.MOSFET
Need a source-drain path owing to realizing higher breakdown voltage BVDSS, and this passage have the highest resistivity,
Thus resulting in power MOSFET and have the feature that RDS (on) numerical value is high, IGBT eliminates these of existing power MOSFET
Major defect.Although latest generation power MOSFET device has been greatly improved RDS (on) characteristic, but when high level,
Conducting power loss still exceeds much than IGBT.The pressure drop that IGBT is relatively low, is converted into the ability of a low VCE (sat),
And the structure of IGBT, compared with same standard bipolar device, more high current density can be supported, and simplify IGBT driving
The schematic diagram of device.
IGBT (igbt) has the advantage of unipolar device and bipolar devices simultaneously, and drive circuit is simple,
Control circuit power consumption and low cost, on-state voltage drop is low, and device own loss is little, is the developing direction of following high-voltage great-current.
IGBT device active area is to be made up of source born of the same parents' unit of many surfaces MOSFET structure, and the back side is p-type collector structure.
Traditional tail currents, turn-off power loss and IGBT device QRR in planar gate IGBT device turn off process is very big,
Easily damage IGBT device, accordingly, it would be desirable to a kind of tail currents reduced in IGBT device turn off process, reduce device and close
Breakdown consumes, and can reduce the planar gate IGBT device of the QRR of device.
Summary of the invention
For solving above-mentioned deficiency of the prior art, it is an object of the invention to provide a kind of planar gate with separate type colelctor electrode
IGBT and preparation method thereof, people's planar gate IGBT device that the present invention provides effectively suppresses the hole injection efficiency of IGBT device,
Avoid excessive QRR；Can effectively suppress the tail currents in IGBT device turn off process, reduce turn-off power loss；
Simultaneously it is also possible that switching speed faster.In order to some aspects of the embodiment disclosed are had a basic understanding, give below
Go out simple summary.This summarized section is not extensive overview, is not key/critical component to be determined or describes these
The protection domain of embodiment.Its sole purpose is to present some concepts, in this, as following detailed description by simple form
Preamble.
It is an object of the invention to use following technical proposals to realize:
In order to reduce the tail currents in IGBT device turn off process, reduce device turn-off power loss, present invention decreases device
QRR, increases shallow grooves by the back side or oxide layer isolation structure forms separate type colelctor electrode.This structure can be effective
The hole injection efficiency of suppression IGBT device, it is to avoid excessive QRR；IGBT device can be effectively suppressed to turn off
During tail currents, reduce turn-off power loss；Simultaneously it is also possible that switching speed faster.
The present invention provides a kind of planar gate IGBT with separate type colelctor electrode, described planar gate IGBT include substrate, to
Under the front metal electrode, isolated oxide film and the planar gate that are successively set on substrate, the p-well between planar gate and substrate
District, is set in turn in N+ type doped region and P+ type doped region in p-well region from top to bottom, is set in turn in the back side of substrate back
N-type low concentration doping relief area and back side P+ collecting zone；It thes improvement is that, P+ collecting zone is provided with employing absolutely overleaf
The back side groove of edge Filled Dielectrics, described back side depth of groove greater than, equal to or less than the thickness of back side P+ collecting zone, described absolutely
Edge medium completely or partially fills groove, and described dielectric has overlapping with P+ collecting zone, to avoid back metal electrode and N
Shaped material contacts；
Described substrate is the n type single crystal silicon sheet substrate of Uniform Doped, and described n type single crystal silicon sheet substrate includes dividing the most successively
The substrate N-layer of cloth and substrate N+ layer.
Further, described dielectric fills part and back side groove forms IGBT back side isolated oxide layer.
Further, described n type single crystal silicon sheet substrate includes:
A, electric field cut-off FS type substrate: generation type is the n type single crystal silicon sheet of Uniform Doped first to carry out substrate thinning to required
The substrate thickness wanted；Front uses oxidation and the mode growth protecting sacrifice layer of deposit, then uses ion implanting mode to carry out silicon
The N-type low concentration relief area at the sheet back side is doped；Use miscellaneous to N-type low concentration relief area of high temperature Long Time Thermal annealing way
Matter carries out activating and knot, forms N-type low concentration doping relief area；Eventually form terminal structure and active area structure cell；?
Injected by doping afterwards and form substrate back p-type conductivity modulation layer；
The 5e2 to 1e4 that high-dopant concentration is n type single crystal silicon sheet substrate concentration of described N-type low concentration doping relief area times；
B, non-break-through NPT type substrate: generation type is first to carry out terminal structure and the formation of active area source born of the same parents' structure；At IGBT
After device surface structure is formed, the n type single crystal silicon sheet carrying out Uniform Doped is thinned to required substrate thickness；Eventually form lining
The doping of bottom back side p-type conductivity modulation layer is injected.
Further, when n type single crystal silicon sheet substrate uses soft break-through SPT type or electric field cut-off FS type, described planar gate IGBT
Including the N-type low concentration relief area being positioned at n type single crystal silicon sheet substrate back；If n type single crystal silicon sheet substrate uses non-break-through NPT
During type, then need not N-type low concentration relief area.
The present invention also provides for the manufacture method of a kind of planar gate IGBT, and it thes improvement is that, described method comprises the steps:
(1) to n type single crystal silicon sheet substrate pre-treatment: the N impurity doping concentration of described n type single crystal silicon sheet substrate and thickness
The breakdown voltage different according to planar gate IGBT and forward conduction voltage drop is needed to select, and by acid, alkali, deionized water
Ultrasonic cleaning operation, carries out chemical treatment to n type single crystal silicon sheet substrate surface；
(2) N-type low concentration doping relief area is made: the n type single crystal silicon sheet substrate face of Uniform Doped is used oxidation or forms sediment
Long-pending mode growth protecting sacrifices film quality, uses ion implanting mode to carry out N-type low concentration doping at silicon chip back side and sends out relief area
Impurity generates, then carries out annealing process, carries out activation and the knot of ion, knot to the required degree of depth, forms N-type low dense
Degree removes front protecting sacrifice layer film quality behind doped buffer region, if needing N-type low when soft break-through SPT type or electric field cut-off FS type
Doped in concentrations profiled relief area, if substrate is non-break-through NPT type, need not N-type low concentration doping relief area；
(3) planar gate is made: the n type single crystal silicon sheet substrate of Uniform Doped is carried out the mode of high-temperature oxydation, at silicon chip table
Look unfamiliar long oxide-film, and use deposit mode growing polycrystalline silicon electrode, then carry out photoetching and etching forms planar gate；
(4) p-well region is made: the gate openings forming planar gate carries out p-type doping by injection mode, then carries out height
Temperature annealing, adulterate knot by p-type, forms the p-well region of IGBT active area；
(5) make N+ type doped region: deposit photoresist, by being lithographically formed mask, the polycrystalline opening of p-well region is used note
Enter mode and carry out N+ doping, form N+ type doped region；
(6) planar gate IGBT surface P+ type doped region is made: grow oxide-film by deposit mode, anti-carve formation many comprehensively
Brilliant sidewall protection structure, uses autoregistration ion implanting mode to carry out P+ doping, forms P+ type doped region；
(7) planar gate IGBT back side P+ collecting zone is made: if substrate uses soft break-through SPT type or electric field cut-off FS type,
The impurity using ion implanting mode to carry out P+ doped region at silicon chip back side generates, then carries out annealing process, carries out swashing of ion
Live and knot；If substrate uses non-break-through NPT type, before metal electrode structure, make back side P+ doped region the most overleaf；
(8) make chip back isolation oxidation Rotating fields: deposit photoresist, by being lithographically formed mask, etch P+ collecting zone,
Forming back side groove, depth of groove selects greater than, equal to or is less than the thickness of P+ collecting zone, uses deposit or evaporation mode raw
Long dielectric, fills groove, is filled up completely with or is partially filled with, and the lower surface of dielectric is to the distance of P+ collecting zone lower surface
In 0 to 1 micrometer range, dielectric part must cover P+ collecting zone, it is to avoid backside collector metal contacts with n type material；
(9) front metal electrode is made: use chemical deposition mode to grow boron phosphorus doping glass film quality, carry out planar gate IGBT
Device isolation, the photoetching and the etching that carry out contact hole form isolation oxidation membrane structure, use physical deposition or evaporation mode growth aluminum
Alloy, carries out photoetching and the etching of metal, forms front metal electrode, completes planar gate IGBT front electrode and connects；
(10) back metal electrode is made: n type single crystal silicon sheet substrate is ground thinning or wet etching clean, use thing
Reason deposit or evaporation form back metal electrode, complete planar gate IGBT back side electrical characteristics and connect.
Further, in described step (), the forward conduction voltage drop of planar gate IGBT is 600V to 6500V.
Further, in described step (two), the temperature of described annealing process is 1100 degree to 1150 degree, and the time is 600
Minute to 1800 minutes.
Further, in described step (three), the oxide-film in silicon chip surface growth is 0.1 to 0.2 micron.
Further, in described step (four), it is knot to 4 to 6 microns that p-type is adulterated, forms the P of IGBT active area
Well region.
Further, in described step (seven), ion is by knot to 0.5 to 1 micrometer range.
Compared with immediate prior art, the excellent effect that the technical scheme that the present invention provides has is:
(1) present invention is by increasing shallow grooves or oxide layer isolation structure, forms the planar gate with separate type collector structure
IGBT, can effectively suppress the hole injection efficiency of IGBT device, it is to avoid excessive QRR, reduces IGBT device
Tail currents in part turn off process, reduces turn-off power loss, improves devices switch speed.
(2) this structure can be used for trench gate structure, back side shallow grooves or oxide layer isolation structure and can have any shape.
(3) manufacturing processing technic used is igbt chip common processes, easily realizes.
For above-mentioned and relevant purpose, one or more embodiments include will be explained in below and the most special
The feature pointed out.Description below and accompanying drawing describe some illustrative aspects, and only each enforcement of its instruction in detail
Some modes in the utilizable various modes of principle of example.Other benefit and novel features by along with following specifically
Bright being considered in conjunction with the accompanying and become obvious, the disclosed embodiments are intended to include all these aspect and their equivalent.
Accompanying drawing explanation
Accompanying drawing is for providing a further understanding of the present invention, and constitutes a part for description, with embodiments of the invention one
Rise and be used for explaining the present invention, be not intended that limitation of the present invention.In the accompanying drawings:
Fig. 1 is a kind of planar gate IGBT generalized section with separate type collector structure that the present invention provides；
Fig. 2 is the planar gate IGBT generalized section that the another kind that the present invention provides has separate type collector structure；
Fig. 3 is the planar gate IGBT generalized section that the second that the present invention provides has separate type collector structure；
Fig. 4 be the present invention provide the third there is the planar gate IGBT generalized section of separate type collector structure；
Fig. 5 is the planar gate IGBT generalized section that provide the 4th kind of the present invention has separate type collector structure；
Fig. 6 is a kind of planar gate IGBT backside surface schematic diagram with separate type collector structure that the present invention provides；
Fig. 7 is the planar gate IGBT backside surface schematic diagram that the another kind that the present invention provides has separate type collector structure；
Fig. 8 is the planar gate IGBT backside surface schematic diagram that the second that the present invention provides has separate type collector structure；
Fig. 9 be the present invention provide the third there is the planar gate IGBT backside surface schematic diagram of separate type collector structure；
Figure 10 is the planar gate IGBT backside surface schematic diagram that provide the 4th kind of the present invention has separate type collector structure；
Figure 11 is the planar gate IGBT backside surface schematic diagram that provide the 5th kind of the present invention has separate type collector structure；
Wherein: 01-N type monocrystalline silicon piece substrate, 02-N type low concentration doping relief area, 04-P well region, 05-N+ type doped region,
06-P+ type adulterates, 07-P+ collecting zone, 08-isolated oxide film, 09-front metal electrode, 10-back metal electrode, the 11-back side
Isolating oxide layer.
Detailed description of the invention
Below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is described in further detail.
The following description and drawings illustrate specific embodiments of the present invention fully, to enable those skilled in the art to put into practice it
?.Other embodiments can include structure, logic, electric, process and other change.Embodiment only generation
The change that table is possible.Unless explicitly requested, otherwise individually assembly and function are optional, and the order operated can change.
The part of some embodiments and feature can be included in or replace part and the feature of other embodiments.The enforcement of the present invention
The scope of scheme includes the gamut of claims, and all obtainable equivalent of claims.In this article,
These embodiments of the present invention can be represented by " inventing " individually or generally with term, and this is only used to conveniently, and
And if in fact disclose the invention more than, be not meant to automatically to limit this application and in the range of any single invention or send out
Bright design.
The present invention provides a kind of planar gate IGBT with separate type collector structure, its generalized section and the planar gate IGBT back of the body
The most as shown in figs. 1 and 6, planar gate IGBT includes substrate 01, is successively set on substrate from top to bottom face schematic surface
Front metal electrode 09, isolated oxide film 08 and planar gate 03, the p-well region 04 between planar gate 03 and substrate 01,
It is set in turn in N+ type doped region 05 and P+ type doped region 06 in p-well region 04 from top to bottom, is set in turn in substrate back
N-type low concentration doping relief area, the back side 02, P+ collecting zone 07 and back metal electrode 10；The back of the body of metal electrode 10 overleaf
Face P+ collecting zone is provided with the back side groove using dielectric to fill, and described back side depth of groove is equal to back side P+ collecting zone
Thickness, described dielectric is filled up completely with groove,；Described dielectric fills part and back side groove forms IGBT back side isolated
Oxide layer 11.The another kind that the present invention provides has the planar gate IGBT generalized section of separate type collector structure；The second
There is the planar gate IGBT generalized section of separate type collector structure；The third has the planar gate of separate type collector structure
IGBT generalized section and the 4th kind of planar gate IGBT generalized section with separate type collector structure are respectively such as Fig. 2-5 institute
Showing, the planar gate IGBT backside surface schematic diagram of its correspondence is as illustrated in figures 7-11.
Fig. 2 is the planar gate IGBT generalized section that the another kind that the present invention provides has separate type collector structure, planar gate
Front metal electrode 09, isolated oxide film 08 and the planar gate that IGBT includes substrate 01, is successively set on substrate from top to bottom
Pole 03, the p-well region 04 between planar gate 03 and substrate 01, it is set in turn in N+ type doping in p-well region 04 from top to bottom
District 05 and P+ type doped region 06, be set in turn in the N-type low concentration doping relief area, the back side 02 of substrate back, P+ collecting zone
07 and back metal electrode 10；The back side P+ collecting zone of metal electrode 10 is provided with the back side using dielectric to fill overleaf
Groove, described back side depth of groove is more than the thickness of back side P+ collecting zone, and described dielectric is filled up completely with groove；Described insulation
Filled Dielectrics part and back side groove form IGBT back side isolated oxide layer 11.
Fig. 3 is the planar gate IGBT generalized section that the another kind that the present invention provides has separate type collector structure, planar gate
Front metal electrode 09, isolated oxide film 08 and the planar gate that IGBT includes substrate 01, is successively set on substrate from top to bottom
Pole 03, the p-well region 04 between planar gate 03 and substrate 01, it is set in turn in N+ type doping in p-well region 04 from top to bottom
District 05 and P+ type doped region 06, be set in turn in the N-type low concentration doping relief area, the back side 02 of substrate back, P+ collecting zone
07 and back metal electrode 10；The back side P+ collecting zone of metal electrode 10 is provided with the back side using dielectric to fill overleaf
Groove, described back side depth of groove is less than the thickness of back side P+ collecting zone, and described dielectric is filled up completely with groove；Described insulation
Filled Dielectrics part and back side groove form IGBT back side isolated oxide layer 11.
Fig. 4 is the planar gate IGBT generalized section that the another kind that the present invention provides has separate type collector structure, planar gate
Front metal electrode 09, isolated oxide film 08 and the planar gate that IGBT includes substrate 01, is successively set on substrate from top to bottom
Pole 03, the p-well region 04 between planar gate 03 and substrate 01, it is set in turn in N+ type doping in p-well region 04 from top to bottom
District 05 and P+ type doped region 06, be set in turn in the N-type low concentration doping relief area, the back side 02 of substrate back, P+ collecting zone
07 and back metal electrode 10；The back side P+ collecting zone of metal electrode 10 is provided with the back side using dielectric to fill overleaf
Groove, described back side depth of groove is equal to the thickness of back side P+ collecting zone, and described dielectric is partially filled with groove；Described insulation
Filled Dielectrics part and back side groove form IGBT back side isolated oxide layer 11.
Fig. 5 is the planar gate IGBT generalized section that the another kind that the present invention provides has separate type collector structure, planar gate
Front metal electrode 09, isolated oxide film 08 and the planar gate that IGBT includes substrate 01, is successively set on substrate from top to bottom
Pole 03, the p-well region 04 between planar gate 03 and substrate 01, it is set in turn in N+ type doping in p-well region 04 from top to bottom
District 05 and P+ type doped region 06, be set in turn in the N-type low concentration doping relief area, the back side 02 of substrate back, P+ collecting zone
07 and back metal electrode 10；The back side P+ collecting zone of metal electrode 10 is provided with the back side using dielectric to fill overleaf
Groove, described back side depth of groove is more than the thickness of back side P+ collecting zone, and described dielectric is partially filled with groove, described insulation
Medium has overlapping with P+ collecting zone, it is to avoid back metal electrode contacts with n type material；Described dielectric fills part and the back side
Groove forms IGBT back side isolated oxide layer 11.
Fig. 6 is a kind of planar gate IGBT backside surface schematic diagram with separate type collector structure that the present invention provides, and 11 are
Back side isolated oxide layer, 07 is back side collecting zone.IGBT back side isolated oxide layer 11 can have any shape, Arbitrary distribution,
As illustrated in figures 7-11.
Described substrate is the n type single crystal silicon sheet substrate of Uniform Doped, and described n type single crystal silicon sheet substrate includes dividing the most successively
The substrate N-layer of cloth and substrate N+ layer.Described n type single crystal silicon sheet substrate includes:
A, electric field cut-off FS type substrate: generation type is the n type single crystal silicon sheet of Uniform Doped first to carry out substrate thinning to required
The substrate thickness wanted；Front uses oxidation and the mode growth protecting sacrifice layer of deposit, then uses ion implanting mode to carry out silicon
The N-type low concentration relief area at the sheet back side is doped；Use miscellaneous to N-type low concentration relief area of high temperature Long Time Thermal annealing way
Matter carries out activating and knot, forms N-type low concentration doping relief area；Eventually form terminal structure and active area structure cell；?
Injected by doping afterwards and form substrate back p-type conductivity modulation layer；
The 5e2 to 1e4 that high-dopant concentration is n type single crystal silicon sheet substrate concentration of described N-type low concentration doping relief area times；
B, non-break-through NPT type substrate: generation type is first to carry out terminal structure and the formation of active area source born of the same parents' structure；At IGBT
After device surface structure is formed, the n type single crystal silicon sheet carrying out Uniform Doped is thinned to required substrate thickness；Eventually form lining
The doping of bottom back side p-type conductivity modulation layer is injected.
When n type single crystal silicon sheet substrate uses soft break-through SPT type or electric field cut-off FS type, described planar gate IGBT includes position
N-type low concentration relief area in n type single crystal silicon sheet substrate back；If n type single crystal silicon sheet substrate uses non-break-through NPT type,
Then need not N-type low concentration relief area.
The present invention also provides for the manufacture method of a kind of planar gate IGBT with separate type collector structure, comprises the steps:
(1) to n type single crystal silicon sheet substrate 01 pretreatment: the N impurity doping concentration of described n type single crystal silicon sheet substrate is with thick
Degree needs the breakdown voltage different according to planar gate IGBT and forward conduction voltage drop demand (600V to 6500V) to select,
And by acid, alkali, deionized water ultrasonic cleaning operation, n type single crystal silicon sheet substrate surface is carried out chemical treatment；
(2) N-type low concentration doping relief area is made: the n type single crystal silicon sheet substrate face of Uniform Doped is used oxidation or forms sediment
Long-pending mode growth protecting sacrifices film quality, uses ion implanting mode to carry out N-type low concentration doping at silicon chip back side and sends out relief area
Impurity generates, then to carry out temperature be 1100 degree to 1150 degree, and the time is the high temperature long term annealing of 600 minutes to 1800 minutes
Technique, carries out activation and the knot of ion, knot to the required degree of depth, just removes after forming N-type low concentration doping relief area
Face protection sacrifice layer film quality, if needing N-type low concentration doping relief area when soft break-through SPT type or electric field cut-off FS type, if lining
The end is then to need not N-type low concentration doping relief area during non-break-through NPT type；
(3) planar gate is made: the n type single crystal silicon sheet substrate of Uniform Doped is carried out the mode of high-temperature oxydation, at silicon chip table
The oxide-film of length 0.1 to 0.2 micron of looking unfamiliar, and use deposit mode growing polycrystalline silicon electrode, then it is flat with etching formation to carry out photoetching
Face grid；
(4) p-well region is made: the gate openings forming planar gate carries out p-type doping by injection mode, then carries out height
Temperature annealing, adulterate knot to 4 to 6 microns by p-type, forms the p-well region of IGBT active area；
(5) make N+ type doped region: deposit photoresist, by being lithographically formed mask, the polycrystalline opening of p-well region is used note
Enter mode and carry out N+ doping, form N+ type doped region；
(6) planar gate IGBT surface P+ type doped region is made: grow oxide-film by deposit mode, anti-carve formation many comprehensively
Brilliant sidewall protection structure, uses autoregistration ion implanting mode to carry out P+ doping, forms P+ type doped region；
(7) planar gate IGBT back side P+ collecting zone is made: if substrate uses soft break-through SPT type or electric field cut-off FS type,
The impurity using ion implanting mode to carry out P+ doped region at silicon chip back side generates, then carries out annealing process, carries out swashing of ion
Live and knot, in knot to 0.5 to 1 micrometer range；If substrate uses non-break-through NPT type, metal electrode structure the most overleaf
Front making back side P+ doped region；
(8) make chip back isolation oxidation Rotating fields: deposit photoresist, by being lithographically formed mask, etch P+ collecting zone,
Forming back side groove, depth of groove may select greater than, equal to or is less than the thickness of P+ collecting zone, uses deposit or evaporation mode
Growth dielectric, fills groove, can be filled up completely with and can also be partially filled with, and the lower surface of dielectric is to P+ collecting zone following table
The distance in face is in 0 to 1 micrometer range, and dielectric part must cover P+ collecting zone, it is to avoid backside collector metal and N-type material
Material contact, this step is the most essential steps of the present invention.
(9) front metal electrode is made: use chemical deposition mode to grow boron phosphorus doping glass film quality, carry out planar gate IGBT
Device isolation, the photoetching and the etching that carry out contact hole form isolation oxidation membrane structure, use physical deposition or evaporation mode growth aluminum
Alloy, carries out photoetching and the etching of metal, forms front metal electrode, completes planar gate IGBT front electrode and connects；
(10) back metal electrode is made: n type single crystal silicon sheet substrate is ground thinning or wet etching clean, use thing
Reason deposit or evaporation form back metal electrode, complete planar gate IGBT back side electrical characteristics and connect.
A kind of planar gate IGBT with separate type colelctor electrode that the present invention provides, on the basis of traditional plane grid-type IGBT,
Forming separate type colelctor electrode by increasing shallow grooves or oxide layer isolation structure, this structure can effectively suppress the sky of IGBT device
Cave injection efficiency, it is to avoid excessive QRR；Can effectively suppress the tail currents in IGBT device turn off process,
Reduce turn-off power loss；Simultaneously it is also possible that switching speed faster.
The particular order of the step during disclosed in should be understood that or level are the examples of illustrative methods.Based on design preference,
The particular order of the step during it should be understood that or level can obtain weight in the case of without departing from the protection domain of the disclosure
New arrangement.Appended claim to a method gives the key element of various step with exemplary order, and is not limited to described
Particular order or level.
In above-mentioned detailed description, various features combine together in single embodiment, to simplify the disclosure.Should not
It is construed to reflect such intention by this open method, i.e. the embodiment of theme required for protection is it will be clear that ground exists
The more feature of feature stated in each claim.On the contrary, as the following claims reflect, this
Daylight is in the state fewer than whole features of disclosed single embodiment.Therefore, appending claims is the most clearly
Being merged in detailed description, wherein each claim is alone as the single preferred embodiment of the present invention.
Described above includes the citing of one or more embodiment.Certainly, in order to describe above-described embodiment, parts or side are described
The all possible combination of method is impossible, but it will be appreciated by one of ordinary skill in the art that each embodiment can be done
Further combinations and permutations.Therefore, embodiment described herein is intended to fall into the protection domain of appended claims
Interior all such changes, modifications and variations.Additionally, the term with regard to using in description or claims " comprises ", should
The mode that contains of word is similar to term and " includes ", as being explained as link word in the claims just as " including, ".
Additionally, use any one term in the description of claims " or " be intended to represent " non-exclusionism or ".
Finally should be noted that: above example is only in order to illustrate that technical scheme is not intended to limit, although reference
The present invention has been described in detail by above-described embodiment, and those of ordinary skill in the field still can concrete to the present invention
Embodiment is modified or equivalent, and these are without departing from any amendment of spirit and scope of the invention or equivalent,
Within the claims of the present invention all awaited the reply in application.
Claims (10)
1. having a planar gate IGBT of separate type colelctor electrode, described planar gate IGBT includes substrate, the most successively
Front metal electrode, isolated oxide film and the planar gate being arranged on substrate, the p-well region between planar gate and substrate, from
Top to bottm being set in turn in N+ type doped region and P+ type doped region in p-well region, the back side N-type being set in turn in substrate back is low
Doped in concentrations profiled relief area and back side P+ collecting zone；It is characterized in that, P+ collecting zone is provided with employing dielectric filling overleaf
Back side groove, described back side depth of groove greater than, equal to or less than the thickness of back side P+ collecting zone, described dielectric is complete
Or being partially filled with in a groove, described dielectric has overlapping with P+ collecting zone, to avoid back metal electrode and n type material
Contact；
Described substrate is the n type single crystal silicon sheet substrate of Uniform Doped, and described n type single crystal silicon sheet substrate includes dividing the most successively
The substrate N-layer of cloth and substrate N+ layer.
2. planar gate IGBT as claimed in claim 1, it is characterised in that described dielectric fills part and back side groove
Form IGBT back side isolated oxide layer.
3. planar gate IGBT as claimed in claim 1, it is characterised in that described n type single crystal silicon sheet substrate includes:
A, electric field cut-off FS type substrate: generation type is the n type single crystal silicon sheet of Uniform Doped first to carry out substrate thinning to required
The substrate thickness wanted；Front uses oxidation and the mode growth protecting sacrifice layer of deposit, then uses ion implanting mode to carry out silicon
The N-type low concentration relief area at the sheet back side is doped；Use miscellaneous to N-type low concentration relief area of high temperature Long Time Thermal annealing way
Matter carries out activating and knot, forms N-type low concentration doping relief area；Eventually form terminal structure and active area structure cell；?
Injected by doping afterwards and form substrate back p-type conductivity modulation layer；
The 5e2 to 1e4 that high-dopant concentration is n type single crystal silicon sheet substrate concentration of described N-type low concentration doping relief area times；
B, non-break-through NPT type substrate: generation type is first to carry out terminal structure and the formation of active area source born of the same parents' structure；At IGBT
After device surface structure is formed, the n type single crystal silicon sheet carrying out Uniform Doped is thinned to required substrate thickness；Eventually form lining
The doping of bottom back side p-type conductivity modulation layer is injected.
4. planar gate IGBT as claimed in claim 1, it is characterised in that when n type single crystal silicon sheet substrate uses soft break-through SPT
When type or electric field cut-off FS type, described planar gate IGBT includes that the N-type low concentration being positioned at n type single crystal silicon sheet substrate back delays
Rush district；If n type single crystal silicon sheet substrate uses non-break-through NPT type, then need not N-type low concentration relief area.
5. the manufacture method of planar gate IGBT as according to any one of claim 1-4, it is characterised in that described side
Method comprises the steps:
(1) to n type single crystal silicon sheet substrate pre-treatment: the N impurity doping concentration of described n type single crystal silicon sheet substrate and thickness
The breakdown voltage different according to planar gate IGBT and forward conduction voltage drop is needed to select, and by acid, alkali, deionized water
Ultrasonic cleaning operation, carries out chemical treatment to n type single crystal silicon sheet substrate surface；
(2) N-type low concentration doping relief area is made: the n type single crystal silicon sheet substrate face of Uniform Doped is used oxidation or forms sediment
Long-pending mode growth protecting sacrifices film quality, uses ion implanting mode to carry out N-type low concentration doping at silicon chip back side and sends out relief area
Impurity generates, then carries out annealing process, carries out activation and the knot of ion, knot to the required degree of depth, forms N-type low dense
Degree removes front protecting sacrifice layer film quality behind doped buffer region, if needing N-type low when soft break-through SPT type or electric field cut-off FS type
Doped in concentrations profiled relief area, if substrate is non-break-through NPT type, need not N-type low concentration doping relief area；
(3) planar gate is made: the n type single crystal silicon sheet substrate of Uniform Doped is carried out the mode of high-temperature oxydation, at silicon chip table
Look unfamiliar long oxide-film, and use deposit mode growing polycrystalline silicon electrode, then carry out photoetching and etching forms planar gate；
(4) p-well region is made: the gate openings forming planar gate carries out p-type doping by injection mode, then carries out height
Temperature annealing, adulterate knot by p-type, forms the p-well region of IGBT active area；
(5) make N+ type doped region: deposit photoresist, by being lithographically formed mask, the polycrystalline opening of p-well region is used note
Enter mode and carry out N+ doping, form N+ type doped region；
(6) planar gate IGBT surface P+ type doped region is made: grow oxide-film by deposit mode, anti-carve formation many comprehensively
Brilliant sidewall protection structure, uses autoregistration ion implanting mode to carry out P+ doping, forms P+ type doped region；
(7) planar gate IGBT back side P+ collecting zone is made: if substrate uses soft break-through SPT type or electric field cut-off FS type,
The impurity using ion implanting mode to carry out P+ doped region at silicon chip back side generates, then carries out annealing process, carries out swashing of ion
Live and knot；If substrate uses non-break-through NPT type, before metal electrode structure, make back side P+ doped region the most overleaf；
(8) make chip back isolation oxidation Rotating fields: deposit photoresist, by being lithographically formed mask, etch P+ collecting zone,
Forming back side groove, depth of groove selects greater than, equal to or is less than the thickness of P+ collecting zone, uses deposit or evaporation mode raw
Long dielectric, fills groove, is filled up completely with or is partially filled with, and the lower surface of dielectric is to the distance of P+ collecting zone lower surface
In 0 to 1 micrometer range, dielectric part must cover P+ collecting zone, it is to avoid backside collector metal contacts with n type material；
(9) front metal electrode is made: use chemical deposition mode to grow boron phosphorus doping glass film quality, carry out planar gate IGBT
Device isolation, the photoetching and the etching that carry out contact hole form isolation oxidation membrane structure, use physical deposition or evaporation mode growth aluminum
Alloy, carries out photoetching and the etching of metal, forms front metal electrode, completes planar gate IGBT front electrode and connects；
(10) back metal electrode is made: n type single crystal silicon sheet substrate is ground thinning or wet etching clean, use thing
Reason deposit or evaporation form back metal electrode, complete planar gate IGBT back side electrical characteristics and connect.
6. manufacture method as claimed in claim 5, it is characterised in that in described step (), planar gate IGBT is just
It is 600V to 6500V to conduction voltage drop.
7. manufacture method as claimed in claim 5, it is characterised in that in described step (two), the temperature of described annealing process
Degree is 1100 degree to 1150 degree, and the time is 600 minutes to 1800 minutes.
8. manufacture method as claimed in claim 5, it is characterised in that in described step (three), grow at silicon chip surface
Oxide-film be 0.1 to 0.2 micron.
9. manufacture method as claimed in claim 5, it is characterised in that in described step (four), be knot that p-type is adulterated
To 4 to 6 microns, form the p-well region of IGBT active area.
10. manufacture method as claimed in claim 5, it is characterised in that in described step (seven), ion is by knot to 0.5
To 1 micrometer range.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106680333A (en) * | 2017-02-13 | 2017-05-17 | 广州奥松电子有限公司 | Humidity sensitive capacitor and manufacturing method thereof |
| CN108493113A (en) * | 2018-03-30 | 2018-09-04 | 北京时代民芯科技有限公司 | A kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip |
| CN111326572A (en) * | 2020-02-17 | 2020-06-23 | 捷捷微电(上海)科技有限公司 | Back structure of semiconductor power device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005333055A (en) * | 2004-05-21 | 2005-12-02 | Toyota Central Res & Dev Lab Inc | Semiconductor apparatus |
| KR20100085508A (en) * | 2009-01-21 | 2010-07-29 | 용 서 구 | Trench insulated gate bipolar trangistor |
| CN102832240A (en) * | 2012-09-11 | 2012-12-19 | 电子科技大学 | Insulated gate bipolar transistor with dielectric layer at collector terminal |
| CN102856368A (en) * | 2012-09-27 | 2013-01-02 | 电子科技大学 | Power bipolar transistor and manufacture method thereof |
| CN103107189A (en) * | 2013-02-28 | 2013-05-15 | 江苏物联网研究发展中心 | IGBT back structure and preparation method |
| CN103378141A (en) * | 2012-04-25 | 2013-10-30 | 上海北车永电电子科技有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN103681817A (en) * | 2012-09-10 | 2014-03-26 | 中国科学院微电子研究所 | IGBT device and manufacturing method thereof |
| CN104393032A (en) * | 2014-12-04 | 2015-03-04 | 国家电网公司 | Plane gate insulated gate bipolar transistor (IGBT) and manufacturing method thereof |
-
2015
- 2015-05-15 CN CN201510249973.3A patent/CN106298897A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005333055A (en) * | 2004-05-21 | 2005-12-02 | Toyota Central Res & Dev Lab Inc | Semiconductor apparatus |
| KR20100085508A (en) * | 2009-01-21 | 2010-07-29 | 용 서 구 | Trench insulated gate bipolar trangistor |
| CN103378141A (en) * | 2012-04-25 | 2013-10-30 | 上海北车永电电子科技有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN103681817A (en) * | 2012-09-10 | 2014-03-26 | 中国科学院微电子研究所 | IGBT device and manufacturing method thereof |
| CN102832240A (en) * | 2012-09-11 | 2012-12-19 | 电子科技大学 | Insulated gate bipolar transistor with dielectric layer at collector terminal |
| CN102856368A (en) * | 2012-09-27 | 2013-01-02 | 电子科技大学 | Power bipolar transistor and manufacture method thereof |
| CN103107189A (en) * | 2013-02-28 | 2013-05-15 | 江苏物联网研究发展中心 | IGBT back structure and preparation method |
| CN104393032A (en) * | 2014-12-04 | 2015-03-04 | 国家电网公司 | Plane gate insulated gate bipolar transistor (IGBT) and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106680333A (en) * | 2017-02-13 | 2017-05-17 | 广州奥松电子有限公司 | Humidity sensitive capacitor and manufacturing method thereof |
| CN108493113A (en) * | 2018-03-30 | 2018-09-04 | 北京时代民芯科技有限公司 | A kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip |
| CN111326572A (en) * | 2020-02-17 | 2020-06-23 | 捷捷微电(上海)科技有限公司 | Back structure of semiconductor power device |
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